Commit Graph

11 Commits

Author SHA1 Message Date
Fangrui Song 5c29ffda90 Revert "[Driver][test] Replace ^//$ with empty string"
This reverts commit 4817b7729a.

It caused some `^/\n` and had some objection about its readability improvement.
2022-06-24 13:52:27 -07:00
Fangrui Song 4817b7729a [Driver][test] Replace ^//$ with empty string
The convention does not add //\n. Having all RUN/CHECK lines separated by //\n
makes editor movement difficult (e.g. { } in Vim).
2022-06-24 11:25:03 -07:00
Fangrui Song da62a5c661 [Driver][test] Clean up riscv* tests
See `D119309` for the guideline (-target, -no-canonical-prefixes, unneeded -o
with -###).
2022-03-25 23:59:31 -07:00
Alexander Pivovarov 4bc8dbe0ca [RISCV] Add SiFive cores E and S series
Add SiFive cores E20, E21, E24, E34, S21, S54 and S76

Differential Revision: https://reviews.llvm.org/D109260
2021-09-08 23:59:04 -07:00
Alexander Pivovarov 6cd4b508a8 [RISCV] Add SiFive core S51
Add SiFive core s51 as rv64imac RocketModel

Reviewed-By: MaskRay, evandro
Differential Revision: https://reviews.llvm.org/D108886
2021-09-02 18:45:25 -07:00
Kito Cheng cfa7094e49 [RISCV] Add -mtune support
- The goal of this patch is improve option compatible with RISCV-V GCC,
   -mcpu support on GCC side will sent patch in next few days.

 - -mtune only affect the pipeline model and non-arch/extension related
   target feature, e.g. instruction fusion; in td file it called
   TuneFeatures, which is introduced by X86 back-end[1].

 - -mtune accept all valid option for -mcpu and extra alias processor
   option, e.g. `generic`, `rocket` and `sifive-7-series`, the purpose is
   option compatible with RISCV-V GCC.

 - Processor alias for -mtune will resolve according the current target arch,
   rv32 or rv64, e.g. `rocket` will resolve to `rocket-rv32` or `rocket-rv64`.

 - Interaction between -mcpu and -mtune:
   * -mtune has higher priority than -mcpu for pipeline model and
     TuneFeatures.

[1] https://reviews.llvm.org/D85165

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D89025
2020-10-16 13:55:08 +08:00
Evandro Menezes a48d480e1f [RISCV] Fix broken test
Fix test for the SiFive E76 core.

This patch fixes the issue introduced by the commit 5d6d8a2769.
2020-10-05 19:28:31 -05:00
Evandro Menezes 5d6d8a2769 [RISCV] Add SiFive cores to the CPU option
Add the SiFive cores E76 and U74 using the SiFive 7 series microarchitecture.

Differential Revision: https://reviews.llvm.org/D88759
2020-10-05 15:50:57 -05:00
Evandro Menezes a0a8f83718 [PATCH] Fix typo (NFC) 2020-10-02 21:19:14 -05:00
Evandro Menezes a000580a89 [RISCV] Update driver tests
Add the RISC-V Bullet core to the driver tests.
2020-09-25 18:36:53 -05:00
Zakk Chen 294d1eae75 [RISCV] Add support for -mcpu option.
Summary:
1. gcc uses `-march` and `-mtune` flag to chose arch and
pipeline model, but clang does not have `-mtune` flag,
we uses `-mcpu` to chose both infos.
2. Add SiFive e31 and u54 cpu which have default march
and pipeline model.
3. Specific `-mcpu` with rocket-rv[32|64] would select
pipeline model only, and use the driver's arch choosing
logic to get default arch.

Reviewers: lenary, asb, evandro, HsiangKai

Reviewed By: lenary, asb, evandro

Tags: #llvm, #clang

Differential Revision: https://reviews.llvm.org/D71124
2020-07-16 11:46:22 -07:00