Commit Graph

3242 Commits

Author SHA1 Message Date
Artem Belevich 24e8a680e5 [NVPTX, CUDA] Improved feature constraints on NVPTX target builtins.
When NVPTX TARGET_BUILTIN specifies sm_XX or ptxYY as required feature,
consider those features available if we're compiling for GPU >= sm_XX or have
enabled PTX version >= ptxYY.

Differential Revision: https://reviews.llvm.org/D45061

llvm-svn: 329829
2018-04-11 17:51:19 +00:00
Yonghong Song 2ad75f7410 bpf: accept all asm register names
Sometimes when people compile bpf programs with
"clang ... -target bpf ...", the kernel header
files may contain host arch inline assembly codes
as in the patch https://patchwork.kernel.org/patch/10119683/
by Arnaldo Carvaldo de Melo.

The current workaround in the above patch
is to guard the inline assembly with "#ifndef __BPF__"
marco. So when __BPF__ is defined, these macros will
have no use.

Such a method is not extensible. As a matter of fact,
most of these inline assembly codes will be thrown away
at the end of clang compilation.

So for bpf target, this patch accepts all asm register
names in clang AST stage. The name will be checked
again during llc code generation if the inline assembly
code is indeed for bpf programs.

With this patch, the above "#ifndef __BPF__" is not needed
any more in https://patchwork.kernel.org/patch/10119683/.

Signed-off-by: Yonghong Song <yhs@fb.com>
llvm-svn: 329823
2018-04-11 16:08:00 +00:00
Gabor Buella 8701b18a25 [X86] Split up -march=icelake to -client & -server
Reviewers: craig.topper, zvi, echristo

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45056

llvm-svn: 329741
2018-04-10 18:58:26 +00:00
Nico Weber a3e7510a4c Attempt to fix Windows build after r329698.
llvm-svn: 329702
2018-04-10 14:08:25 +00:00
Gabor Buella e3330c1b61 [X86] Disable SGX for Skylake Server
Reviewers: craig.topper, zvi, echristo

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45058

llvm-svn: 329701
2018-04-10 14:04:21 +00:00
Nico Weber 148c8cb4bf Use llvm::sys::fs::real_path() in clang.
No expected behavior change.
https://reviews.llvm.org/D45165

llvm-svn: 329698
2018-04-10 13:36:38 +00:00
Yaxun Liu bec8a66454 [CUDA] Revert defining __CUDA_ARCH__ for amdgcn targets
amdgcn targets only support HIP, which does not define __CUDA_ARCH__.

this is a partial unroll of r329232 / D45277.

Differential Revision: https://reviews.llvm.org/D45387

llvm-svn: 329584
2018-04-09 15:43:01 +00:00
Dean Michael Berris 20dc6ef746 [XRay][llvm+clang] Consolidate attribute list files
Summary:
This change consolidates the always/never lists that may be provided to
clang to externally control which functions should be XRay instrumented
by imbuing attributes. The files follow the same format as defined in
https://clang.llvm.org/docs/SanitizerSpecialCaseList.html for the
sanitizer blacklist.

We also deprecate the existing `-fxray-instrument-always=` and
`-fxray-instrument-never=` flags, in favour of `-fxray-attr-list=`.

This fixes http://llvm.org/PR34721.

Reviewers: echristo, vlad.tsyrklevich, eugenis

Reviewed By: vlad.tsyrklevich

Subscribers: llvm-commits, cfe-commits

Differential Revision: https://reviews.llvm.org/D45357

llvm-svn: 329543
2018-04-09 04:02:09 +00:00
Yaxun Liu 8391387f7b [HIP] define __CUDA_ARCH_=1 for amdgcn targets
Differential Revision: https://reviews.llvm.org/D45277

llvm-svn: 329420
2018-04-06 16:43:42 +00:00
Alexander Kornienko 2a8c18d991 Fix typos in clang
Found via codespell -q 3 -I ../clang-whitelist.txt
Where whitelist consists of:

  archtype
  cas
  classs
  checkk
  compres
  definit
  frome
  iff
  inteval
  ith
  lod
  methode
  nd
  optin
  ot
  pres
  statics
  te
  thru

Patch by luzpaz! (This is a subset of D44188 that applies cleanly with a few
files that have dubious fixes reverted.)

Differential revision: https://reviews.llvm.org/D44188

llvm-svn: 329399
2018-04-06 15:14:32 +00:00
Shiva Chen 4891dbf557 [PATCH] [RISCV] Extend getTargetDefines for RISCVTargetInfo
Summary:
This patch extend getTargetDefines and implement handleTargetFeatures
and hasFeature. and define corresponding marco for those features.

Reviewers: asb, apazos, eli.friedman

Differential Revision: https://reviews.llvm.org/D44727

Patch by Kito Cheng.

llvm-svn: 329278
2018-04-05 12:54:00 +00:00
Yaxun Liu 8a5fc15aa4 [CUDA] Add amdgpu sub archs
Patch by Greg Rodgers.
Revised and lit tests added by Yaxun Liu.

Differential Revision: https://reviews.llvm.org/D45277

llvm-svn: 329232
2018-04-04 21:19:27 +00:00
Max Moroz e097567006 Fixes errors with FS iterators caused by https://reviews.llvm.org/D44960
Summary:
In https://reviews.llvm.org/D44960, file status check is executed every
time a real file system directory iterator is constructed or
incremented, and emits an error code. This change list fixes the errors
in VirtualFileSystem caused by https://reviews.llvm.org/D44960.

Patch by Yuke Liao (@liaoyuke).

Reviewers: vsk, pcc, zturner, liaoyuke

Reviewed By: vsk

Subscribers: mgrang, cfe-commits

Differential Revision: https://reviews.llvm.org/D45178

llvm-svn: 329223
2018-04-04 19:47:25 +00:00
Krzysztof Parzyszek 3163610010 [Hexagon] Remove -mhvx-double and the corresponding subtarget feature
Specifying the HVX vector length should be done via the -mhvx-length
option.

llvm-svn: 329077
2018-04-03 15:59:10 +00:00
Saleem Abdulrasool 13aeee0d36 CodeGenCXX: support PreserveMostCC in MS ABI
Microsoft has reserved 'U' for the PreserveMostCC which is used in the
swift runtime.  Add support for this.  This allows the swift runtime to
be built for Windows again.

llvm-svn: 329025
2018-04-02 22:25:50 +00:00
Manoj Gupta cb668d8512 [AArch64]: Add support for parsing rN registers.
Summary:
Allow rN registers to be simply parsed as correspoing xN registers.
The "register ... asm("rN")" is an command to the
compiler's register allocator, not an operand to any individual assembly
instruction. GCC documents this syntax as "...the name of the register
that should be used."

This is needed to support the changes in Linux kernel (see
https://lkml.org/lkml/2018/3/1/268 )

Note: This will add support only for the limited use case of
register ... asm("rN"). Any other uses that make rN leak into assembly
are not supported.

Reviewers: kristof.beyls, rengolin, peter.smith, t.p.northover

Reviewed By: peter.smith

Subscribers: javed.absar, eraman, cfe-commits, srhines

Differential Revision: https://reviews.llvm.org/D44815

llvm-svn: 328829
2018-03-29 21:11:15 +00:00
Eugene Zelenko 5a52011c41 [Basic] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 328735
2018-03-28 22:09:09 +00:00
Akira Hatanaka fcbe17c6be [ObjC++] Make parameter passing and function return compatible with ObjC
ObjC and ObjC++ pass non-trivial structs in a way that is incompatible
with each other. For example:
    
typedef struct {
  id f0;
  __weak id f1;
} S;
    
// this code is compiled in c++.
extern "C" {
  void foo(S s);
}
    
void caller() {
  // the caller passes the parameter indirectly and destructs it.
  foo(S());
}
    
// this function is compiled in c.
// 'a' is passed directly and is destructed in the callee.
void foo(S a) {
}
    
This patch fixes the incompatibility by passing and returning structs
with __strong or weak fields using the C ABI in C++ mode. __strong and
__weak fields in a struct do not cause the struct to be destructed in
the caller and __strong fields do not cause the struct to be passed
indirectly.
    
Also, this patch fixes the microsoft ABI bug mentioned here:
    
https://reviews.llvm.org/D41039?id=128767#inline-364710
    
rdar://problem/38887866
    
Differential Revision: https://reviews.llvm.org/D44908

llvm-svn: 328731
2018-03-28 21:13:14 +00:00
Matt Arsenault b130ea5605 AMDGPU: Update datalayout for stack alignment
llvm-svn: 328657
2018-03-27 19:26:51 +00:00
Mandeep Singh Grang c205d8cc8d [clang] Change std::sort to llvm::sort in response to r327219
r327219 added wrappers to std::sort which randomly shuffle the container before
sorting.  This will help in uncovering non-determinism caused due to undefined
sorting order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of
std::sort.

llvm-svn: 328636
2018-03-27 16:50:00 +00:00
Yaxun Liu ac1263cd54 [AMDGPU] Fix codegen for inline assembly
Need to override convertConstraint to recognise amdgpu specific register names.

Differential Revision: https://reviews.llvm.org/D44533

llvm-svn: 328359
2018-03-23 19:43:42 +00:00
Saleem Abdulrasool 29149d5cb7 Basic: support PreserveMost and PreserveAll on Windows ARM
Do not ignore these calling conventions on Windows ARM.  They are used
by the swift runtime for certain calls.

llvm-svn: 328007
2018-03-20 17:33:26 +00:00
Sjoerd Meijer 87793e7599 [ARM] Pass half or i16 types for NEON intrinsics
For generating NEON intrinsics, this determines the NEON data type, and whether
it should be a half type or an i16 type. I.e., we always pass a half type for
AArch64, this hasn't changed, but now also for ARM but only when FullFP16 is
enabled, and i16 otherwise.

This is intended to be non-functional change, but together with the backend
work in D44538 which adds support for f16 vectors, this enables adding the
AArch32 FP16 (vector) intrinsics.

Differential Revision: https://reviews.llvm.org/D44561

llvm-svn: 327836
2018-03-19 13:22:49 +00:00
Sjoerd Meijer a7463df6e2 [ARM] ACLE FP16 feature test macros
This is a partial recommit of r327189 that was reverted
due to test issues. I.e., this recommits minimal functional
change, the FP16 feature test macros, and adds tests that 
were missing in the original commit.

llvm-svn: 327455
2018-03-13 22:11:06 +00:00
Sjoerd Meijer 95da875898 This reverts "r327189 - [ARM] Add ARMv8.2-A FP16 vector intrinsic"
This is causing problems in testing, and PR36683 was raised.
Reverting it until we have sorted out how to pass f16 vectors.

llvm-svn: 327437
2018-03-13 19:38:56 +00:00
Abderrazek Zaafrani 5bd68cf742 [ARM] Add ARMv8.2-A FP16 vector intrinsic
Add the fp16 neon vector intrinsic for ARM as described in the ARM ACLE document.

Reviews in https://reviews.llvm.org/D43650

llvm-svn: 327189
2018-03-09 23:39:34 +00:00
Matthew Voss 0a6a701f36 Correct the alignment for the PS4 target
https://reviews.llvm.org/D44218

llvm-svn: 326942
2018-03-07 20:48:16 +00:00
Yaxun Liu 1578a0a55d [AMDGPU] Clean up old address space mapping and fix constant address space value
Differential Revision: https://reviews.llvm.org/D43911

llvm-svn: 326725
2018-03-05 17:50:10 +00:00
Heejin Ahn 8b6af22e60 [WebAssembly] Add exception handling option
Summary: Add exception handling option to clang.

Reviewers: dschuff

Subscribers: jfb, sbc100, jgravelle-google, sunfish, cfe-commits

Differential Revision: https://reviews.llvm.org/D43681

llvm-svn: 326517
2018-03-02 00:39:16 +00:00
Konstantin Zhuravlyov d6b3453bdb AMDGPU: Define FP_FAST_FMA{F} macros for amdgcn
- Expand GK_*s (i.e. GFX6 -> GFX600, GFX601, etc.)
  - This allows us to choose features correctly in some cases (for example, fast fmaf is available on gfx600, but not gfx601)
- Move HasFMAF, HasFP64, HasLDEXPF to GPUInfo tables
- Add HasFastFMA, HasFastFMAF to GPUInfo tables
- Add missing tests

llvm-svn: 326254
2018-02-27 21:48:05 +00:00
David Zarzycki b0c752d3c1 Fix for LLVM r326109
llvm-svn: 326110
2018-02-26 18:42:30 +00:00
Mandeep Singh Grang ac24bb53bb [RISCV] Enable __int128_t and __uint128_t through clang flag
Summary:
If the flag -fforce-enable-int128 is passed, it will enable support for __int128_t and __uint128_t types.
This flag can then be used to build compiler-rt for RISCV32.

Reviewers: asb, kito-cheng, apazos, efriedma

Reviewed By: asb, efriedma

Subscribers: shiva0217, efriedma, jfb, dschuff, sdardis, sbc100, jgravelle-google, aheejin, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, cfe-commits

Differential Revision: https://reviews.llvm.org/D43105

llvm-svn: 326045
2018-02-25 03:58:23 +00:00
Yonghong Song 8b1e93b7d6 bpf: Hook target feature "alu32" with LLVM
LLVM has supported a new target feature "alu32" which could be enabled or
disabled by "-mattr=[+|-]alu32" when using llc.

This patch link Clang with it, so it could be also done by passing related
options to Clang, for example:

  -Xclang -target-feature -Xclang +alu32

Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
llvm-svn: 325996
2018-02-23 23:55:29 +00:00
Craig Topper 94a940d2b4 [X86] Disable CLWB in Cannon Lake
Cannon Lake does not support CLWB, therefore it
does not include all features listed under SKX.

Patch by Gabor Buella

Differential Revision: https://reviews.llvm.org/D43459

llvm-svn: 325655
2018-02-21 00:16:50 +00:00
Simon Dardis 0bc2d9b0c5 [mips] Spectre variant two mitigation for MIPSR2
This patch provides mitigation for CVE-2017-5715, Spectre variant two,
which affects the P5600 and P6600. It provides the option
-mindirect-jump=hazard, which instructs the LLVM backend to replace
indirect branches with their hazard barrier variants.

This option is accepted when targeting MIPS revision two or later.

The migitation strategy suggested by MIPS for these processors is to
use two hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard
barrier variants of the 'jalr' and 'jr' instructions respectively.

These instructions impede the execution of instruction stream until
architecturally defined hazards (changes to the instruction stream,
privileged registers which may affect execution) are cleared. These
instructions in MIPS' designs are not speculated past.

These instructions are used with the option -mindirect-jump=hazard
when branching indirectly and for indirect function calls.

These instructions are defined by the MIPS32R2 ISA, so this mitigation
method is not compatible with processors which implement an earlier
revision of the MIPS ISA.

Implementation note: I've opted to provide this as an
-mindirect-jump={hazard,...} style option in case alternative
mitigation methods are required for other implementations of the MIPS
ISA in future, e.g. retpoline style solutions.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D43487

llvm-svn: 325651
2018-02-21 00:05:05 +00:00
Dylan McKay 8ad69f2d1f [AVR] Set the program address space in the data layout
This is accompanied by r325481 in LLVM.

llvm-svn: 325483
2018-02-19 10:46:16 +00:00
Dimitry Andric 2e3f23bbcc [X86] Add 'sahf' CPU feature to frontend
Summary:
Make clang accept `-msahf` (and `-mno-sahf`) flags to activate the
`+sahf` feature for the backend, for bug 36028 (Incorrect use of
pushf/popf enables/disables interrupts on amd64 kernels).  This was
originally submitted in bug 36037 by Jonathan Looney
<jonlooney@gmail.com>.

As described there, GCC also uses `-msahf` for this feature, and the
backend already recognizes the `+sahf` feature. All that is needed is to
teach clang to pass this on to the backend.

The mapping of feature support onto CPUs may not be complete; rather, it
was chosen to match LLVM's idea of which CPUs support this feature (see
lib/Target/X86/X86.td).

I also updated the affected test case (CodeGen/attr-target-x86.c) to
match the emitted output.

Reviewers: craig.topper, coby, efriedma, rsmith

Reviewed By: craig.topper

Subscribers: emaste, cfe-commits

Differential Revision: https://reviews.llvm.org/D43394

llvm-svn: 325446
2018-02-17 21:04:35 +00:00
Eugene Zelenko 25cae5a21f [Basic] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 325412
2018-02-16 23:40:07 +00:00
Konstantin Zhuravlyov cf71761495 Reapply r325193
llvm-svn: 325203
2018-02-15 02:37:04 +00:00
Konstantin Zhuravlyov b7b86127f5 Revert r325193 as it breaks buildbots
llvm-svn: 325200
2018-02-15 02:27:45 +00:00
Richard Smith 47c9b5d4d6 Add missing definition for class static after r325193.
llvm-svn: 325195
2018-02-15 01:01:06 +00:00
Konstantin Zhuravlyov 5c9d4e7957 AMDGPU: Cleanup most of the macros
- Insert __AMD__ macro
- Insert __AMDGPU__ macro
- Insert __devicename__ macro
- Add missing tests for arch macros

Differential Revision: https://reviews.llvm.org/D36802

llvm-svn: 325193
2018-02-15 00:20:26 +00:00
Bruno Cardoso Lopes 6d9cf8aa9d [Modules] Add more language features to be used with requires-declaration
Features added: c99, c11, c17, cplusplus14 and cplusplus17.

rdar://problem/36328787
rdar://problem/36668431

llvm-svn: 325154
2018-02-14 19:01:03 +00:00
Yaxun Liu 651bd73c02 [AMDGPU] Change constant addr space to 4
Differential Revision: https://reviews.llvm.org/D43171

llvm-svn: 325031
2018-02-13 18:01:21 +00:00
George Karpenkov 441e8fdf94 [NFC] Extract method to SourceManager for traversing the macro "stack"
The code for going up the macro arg expansion is duplicated in many
places (and we need it for the analyzer as well, so I did not want to
duplicate it two more times).

This patch is an NFC, so the semantics should remain the same.

Differential Revision: https://reviews.llvm.org/D42458

llvm-svn: 324780
2018-02-09 23:30:07 +00:00
Matt Arsenault e7da136a74 AMDGPU: Update for datalayout change
llvm-svn: 324748
2018-02-09 16:58:41 +00:00
Konstantin Zhuravlyov 76854e7daa AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
- Remove gfx800
- Remove gfx804
- Remove gfx901
- Remove gfx903

Differential Revision: https://reviews.llvm.org/D40045

llvm-svn: 324714
2018-02-09 07:02:28 +00:00
Richard Smith 6c2b5a8ff0 [modules] Fix incorrect diagnostic mapping computation when a module changes
diagnostic settings using _Pragma within a macro.

The AST writer had previously been assuming that all diagnostic state
transitions would occur within a FileID corresponding to a file. When a
diagnostic state change occured within a macro, it was unable to form a
location for that state change and would instead corrupt the diagnostic state
of the "root" node (and thus that of the main compilation).

Also introduce a "#pragma clang __debug diag_mapping" debugging utility
that I added to track this issue down.

llvm-svn: 324695
2018-02-09 01:15:13 +00:00
Erich Keane fa69c71dce Fix UBSan issue with PPC::isValidCPUName
Apparently storing the pointer to a StringLiteral as
a StringRef caused this section of code to issue a ubsan
warning.  This will hopefully fix that.

llvm-svn: 324687
2018-02-09 00:13:49 +00:00
Erich Keane 086331b4ff Add size to constexpr Arrays
What seems to be a bug in older versions of MSVC, constexpr
member arrays with a redefinition (to force emission) require
their initial definition to have the size between the brackets.

llvm-svn: 324682
2018-02-08 23:49:40 +00:00
Erich Keane e44bdb3f70 Add Rest of Targets Support to ValidCPUList (enabling march notes)
A followup to: https://reviews.llvm.org/D42978

Most of the rest of the Targets were pretty rote, so this
patch knocks them all out at once. 

Differential Revision: https://reviews.llvm.org/D43057

llvm-svn: 324676
2018-02-08 23:16:55 +00:00
Erich Keane d45879d8ad Add NVPTX Support to ValidCPUList (enabling march notes)
A followup to: https://reviews.llvm.org/D42978
This patch adds NVPTX support for
enabling the march notes.

Differential Revision: https://reviews.llvm.org/D43045

llvm-svn: 324675
2018-02-08 23:16:00 +00:00
Erich Keane d1d85f50d0 Add X86 Support to ValidCPUList (enabling march notes)
A followup to: https://reviews.llvm.org/D42978
This patch adds X86 and X86_64 support for
enabling the march notes.

Differential Revision: https://reviews.llvm.org/D43041

llvm-svn: 324674
2018-02-08 23:15:02 +00:00
Erich Keane 3ec1743d0d Make march/target-cpu print a note with the list of valid values for ARM
When rejecting a march= or target-cpu command line parameter,
the message is quite lacking. This patch adds a note that prints
all possible values for the current target, if the target supports it.

This adds support for the ARM/AArch64 targets (more to come!). 

Differential Revision: https://reviews.llvm.org/D42978 

llvm-svn: 324673
2018-02-08 23:14:15 +00:00
Erich Keane 9176f669b4 [NFCi] Replace a couple of usages of const StringRef& with StringRef
No sense passing these by reference when a copy is about as free, and
saves on potential indirection later.

llvm-svn: 324540
2018-02-07 23:04:38 +00:00
Walter Lee 637aafc451 [Myriad] Define __ma2x5x and __ma2x8x
Summary: Add architecture defines for ma2x5x and ma2x8x.

Reviewers: jyknight

Subscribers: fedor.sergeev, MartinO

Differential Revision: https://reviews.llvm.org/D42882

llvm-svn: 324420
2018-02-06 22:39:47 +00:00
Alex Bradbury 3e1478f866 [RISCV] Create a LinuxTargetInfo when targeting Linux
Previously, RISCV32TargetInfo or RISCV64TargetInfo were created 
unconditionally. Use LinuxTargetInfo<RISCV??TargetInfo> to ensure that the 
proper OS-specific defines are present.

This patch only adds logic to instantiate LinuxTargetInfo and leaves a TODO, 
as I'm reluctant to add logic for other targets (e.g. FreeBSD, RTEMS) until 
I've produced and tested at least one binary for that OS+target combo.

Thanks to @mgrang to reporting the issue.

llvm-svn: 324170
2018-02-03 11:56:11 +00:00
Yaxun Liu f5f45e5e63 [AMDGPU] Switch to the new addr space mapping by default
This requires corresponding llvm change.

Differential Revision: https://reviews.llvm.org/D40956

llvm-svn: 324102
2018-02-02 16:08:24 +00:00
Artem Belevich fbc56a904f [CUDA] Added partial support for CUDA-9.1
Clang can use CUDA-9.1 now, though new APIs (are not implemented yet.

The major change is that headers in CUDA-9.1 went through substantial
changes that started in CUDA-9.0 which required substantial changes
in the cuda compatibility headers provided by clang.

There are two major issues:
* CUDA SDK no longer provides declarations for libdevice functions.
* A lot of device-side functions have become nvcc's builtins and
  CUDA headers no longer contain their implementations.

This patch changes the way CUDA headers are handled if we compile
with CUDA 9.x. Both 9.0 and 9.1 are affected.

* Clang provides its own declarations of libdevice functions.
* For CUDA-9.x clang now provides implementation of device-side
  'standard library' functions using libdevice.

This patch should not affect compilation with CUDA-8. There may be
some observable differences for CUDA-9.0, though they are not expected
to affect functionality.

Tested: CUDA test-suite tests for all supported combinations of:
        CUDA: 7.0,7.5,8.0,9.0,9.1
        GPU: sm_20, sm_35, sm_60, sm_70

Differential Revision: https://reviews.llvm.org/D42513

llvm-svn: 323713
2018-01-30 00:00:12 +00:00
Craig Topper ace5c37c57 [X86] Add 'rdrnd' feature to silvermont to match recent gcc bug fix.
gcc recently fixed this bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83546

llvm-svn: 323552
2018-01-26 19:34:45 +00:00
Craig Topper 3672f00e01 [X86] Define __IBT__ when -mibt is specified.
llvm-svn: 323543
2018-01-26 18:31:14 +00:00
Wei Mi d1621699dc Adjust MaxAtomicInlineWidth for i386/i486 targets.
This is to fix the bug reported in https://bugs.llvm.org/show_bug.cgi?id=34347#c6.
Currently, all  MaxAtomicInlineWidth of x86-32 targets are set to 64. However,
i386 doesn't support any cmpxchg related instructions. i486 only supports cmpxchg.
So in this patch MaxAtomicInlineWidth is reset as follows:
For i386, the MaxAtomicInlineWidth should be 0 because no cmpxchg is supported.
For i486, the MaxAtomicInlineWidth should be 32 because it supports cmpxchg.
For others 32 bits x86 cpu, the MaxAtomicInlineWidth should be 64 because of cmpxchg8b.

Differential Revision: https://reviews.llvm.org/D42154

llvm-svn: 323281
2018-01-23 23:27:57 +00:00
Dan Gohman 59f16991b0 [WebAssembly] Factor out settings common to wasm32 and wasm64. NFC.
MaxAtomicPromoteWidth and MaxAtomicInlineWidth are 64 on both
wasm32 and wasm64, so they can be set in shared code.

llvm-svn: 323253
2018-01-23 20:22:12 +00:00
Chandler Carruth c58f2166ab Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre..
Summary:
First, we need to explain the core of the vulnerability. Note that this
is a very incomplete description, please see the Project Zero blog post
for details:
https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html

The basis for branch target injection is to direct speculative execution
of the processor to some "gadget" of executable code by poisoning the
prediction of indirect branches with the address of that gadget. The
gadget in turn contains an operation that provides a side channel for
reading data. Most commonly, this will look like a load of secret data
followed by a branch on the loaded value and then a load of some
predictable cache line. The attacker then uses timing of the processors
cache to determine which direction the branch took *in the speculative
execution*, and in turn what one bit of the loaded value was. Due to the
nature of these timing side channels and the branch predictor on Intel
processors, this allows an attacker to leak data only accessible to
a privileged domain (like the kernel) back into an unprivileged domain.

The goal is simple: avoid generating code which contains an indirect
branch that could have its prediction poisoned by an attacker. In many
cases, the compiler can simply use directed conditional branches and
a small search tree. LLVM already has support for lowering switches in
this way and the first step of this patch is to disable jump-table
lowering of switches and introduce a pass to rewrite explicit indirectbr
sequences into a switch over integers.

However, there is no fully general alternative to indirect calls. We
introduce a new construct we call a "retpoline" to implement indirect
calls in a non-speculatable way. It can be thought of loosely as
a trampoline for indirect calls which uses the RET instruction on x86.
Further, we arrange for a specific call->ret sequence which ensures the
processor predicts the return to go to a controlled, known location. The
retpoline then "smashes" the return address pushed onto the stack by the
call with the desired target of the original indirect call. The result
is a predicted return to the next instruction after a call (which can be
used to trap speculative execution within an infinite loop) and an
actual indirect branch to an arbitrary address.

On 64-bit x86 ABIs, this is especially easily done in the compiler by
using a guaranteed scratch register to pass the target into this device.
For 32-bit ABIs there isn't a guaranteed scratch register and so several
different retpoline variants are introduced to use a scratch register if
one is available in the calling convention and to otherwise use direct
stack push/pop sequences to pass the target address.

This "retpoline" mitigation is fully described in the following blog
post: https://support.google.com/faqs/answer/7625886

We also support a target feature that disables emission of the retpoline
thunk by the compiler to allow for custom thunks if users want them.
These are particularly useful in environments like kernels that
routinely do hot-patching on boot and want to hot-patch their thunk to
different code sequences. They can write this custom thunk and use
`-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this
case, on x86-64 thu thunk names must be:
```
  __llvm_external_retpoline_r11
```
or on 32-bit:
```
  __llvm_external_retpoline_eax
  __llvm_external_retpoline_ecx
  __llvm_external_retpoline_edx
  __llvm_external_retpoline_push
```
And the target of the retpoline is passed in the named register, or in
the case of the `push` suffix on the top of the stack via a `pushl`
instruction.

There is one other important source of indirect branches in x86 ELF
binaries: the PLT. These patches also include support for LLD to
generate PLT entries that perform a retpoline-style indirection.

The only other indirect branches remaining that we are aware of are from
precompiled runtimes (such as crt0.o and similar). The ones we have
found are not really attackable, and so we have not focused on them
here, but eventually these runtimes should also be replicated for
retpoline-ed configurations for completeness.

For kernels or other freestanding or fully static executables, the
compiler switch `-mretpoline` is sufficient to fully mitigate this
particular attack. For dynamic executables, you must compile *all*
libraries with `-mretpoline` and additionally link the dynamic
executable and all shared libraries with LLD and pass `-z retpolineplt`
(or use similar functionality from some other linker). We strongly
recommend also using `-z now` as non-lazy binding allows the
retpoline-mitigated PLT to be substantially smaller.

When manually apply similar transformations to `-mretpoline` to the
Linux kernel we observed very small performance hits to applications
running typical workloads, and relatively minor hits (approximately 2%)
even for extremely syscall-heavy applications. This is largely due to
the small number of indirect branches that occur in performance
sensitive paths of the kernel.

When using these patches on statically linked applications, especially
C++ applications, you should expect to see a much more dramatic
performance hit. For microbenchmarks that are switch, indirect-, or
virtual-call heavy we have seen overheads ranging from 10% to 50%.

However, real-world workloads exhibit substantially lower performance
impact. Notably, techniques such as PGO and ThinLTO dramatically reduce
the impact of hot indirect calls (by speculatively promoting them to
direct calls) and allow optimized search trees to be used to lower
switches. If you need to deploy these techniques in C++ applications, we
*strongly* recommend that you ensure all hot call targets are statically
linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well
tuned servers using all of these techniques saw 5% - 10% overhead from
the use of retpoline.

We will add detailed documentation covering these components in
subsequent patches, but wanted to make the core functionality available
as soon as possible. Happy for more code review, but we'd really like to
get these patches landed and backported ASAP for obvious reasons. We're
planning to backport this to both 6.0 and 5.0 release streams and get
a 5.0 release with just this cherry picked ASAP for distros and vendors.

This patch is the work of a number of people over the past month: Eric, Reid,
Rui, and myself. I'm mailing it out as a single commit due to the time
sensitive nature of landing this and the need to backport it. Huge thanks to
everyone who helped out here, and everyone at Intel who helped out in
discussions about how to craft this. Also, credit goes to Paul Turner (at
Google, but not an LLVM contributor) for much of the underlying retpoline
design.

Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer

Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D41723

llvm-svn: 323155
2018-01-22 22:05:25 +00:00
Craig Topper 8cdb94901d [X86] Add rdpid command line option and intrinsics.
Summary: This patch adds -mrdpid/-mno-rdpid and the rdpid intrinsic. The corresponding LLVM commit has already been made.

Reviewers: RKSimon, spatel, zvi, AndreiGrischenko

Reviewed By: RKSimon

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D42272

llvm-svn: 323047
2018-01-20 18:36:52 +00:00
Craig Topper 035bf77426 [X86] Put the code that defines __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 for the preprocessor with the other __GCC_HAVE_SYNC_COMPARE_AND_SWAP_* defines. NFC
llvm-svn: 323046
2018-01-20 18:36:06 +00:00
Abderrazek Zaafrani ce8746d178 [AArch64] Add ARMv8.2-A FP16 scalar intrinsics
https://reviews.llvm.org/D41792

llvm-svn: 323006
2018-01-19 23:11:18 +00:00
Dan Gohman d0c4e1e9fc [WebAssembly] Add target flags for sign-ext opcodes.
Add -msign-ext and -mno-sign-ext to control the new sign-ext target
feature.

llvm-svn: 322967
2018-01-19 17:16:32 +00:00
Nico Weber 8321ad9ffc Make DiagnosticsEngine() take DiagOpts as DiagnosticsEngine.
No behavior change, but makes it a bit clearer that DiagnosticsEngine adds a
ref to DiagOpts.

llvm-svn: 322611
2018-01-17 02:55:27 +00:00
Ulrich Weigand e1d2d22d2a [SystemZ] Support vector registers with inline asm
Allow using vector register names and the "v" constraint
in inline asm to ensure compatibility with GCC.

llvm-svn: 322562
2018-01-16 15:39:23 +00:00
Alexey Bataev 647dd84422 [OPENMP] Initial codegen for `target teams distribute parallel for
simd`.

Added host codegen + codegen for devices with default codegen for
`#pragma omp target teams distribute parallel for simd` directive.

llvm-svn: 322515
2018-01-15 20:59:40 +00:00
Alexey Bataev 8451efad89 [OPENMP] Add codegen for `depend` clauses on `target` directive.
Added basic support for codegen of `depend` clauses on `target`
directive.

llvm-svn: 322501
2018-01-15 19:06:12 +00:00
Alex Bradbury 71f45455e1 [RISCV] Add the RISCV target and compiler driver
As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver 
support (RV64 to follow).

Differential Revision: https://reviews.llvm.org/D39963

llvm-svn: 322276
2018-01-11 13:36:56 +00:00
Craig Topper a1ef12a051 [X86] Make -mavx512f imply -mfma and -mf16c in the frontend like it does in the backend.
Similarly, make -mno-fma and -mno-f16c imply -mno-avx512f.

Withou this  "-mno-sse -mavx512f" ends up with avx512f being enabled in the frontend but disabled in the backend.

llvm-svn: 322245
2018-01-11 01:37:59 +00:00
Oren Ben Simhon 57cc1a5d77 Added Control Flow Protection Flag
Cf-protection is a target independent flag that instructs the back-end to instrument control flow mechanisms like: Branch, Return, etc.
For example in X86 this flag will be used to instrument Indirect Branch Tracking instructions.

Differential Revision: https://reviews.llvm.org/D40478

Change-Id: I5126e766c0e6b84118cae0ee8a20fe78cc373dea
llvm-svn: 322063
2018-01-09 08:53:59 +00:00
Erich Keane 281d20b601 Implement Attribute Target MultiVersioning
GCC's attribute 'target', in addition to being an optimization hint,
also allows function multiversioning. We currently have the former
implemented, this is the latter's implementation.

This works by enabling functions with the same name/signature to coexist,
so that they can all be emitted. Multiversion state is stored in the
FunctionDecl itself, and SemaDecl manages the definitions.
Note that it ends up having to permit redefinition of functions so
that they can all be emitted. Additionally, all versions of the function
must be emitted, so this also manages that.

Note that this includes some additional rules that GCC does not, since
defining something as a MultiVersion function after a usage has been made illegal.

The only 'history rewriting' that happens is if a function is emitted before
it has been converted to a multiversion'ed function, at which point its name
needs to be changed.

Function templates and virtual functions are NOT yet supported (not supported
in GCC either).

Additionally, constructors/destructors are disallowed, but the former is 
planned.

llvm-svn: 322028
2018-01-08 21:34:17 +00:00
Volodymyr Sapsai 4ea49798a9 Fix TLS support check for Darwin 32-bit simulator targets.
Also instead of checking architecture explicitly, use recently added
"simulator" environment in the triple.

rdar://problem/35083787

Reviewers: arphaman, bob.wilson

Reviewed By: arphaman

Subscribers: gparker42, cfe-commits

Differential Revision: https://reviews.llvm.org/D41750

llvm-svn: 321890
2018-01-05 20:20:03 +00:00
Bruno Cardoso Lopes 8587dfd94b Reapply r321781: [Modules] Allow modules specified by -fmodule-map-file to shadow implicitly found ones
When modules come from module map files explicitly specified by
-fmodule-map-file= arguments, allow those to override/shadow modules
with the same name that are found implicitly by header search. If such a
module is looked up by name (e.g. @import), we will always find the one
from -fmodule-map-file. If we try to use a shadowed module by including
one of its headers report an error.

This enables developers to force use of a specific copy of their module
to be used if there are multiple copies that would otherwise be visible,
for example if they develop modules that are installed in the default
search paths.

Patch originally by Ben Langmuir,
http://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20151116/143425.html

Based on cfe-dev discussion:
http://lists.llvm.org/pipermail/cfe-dev/2015-November/046164.html

Differential Revision: https://reviews.llvm.org/D31269

rdar://problem/23612102

llvm-svn: 321855
2018-01-05 02:33:18 +00:00
Bruno Cardoso Lopes fec26b0bbb Revert "[Modules] Allow modules specified by -fmodule-map-file to shadow implicitly found ones"
This reverts r321781 until I fix the leaks pointed out by bots:

http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/12146
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/3741

llvm-svn: 321786
2018-01-04 07:31:24 +00:00
Bruno Cardoso Lopes b6ec4a33fb [Modules] Allow modules specified by -fmodule-map-file to shadow implicitly found ones
When modules come from module map files explicitly specified by
-fmodule-map-file= arguments, allow those to override/shadow modules
with the same name that are found implicitly by header search. If such a
module is looked up by name (e.g. @import), we will always find the one
from -fmodule-map-file. If we try to use a shadowed module by including
one of its headers report an error.

This enables developers to force use of a specific copy of their module
to be used if there are multiple copies that would otherwise be visible,
for example if they develop modules that are installed in the default
search paths.

Patch originally by Ben Langmuir,
http://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20151116/143425.html

Based on cfe-dev discussion:
http://lists.llvm.org/pipermail/cfe-dev/2015-November/046164.html

Differential Revision: https://reviews.llvm.org/D31269

rdar://problem/23612102

llvm-svn: 321781
2018-01-04 02:17:40 +00:00
Carlo Bertolli 52978c3554 [OpenMP] Initial implementation of code generation for pragma 'target teams distribute parallel for' on host
https://reviews.llvm.org/D41709

This patch includes code generation and testing for offloading when target device is host.

llvm-svn: 321759
2018-01-03 21:12:44 +00:00
Craig Topper d2fe244a6a Revert r321504 "[X86] Don't accidentally enable PKU on cannon lake and icelake or CLWB on cannonlake."
I based that commit on what was in Intel's public documentation here https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

Which specifically said CLWB wasn't until Icelake.

But I've since cross checked with SDE and it thinks these features exist on CNL and ICL. So now I don't know what to believe.

I've added test coverage of the current behavior as part of the revert so at least now have proof of what we're doing.

llvm-svn: 321547
2017-12-29 06:39:16 +00:00
Benjamin Kramer 3a13ed60ba Avoid int to string conversion in Twine or raw_ostream contexts.
Some output changes from uppercase hex to lowercase hex, no other functionality change intended.

llvm-svn: 321526
2017-12-28 16:58:54 +00:00
Craig Topper 520d055f66 [X86] Don't accidentally enable PKU on cannon lake and icelake or CLWB on cannonlake.
We have cannonlake and icelake inheriting from skylake server in a switch using fallthroughs. But they aren't perfect supersets of skylake server.

llvm-svn: 321504
2017-12-27 22:26:01 +00:00
Craig Topper b36447d346 [X86] Enable avx512vpopcntdq and clwb for icelake.
Per table 1-1 of the October 2017 edition of Intel® Architecture Instruction Set Extensions and Future Features Programming Reference

llvm-svn: 321502
2017-12-27 22:25:59 +00:00
Coby Tayree a09663a5c1 [x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557

llvm-svn: 321487
2017-12-27 11:25:07 +00:00
Coby Tayree 3d9c88cfec [x86][icelake][vnni]
added vnni feature recognition
added intrinsics support for VNNI instructions
_mm256_mask_dpbusd_epi32
_mm256_maskz_dpbusd_epi32
_mm256_dpbusd_epi32
_mm256_mask_dpbusds_epi32
_mm256_maskz_dpbusds_epi32
_mm256_dpbusds_epi32
_mm256_mask_dpwssd_epi32
_mm256_maskz_dpwssd_epi32
_mm256_dpwssd_epi32
_mm256_mask_dpwssds_epi32
_mm256_maskz_dpwssds_epi32
_mm256_dpwssds_epi32
_mm128_mask_dpbusd_epi32
_mm128_maskz_dpbusd_epi32
_mm128_dpbusd_epi32
_mm128_mask_dpbusds_epi32
_mm128_maskz_dpbusds_epi32
_mm128_dpbusds_epi32
_mm128_mask_dpwssd_epi32
_mm128_maskz_dpwssd_epi32
_mm128_dpwssd_epi32
_mm128_mask_dpwssds_epi32
_mm128_maskz_dpwssds_epi32
_mm128_dpwssds_epi32
_mm512_mask_dpbusd_epi32
_mm512_maskz_dpbusd_epi32
_mm512_dpbusd_epi32
_mm512_mask_dpbusds_epi32
_mm512_maskz_dpbusds_epi32
_mm512_dpbusds_epi32
_mm512_mask_dpwssd_epi32
_mm512_maskz_dpwssd_epi32
_mm512_dpwssd_epi32
_mm512_mask_dpwssds_epi32
_mm512_maskz_dpwssds_epi32
_mm512_dpwssds_epi32
matching a similar work on the backend (D40208)
Differential Revision: https://reviews.llvm.org/D41558

llvm-svn: 321484
2017-12-27 10:37:51 +00:00
Coby Tayree 2268576fa0 [x86][icelake][bitalg]
added bitalg feature recognition
added intrinsics support for bitalg instructions
_mm512_popcnt_epi16
_mm512_mask_popcnt_epi16
_mm512_maskz_popcnt_epi16
_mm512_popcnt_epi8
_mm512_mask_popcnt_epi8
_mm512_maskz_popcnt_epi8
_mm512_mask_bitshuffle_epi64_mask
_mm512_bitshuffle_epi64_mask
_mm256_popcnt_epi16
_mm256_mask_popcnt_epi16
_mm256_maskz_popcnt_epi16
_mm128_popcnt_epi16
_mm128_mask_popcnt_epi16
_mm128_maskz_popcnt_epi16
_mm256_popcnt_epi8
_mm256_mask_popcnt_epi8
_mm256_maskz_popcnt_epi8
_mm128_popcnt_epi8
_mm128_mask_popcnt_epi8
_mm128_maskz_popcnt_epi8
_mm256_mask_bitshuffle_epi32_mask
_mm256_bitshuffle_epi32_mask
_mm128_mask_bitshuffle_epi16_mask
_mm128_bitshuffle_epi16_mask
matching a similar work on the backend (D40222)
Differential Revision: https://reviews.llvm.org/D41564

llvm-svn: 321483
2017-12-27 10:01:00 +00:00
Coby Tayree cf96c876c6 [x86][icelake][vpclmulqdq]
added vpclmulqdq feature recognition
added intrinsics support for vpclmulqdq instructions
  _mm256_clmulepi64_epi128
  _mm512_clmulepi64_epi128
matching a similar work on the backend (D40101)
Differential Revision: https://reviews.llvm.org/D41573

llvm-svn: 321480
2017-12-27 09:00:31 +00:00
Coby Tayree f4811ebc39 [x86][icelake][gfni]
added gfni feature recognition
added intrinsics support for gfni instructions
  _mm_gf2p8affineinv_epi64_epi8
  _mm_mask_gf2p8affineinv_epi64_epi8
  _mm_maskz_gf2p8affineinv_epi64_epi8
  _mm256_gf2p8affineinv_epi64_epi8
  _mm256_mask_gf2p8affineinv_epi64_epi8
  _mm256_maskz_gf2p8affineinv_epi64_epi8
  _mm512_gf2p8affineinv_epi64_epi8
  _mm512_mask_gf2p8affineinv_epi64_epi8
  _mm512_maskz_gf2p8affineinv_epi64_epi8
  _mm_gf2p8affine_epi64_epi8
  _mm_mask_gf2p8affine_epi64_epi8
  _mm_maskz_gf2p8affine_epi64_epi8
  _mm256_gf2p8affine_epi64_epi8
  _mm256_mask_gf2p8affine_epi64_epi8
  _mm256_maskz_gf2p8affine_epi64_epi8
  _mm512_gf2p8affine_epi64_epi8
  _mm512_mask_gf2p8affine_epi64_epi8
  _mm512_maskz_gf2p8affine_epi64_epi8
  _mm_gf2p8mul_epi8
  _mm_mask_gf2p8mul_epi8
  _mm_maskz_gf2p8mul_epi8
  _mm256_gf2p8mul_epi8
  _mm256_mask_gf2p8mul_epi8
  _mm256_maskz_gf2p8mul_epi8
  _mm512_gf2p8mul_epi8
  _mm512_mask_gf2p8mul_epi8
  _mm512_maskz_gf2p8mul_epi8
matching a similar work on the backend (D40373)
Differential Revision: https://reviews.llvm.org/D41582

llvm-svn: 321477
2017-12-27 08:37:47 +00:00
Coby Tayree a1e5f0c339 [x86][icelake][vaes]
added vaes feature recognition
added intrinsics support for vaes instructions, matching a similar work on the backend (D40078)
  _mm256_aesenc_epi128
  _mm512_aesenc_epi128
  _mm256_aesenclast_epi128
  _mm512_aesenclast_epi128
  _mm256_aesdec_epi128
  _mm512_aesdec_epi128
  _mm256_aesdeclast_epi128
  _mm512_aesdeclast_epi128

llvm-svn: 321474
2017-12-27 08:16:54 +00:00
Craig Topper 66b110edce [X86] Add 'prfchw' to the correct CPUs to match the backend.
llvm-svn: 321341
2017-12-22 04:51:00 +00:00
Erich Keane e8192cc15f Correct hasFeature/isValidFeatureName's handling of shstk/adx/mwaitx
https://bugs.llvm.org/show_bug.cgi?id=35721 reports that x86intrin.h
is issuing a few warnings. This is because attribute target is using
isValidFeatureName for its source. It was also discovered that two of
these were missing from hasFeature.  

Additionally, shstk is and ibu are reordered alphabetically, as came
up during code review.

llvm-svn: 321324
2017-12-21 23:27:36 +00:00
Abderrazek Zaafrani f58a132eef [AARch64] Add ARMv8.2-A FP16 vector intrinsics
Putting back the code that was reverted few weeks ago.

Differential Revision: https://reviews.llvm.org/D34161

llvm-svn: 321294
2017-12-21 19:20:01 +00:00
Gabor Horvath 53b5c13b9d Make DiagnosticIDs::getAllDiagnostics use std::vector. NFC.
The size of the result vector is currently around 4600 with
Flavor::WarningOrError, which makes std::vector a better candidate than
llvm::SmallVector.

Patch by: Andras Leitereg!

Differential Revision: https://reviews.llvm.org/D39372

llvm-svn: 321190
2017-12-20 16:55:41 +00:00
Pavel Labath bf8519b5c9 Remove llvm::MemoryBuffer const_casts
Summary:
llvm has grown a WritableMemoryBuffer class, which is convertible
(inherits from) a MemoryBuffer. We can use it to avoid conts_casting the
buffer contents when we want to write to it.

Reviewers: dblaikie, rsmith

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D41387

llvm-svn: 321167
2017-12-20 11:34:38 +00:00
Richard Smith c70f1d63f8 [c++20] P0515R3: Parsing support and basic AST construction for operator <=>.
Adding the new enumerator forced a bunch more changes into this patch than I
would have liked. The -Wtautological-compare warning was extended to properly
check the new comparison operator, clang-format needed updating because it uses
precedence levels as weights for determining where to break lines (and several
operators increased their precedence levels with this change), thread-safety
analysis needed changes to build its own IL properly for the new operator.

All "real" semantic checking for this operator has been deferred to a future
patch. For now, we use the relational comparison rules and arbitrarily give
the builtin form of the operator a return type of 'void'.

llvm-svn: 320707
2017-12-14 15:16:18 +00:00
Alexey Bataev fbe17fb8a5 [OPENMP] Initial codegen for `target teams distribute simd` directive.
Host + generic device codegen for `target teams distribute simd`
directive.

llvm-svn: 320608
2017-12-13 19:45:06 +00:00
Krzysztof Parzyszek cc5cd2c013 [Hexagon] Add front-end support for Hexagon V65
llvm-svn: 320579
2017-12-13 13:48:07 +00:00
Aleksandar Beserminji 92985796dc [mips] Minor update to the comment (NFC)
llvm-svn: 320354
2017-12-11 12:12:16 +00:00
Aleksandar Beserminji 8ee5296152 [mips] Removal of microMIPS64R6
microMIPS64R6 is removed from backend, and therefore frontend
will show an error when target is microMIPS64R6.

This is Clang part of patch.

Differential Revision: https://reviews.llvm.org/D35624

llvm-svn: 320351
2017-12-11 11:29:17 +00:00
Akira Hatanaka 502775a2ee [CodeGen][X86] Fix handling of __fp16 vectors.
This commit fixes a bug in IRGen where it generates completely broken
code for __fp16 vectors on X86. For example when the following code is
compiled:

half4 hv0, hv1, hv2; // these are vectors of __fp16.

void foo221() {
  hv0 = hv1 + hv2;
}

clang generates the following IR, in which two i16 vectors are added:

@hv1 = common global <4 x i16> zeroinitializer, align 8
@hv2 = common global <4 x i16> zeroinitializer, align 8
@hv0 = common global <4 x i16> zeroinitializer, align 8

define void @foo221() {
  %0 = load <4 x i16>, <4 x i16>* @hv1, align 8
  %1 = load <4 x i16>, <4 x i16>* @hv2, align 8
  %add = add <4 x i16> %0, %1
  store <4 x i16> %add, <4 x i16>* @hv0, align 8
  ret void
}

To fix the bug, this commit uses the code committed in r314056, which
modified clang to promote and truncate __fp16 vectors to and from float
vectors in the AST. It also fixes another IRGen bug where a short value
is assigned to an __fp16 variable without any integer-to-floating-point
conversion, as shown in the following example:

__fp16 a;
short b;

void foo1() {
  a = b;
}

@b = common global i16 0, align 2
@a = common global i16 0, align 2

define void @foo1() #0 {
  %0 = load i16, i16* @b, align 2
  store i16 %0, i16* @a, align 2
  ret void
}

rdar://problem/20625184

Differential Revision: https://reviews.llvm.org/D40112

llvm-svn: 320215
2017-12-09 00:02:37 +00:00
Alexey Bataev dfa430f694 [OPENMP] Initial codegen for `target teams distribute` directive.
Host + default devices codegen for `target teams distribute` directive.

llvm-svn: 320149
2017-12-08 15:03:50 +00:00
Sven van Haastregt 3bb7eaf72e [OpenCL] Fix layering violation by getOpenCLTypeAddrSpace
Commit 7ac28eb0a5 / r310911 ("[OpenCL] Allow targets to select address
space per type", 2017-08-15) made Basic depend on AST, introducing a
circular dependency.  Break this dependency by adding the
OpenCLTypeKind enum in Basic and map from AST types to this enum in
ASTContext.

Differential Revision: https://reviews.llvm.org/D40838

llvm-svn: 319883
2017-12-06 10:11:28 +00:00
Dan Gohman b24e9dbafe [WebAssembly] Don't use Wasm function sections for more than one function
Patch by Nicholas Wilson!

Fixes PR35467.

Differential Revision: https://reviews.llvm.org/D40738

llvm-svn: 319801
2017-12-05 17:46:17 +00:00
Matt Arsenault e4f6280a26 AMDGPU: Don't add fp64 feature to r600 subtargets
Should fix test after r319709

llvm-svn: 319735
2017-12-05 03:51:26 +00:00
Carlo Bertolli 56a2aa4ddc [OpenMP] Initial implementation of code generation for pragma 'teams distribute parallel for simd' on host
https://reviews.llvm.org/D40795

This includes regression tests for all associated clauses.

llvm-svn: 319696
2017-12-04 20:57:19 +00:00
Aaron Ballman c351fba69e Now that C++17 is official (https://www.iso.org/standard/68564.html), start changing the C++1z terminology over to C++17. NFC intended, these are all mechanical changes.
llvm-svn: 319688
2017-12-04 20:27:34 +00:00
Martell Malone c950c651a4 Toolchain: Normalize dwarf, sjlj and seh eh
This is a re-apply of r319294.

adds -fseh-exceptions and -fdwarf-exceptions flags

clang will check if the user has specified an exception model flag,
in the absense of specifying the exception model clang will then check
the driver default and append the model flag for that target to cc1

-fno-exceptions has a higher priority then specifying the model

move __SEH__ macro definitions out of Targets into InitPreprocessor
behind the -fseh-exceptions flag

move __ARM_DWARF_EH__ macrodefinitions out of verious targets and into
InitPreprocessor behind the -fdwarf-exceptions flag and arm|thumb check

remove unused USESEHExceptions from the MinGW Driver

fold USESjLjExceptions into a new GetExceptionModel function that
gives the toolchain classes more flexibility with eh models

Reviewers: rnk, mstorsjo

Differential Revision: https://reviews.llvm.org/D39673

llvm-svn: 319297
2017-11-29 07:25:12 +00:00
Martell Malone 2fa25706ed Revert "Toolchain: Normalize dwarf, sjlj and seh eh"
This reverts rL319294.
The windows sanitizer does not like seh on x86.
Will re apply with None type for x86

llvm-svn: 319295
2017-11-29 06:51:27 +00:00
Martell Malone 390cfcb0b1 Toolchain: Normalize dwarf, sjlj and seh eh
adds -fseh-exceptions and -fdwarf-exceptions flags

clang will check if the user has specified an exception model flag,
in the absense of specifying the exception model clang will then check
the driver default and append the model flag for that target to cc1

clang cc1 assumes dwarf is the default if none is passed
and -fno-exceptions has a higher priority then specifying the model

move __SEH__ macro definitions out of Targets into InitPreprocessor
behind the -fseh-exceptions flag

move __ARM_DWARF_EH__ macrodefinitions out of verious targets and into
InitPreprocessor behind the -fdwarf-exceptions flag and arm|thumb check

remove unused USESEHExceptions from the MinGW Driver

fold USESjLjExceptions into a new GetExceptionModel function that
gives the toolchain classes more flexibility with eh models

Reviewers: rnk, mstorsjo

Differential Revision: https://reviews.llvm.org/D39673

llvm-svn: 319294
2017-11-29 06:25:13 +00:00
Alexey Bataev 2ba67045e3 [OPENMP] Generalize capturing of clauses expressions.
The handling and capturing of the non-constant expressions of some of
the capturable clauses in combined directives is generalized.

llvm-svn: 319227
2017-11-28 21:11:44 +00:00
Dan Gohman 0811cd1d15 [WebAssembly] Add options for using the nontrapping-fptoint feature.
This adds ways to control use of WebAssembly's new nontrapping-fptoint
feature.

llvm-svn: 319129
2017-11-28 01:13:45 +00:00
Alexey Bataev 974acd6b13 [OPENMP] Codegen for `distribute parallel for simd` directive.
Added proper codegen for `distribute parallel for simd` directive.

llvm-svn: 319078
2017-11-27 19:38:52 +00:00
Oren Ben Simhon fec21ec0c6 Control-Flow Enforcement Technology - Shadow Stack and Indirect Branch Tracking support (Clang side)
Shadow stack solution introduces a new stack for return addresses only.
The stack has a Shadow Stack Pointer (SSP) that points to the last address to which we expect to return.
If we return to a different address an exception is triggered.
This patch includes shadow stack intrinsics as well as the corresponding CET header.
It includes CET clang flags for shadow stack and Indirect Branch Tracking.

For more information, please see the following:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

Differential Revision: https://reviews.llvm.org/D40224

Change-Id: I79ad0925a028bbc94c8ecad75f6daa2f214171f1
llvm-svn: 318995
2017-11-26 12:34:54 +00:00
Alexey Bataev 7f96c375ac [OPENMP] General improvement of code, NFC.
llvm-svn: 318849
2017-11-22 17:19:31 +00:00
Erich Keane 0a340ab31c [X86] Update CPUSupports code to reuse LLVM .def file [NFC]
llvm-svn: 318815
2017-11-22 00:54:01 +00:00
Alexey Bataev 7828b25251 [OPENMP] Initial support for asynchronous data update, NFC.
OpenMP 5.0 introduces asynchronous data update/dependecies clauses on
target data directives. Patch adds initial support for outer task
regions to use task-based codegen for future async target data
directives.

llvm-svn: 318781
2017-11-21 17:08:48 +00:00
Martell Malone 051e966e49 [MINGW] normalize WIN32 macros
move _WIN64 and _WIN32 defines to lib/Basic/Targets/OSTargets.h
move WIN32, WIN64 and __MINGW64__ to addMinGWDefines

fixes __MINGW64__ not being defined for aarch64
adds WIN32 definition for x64

Reviewers: mstorsjo

Differential Revision: https://reviews.llvm.org/D40285

llvm-svn: 318755
2017-11-21 11:28:29 +00:00
Coby Tayree afdaa6704f [x86][inline-asm] allow recognition of MPX regs inside ms inline-asm blob
Differential Revision: https://reviews.llvm.org/D38445

llvm-svn: 318739
2017-11-21 08:50:10 +00:00
Reid Kleckner 13a3d9eb7b [MS] Increase default new alignment for win64 and test it
Summary:
This raises __STDCPP_DEFAULT_NEW_ALIGNMENT__ from 8 to 16 on Win64.
This matches platforms that follow the usual `2 * sizeof(void*)`
alignment requirement for malloc. We might want to consider making that
the default rather than relying on long double alignment.

Fixes PR35356

Reviewers: STL_MSFT, rsmith

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D40277

llvm-svn: 318723
2017-11-21 01:25:56 +00:00
Craig Topper 0ff0fbbd6b [X86] Remove 'mm3now' from isValidFeatureName.
The correct spelling is '3dnow' which is already in the list.

llvm-svn: 318716
2017-11-21 00:33:26 +00:00
Carlo Bertolli 62fae15600 [OpenMP] Initial implementation of code generation for pragma 'teams distribute parallel for' on host
https://reviews.llvm.org/D40187

This patch implements code gen for 'teams distribute parallel for' on the host, including all its clauses and related regression tests.

llvm-svn: 318692
2017-11-20 20:46:39 +00:00
Craig Topper 546cee4170 [X86] Add icelake CPU support for -march.
llvm-svn: 318617
2017-11-19 02:55:15 +00:00
Craig Topper 222c1725cd [X86] Set __corei7__ preprocessor defines for skylake server and cannonlake.
This is the resolution we came to in D38824.

llvm-svn: 318616
2017-11-19 02:55:14 +00:00
Jonas Hahnfeld 87d4426988 [OpenMP] Show error if VLAs are not supported
Some target devices (e.g. Nvidia GPUs) don't support dynamic stack
allocation and hence no VLAs. Print errors with description instead
of failing in the backend or generating code that doesn't work.

This patch handles explicit uses of VLAs (local variable in target
or declare target region) or implicitly generated (private) VLAs
for reductions on VLAs or on array sections with non-constant size.

Differential Revision: https://reviews.llvm.org/D39505

llvm-svn: 318601
2017-11-18 21:00:46 +00:00
Alexey Bataev f836537516 [OPENMP] Codegen for `target simd` construct.
Added codegen support for `target simd` directive.

llvm-svn: 318536
2017-11-17 17:57:25 +00:00
Martin Storsjo ec82128971 [MinGW] Define __ARM_DWARF_EH__ for MinGW/ARM
Since SVN r318510, the MinGW/ARM configuration defaults to
dwarf exception handling.

Differential Revision: https://reviews.llvm.org/D39533

llvm-svn: 318511
2017-11-17 08:06:49 +00:00
Ben Hamilton 7838101678 [VirtualFileSystem] Support creating directories then adding files inside
Summary:
In https://reviews.llvm.org/D39572 , I added support for specifying
`Type` when invoking `InMemoryFileSystem::addFile()`.

However, I didn't account for the fact that when `Type` is
`directory_file`, we need to construct an `InMemoryDirectory`, not an
`InMemoryFile`, or else clients cannot create files inside that
directory.

This diff fixes the bug and adds a test.

Test Plan: New test added. Ran test with:

  % make -j12 check-clang-tools

Reviewers: bkramer, hokein

Reviewed By: bkramer

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D40140

llvm-svn: 318445
2017-11-16 19:34:08 +00:00
Erich Keane 6da1108659 Split x86 "Processor" info into its own def file. [NFC]
A first step toward removing the repetition of
features/CPU info in the x86 target info, this
patch pulls all the processor information out into
its own .def file.

Differential Revision: https://reviews.llvm.org/D40093

llvm-svn: 318343
2017-11-15 22:25:39 +00:00
Erich Keane 8202521cf5 Simplify CpuIs code to use include from LLVM
LLVM exposes a file in the backend (X86TargetParser.def) that
contains information about the correct list of CpuIs values.

This patch removes 2 of the copied and pasted versions of this
list from clang and instead includes the data from the .def file.

Differential Revision: https://reviews.llvm.org/D40054

llvm-svn: 318234
2017-11-15 00:11:24 +00:00
Gabor Horvath 328d3afc3b Make DiagnosticIDs::getAllDiagnostics static. NFC.
Patch by: Andras Leitereg!

Differential Revision: https://reviews.llvm.org/D39372

llvm-svn: 318150
2017-11-14 12:14:49 +00:00
Alexey Bataev 5d7edca316 [OPENMP] Codegen for `#pragma omp target parallel for simd`.
Added codegen for `#pragma omp target parallel for simd` and clauses.

llvm-svn: 317813
2017-11-09 17:32:15 +00:00
Alexey Bataev 9a5e64f56a [OPENMP] Treat '#pragma omp target parallel for simd' as simd directive.
`#pragma omp target parallel for simd` mistakenly was not treated as a
simd directive, fixed this problem.

llvm-svn: 317811
2017-11-09 17:01:35 +00:00
Ben Hamilton e5af5bde71 [VirtualFileSystem] InMemoryFileSystem::addFile(): Type and Perms
Summary:
This implements a FIXME in InMemoryFileSystem::addFile(), allowing
clients to specify User, Group, Type, and/or Perms when creating a
file in an in-memory filesystem.

New tests included. Ran tests with:

% ninja BasicTests && ./tools/clang/unittests/Basic/BasicTests

Fixes PR#35172 (https://bugs.llvm.org/show_bug.cgi?id=35172)

Reviewers: bkramer, hokein

Reviewed By: bkramer, hokein

Subscribers: alexfh

Differential Revision: https://reviews.llvm.org/D39572

llvm-svn: 317800
2017-11-09 16:01:16 +00:00
Alexey Bataev fb0ebecf0e [OPENMP] Codegen for `#pragma omp target parallel for`.
llvm-svn: 317719
2017-11-08 20:16:14 +00:00
Mitch Phillips 512fa40b3e Update SanitizerSpecialCaseList to use renamed functions in base class.
Note: This change has a cyclical dependency on D39485. Both these changes must be submitted at the same time to avoid a build breakage.

Reviewers: vlad.tsyrklevich

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D39486

llvm-svn: 317616
2017-11-07 21:16:37 +00:00
Martin Storsjo b438ea3f1c [X86] Add 3dnow and 3dnowa to the list of valid target features
These were missed in SVN r316783, which broke compiling mingw-w64 CRT.

Differential Revision: https://reviews.llvm.org/D39631

llvm-svn: 317504
2017-11-06 20:33:13 +00:00
Eugene Zelenko 918e0ca77a [Basic] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 317381
2017-11-03 22:35:27 +00:00
Craig Topper a2b907a469 [X86] Define i586 and pentium preprocessor defines for -march=lakemont to match GCC
llvm-svn: 317069
2017-11-01 02:18:49 +00:00
Saleem Abdulrasool 1924b24aca Basic: improve coverage for Darwin targets and fix ABI
The existing coverage for the Darwin targets wasn't enough to catch all
the variations.  Improve the coverage a bit further and fix a few cases
for Darwin targets.

llvm-svn: 316826
2017-10-28 06:00:43 +00:00
Saleem Abdulrasool 418a816cdc ARM: centralise SizeType, PtrDiffType, and IntPtrType
Centralise the definitions of these compiler vended types to aid
inspection to ensure that they are defined similarly.  The one case that
stands out is the Darwin case where the types do not match up.  This
fixes the API conformance for APCS-GNU as well.

llvm-svn: 316810
2017-10-27 23:04:27 +00:00
Erich Keane cf8807c931 Filter out invalid 'target' items from being passed to LLVM
Craig noticed that CodeGen wasn't properly ignoring the
values sent to the target attribute. This patch ignores
them.

This patch also sets the 'default' for this checking to
'supported', since only X86 has implemented the support
for checking valid CPU names and Feature Names.

One test was changed to i686, since it uses a lakemont,
which would otherwise be prohibited in x86_64.

Differential Revision: https://reviews.llvm.org/D39357

llvm-svn: 316783
2017-10-27 18:32:23 +00:00
Erich Keane 3231918f4f Remove x86,x86_32/64 from isValidFeatureName
These are not valid values for this, and are pretty
non-sensical, since LLVM doesn't understand them.

Differential Revision: https://reviews.llvm.org/D39378

llvm-svn: 316781
2017-10-27 18:29:02 +00:00
Craig Topper 13cb23b8b3 [X86] Add 'sse4' to X86TargetInfo::isValidFeatureName
sse4 is valid for target attribute and functions as an alias of sse4.2.

llvm-svn: 316718
2017-10-27 00:18:16 +00:00
Craig Topper a6021e3bc1 [X86] Make -march=i686 an alias of -march=pentiumpro
I think the only reason they are different is because we don't set tune_i686 for -march=i686 to match GCC. But GCC 4.9.0 seems to have changed this behavior and they do set it now. So I think they can aliases now.

Differential Revision: https://reviews.llvm.org/D39349

llvm-svn: 316712
2017-10-26 23:06:19 +00:00
Justin Lebar 066494d8c1 [CUDA] Print an error if you try to compile with < sm_30 on CUDA 9.
Summary:
CUDA 9's minimum sm is sm_30.

Ideally we should also make sm_30 the default when compiling with CUDA
9, but that seems harder than it should be.

Subscribers: sanjoy

Differential Revision: https://reviews.llvm.org/D39109

llvm-svn: 316611
2017-10-25 21:32:06 +00:00
Craig Topper 009cebfed8 [X86] Add avx512vpopcntdq to Knights Mill
As indicated by Table 1-1 in Intel Architecture Instruction Set Extensions and Future Features Programming Reference from October 2017.

llvm-svn: 316593
2017-10-25 17:10:58 +00:00
Erich Keane 9ec60988cd Pull X86 "CPUKind" checking into .cpp file. [NFC]
Preparing to do a refactor of CPU/feature checking, this
patch pulls the one CPU implementation from the .h file
to the .cpp file.

llvm-svn: 316338
2017-10-23 16:20:15 +00:00
Saleem Abdulrasool e5696580aa Basic: restore {,u}intptr_t on NetBSD/ARM
NetBSD uses `long int` for `intptr_t` on ARM.  This was changed in SVN
r316046, referenced against other compilers.  However, NetBSD's
reference was incorrect as the current clang behaviour is more
up-to-date.  Restore the original behaviour for that target.

llvm-svn: 316204
2017-10-20 04:11:28 +00:00
Jan Vesely cda72c9c3c AMDGPU: Parse r600 CPU name early and expose FMAF capability
Improve amdgcn macro test
Differential Revision: https://reviews.llvm.org/D38667

llvm-svn: 316181
2017-10-19 20:40:13 +00:00
Sumanth Gundapaneni 57098f5ac3 [Hexagon] Handling of new HVX flags and target-features
This patch has the following changes
A new flag "-mhvx-length={64B|128B}" is introduced to specify the length of the vector.
Previously we have used "-mhvx-double" for 128 Bytes. This adds the target-feature "+hvx-length{64|128}b"

The "-mhvx" flag must be provided on command line to enable HVX for Hexagon. If no -mhvx-length flag
is specified, a default length is picked from the arch mentioned in this priority order from either -mhvx=vxx
or -mcpu. For v60 and v62 the default length is 64 Byte. For unknown versions, the length is 128 Byte. The 
-mhvx flag adds the target-feature "+hvxv{hvx_version}"

The 64 Byte mode is soon going to be deprecated. A warning is emitted if 64 Byte is enabled. A warning is
still emitted for the default 64 Byte as well. This warning can be suppressed with a -Wno flag.

The "-mhvx-double" and "-mno-hvx-double" flags are deprecated. A warning is emitted if the driver sees
them on commandline. "-mhvx-double" is an alias to "-mhvx-length=128B"

The compilation will error out if -mhvx-length is specified with out an -mhvx/-mhvx= flag

The macro HVX_LENGTH is defined and is set to the length of the vector. 
Eg: #define HVX_LENGTH 64

The macro HVX_ARCH is defined and is set to the version of the HVX. 
Eg: #define HVX_ARCH 62

Differential Revision: https://reviews.llvm.org/D38852

llvm-svn: 316102
2017-10-18 18:10:13 +00:00
Saleem Abdulrasool 8d799f8ef9 Basic: fix __{,U}INTPTR_TYPE__ on ARM
Darwin and OpenBSD are the only platforms which use `long int` for
`__INTPTR_TYPE__`.  The other platforms use `int` in 32-bit, and `long
int` on 64-bit (except for VMS and Windows which are LLP64).  Adjust the
type definitions to match the platform definitions.  We now generate the
same definition as GCC on all the targets.

llvm-svn: 316046
2017-10-18 00:00:50 +00:00
Saleem Abdulrasool f78f7c05d4 Basic: fix `__INTPTR_TYPE__` for Windows ARM
The `IntPtrType` for Windows ARM should be `int` as per MSVC.  Adjust
the type accordingly.

llvm-svn: 316042
2017-10-17 22:49:53 +00:00
Jonas Hahnfeld 23604a8399 [OpenMP] Implement omp_is_initial_device() as builtin
This allows to return the static value that we know at compile time.

Differential Revision: https://reviews.llvm.org/D38968

llvm-svn: 316001
2017-10-17 14:28:14 +00:00
Alex Lorenz f5ca27cc37 [refactor] allow the use of refactoring diagnostics
This commit allows the refactoring library to use its own set of
refactoring-specific diagnostics to reports things like initiation errors.

Differential Revision: https://reviews.llvm.org/D38772

llvm-svn: 315924
2017-10-16 18:28:26 +00:00
Alexander Richardson 6d989436d0 Convert clang::LangAS to a strongly typed enum
Summary:
Convert clang::LangAS to a strongly typed enum

Currently both clang AST address spaces and target specific address spaces
are represented as unsigned which can lead to subtle errors if the wrong
type is passed. It is especially confusing in the CodeGen files as it is
not possible to see what kind of address space should be passed to a
function without looking at the implementation.
I originally made this change for our LLVM fork for the CHERI architecture
where we make extensive use of address spaces to differentiate between
capabilities and pointers. When merging the upstream changes I usually
run into some test failures or runtime crashes because the wrong kind of
address space is passed to a function. By converting the LangAS enum to a
C++11 we can catch these errors at compile time. Additionally, it is now
obvious from the function signature which kind of address space it expects.

I found the following errors while writing this patch:

- ItaniumRecordLayoutBuilder::LayoutField was passing a clang AST address
  space to  TargetInfo::getPointer{Width,Align}()
- TypePrinter::printAttributedAfter() prints the numeric value of the
  clang AST address space instead of the target address space.
  However, this code is not used so I kept the current behaviour
- initializeForBlockHeader() in CGBlocks.cpp was passing
  LangAS::opencl_generic to TargetInfo::getPointer{Width,Align}()
- CodeGenFunction::EmitBlockLiteral() was passing a AST address space to
  TargetInfo::getPointerWidth()
- CGOpenMPRuntimeNVPTX::translateParameter() passed a target address space
  to Qualifiers::addAddressSpace()
- CGOpenMPRuntimeNVPTX::getParameterAddress() was using
  llvm::Type::getPointerTo() with a AST address space
- clang_getAddressSpace() returns either a LangAS or a target address
  space. As this is exposed to C I have kept the current behaviour and
  added a comment stating that it is probably not correct.

Other than this the patch should not cause any functional changes.

Reviewers: yaxunl, pcc, bader

Reviewed By: yaxunl, bader

Subscribers: jlebar, jholewinski, nhaehnle, Anastasia, cfe-commits

Differential Revision: https://reviews.llvm.org/D38816

llvm-svn: 315871
2017-10-15 18:48:14 +00:00
Craig Topper f8c10aa3a3 [X86] Add skeleton support for knm cpu
This adds support Knights Mill CPU. Preprocessor defines match gcc's implementation.

Differential Revision: https://reviews.llvm.org/D38813

llvm-svn: 315723
2017-10-13 18:14:24 +00:00
Yaxun Liu b7318e02c1 [OpenCL] Add LangAS::opencl_private to represent private address space in AST
Currently Clang uses default address space (0) to represent private address space for OpenCL
in AST. There are two issues with this:

Multiple address spaces including private address space cannot be diagnosed.
There is no mangling for default address space. For example, if private int* is emitted as
i32 addrspace(5)* in IR. It is supposed to be mangled as PUAS5i but it is mangled as
Pi instead.

This patch attempts to represent OpenCL private address space explicitly in AST. It adds
a new enum LangAS::opencl_private and adds it to the variable types which are implicitly
private:

automatic variables without address space qualifier

function parameter

pointee type without address space qualifier (OpenCL 1.2 and below)

Differential Revision: https://reviews.llvm.org/D35082

llvm-svn: 315668
2017-10-13 03:37:48 +00:00
Martin Storsjo d8a44ed74c [COFF, ARM64] Add MS builtins __dmb, __dsb, __isb
Differential Revision: https://reviews.llvm.org/D38821

llvm-svn: 315567
2017-10-12 07:05:37 +00:00
Craig Topper 8c8e83a15f [X86] Add support for 'amdfam17h' to __builtin_cpu_is to match gcc.
The compiler-rt implementation already supported it, it just wasn't exposed.

llvm-svn: 315517
2017-10-11 21:42:02 +00:00
Peter Collingbourne 0dfdb44797 Support: Have directory_iterator::status() return FindFirstFileEx/FindNextFile results on Windows.
This allows clients to avoid an unnecessary fs::status() call on each
directory entry. Because the information returned by FindFirstFileEx
is a subset of the information returned by a regular status() call,
I needed to extract a base class from file_status that contains only
that information.

On my machine, this reduces the time required to enumerate a ThinLTO
cache directory containing 520k files from almost 4 minutes to less
than 2 seconds.

Differential Revision: https://reviews.llvm.org/D38716

llvm-svn: 315378
2017-10-10 22:19:46 +00:00
Saleem Abdulrasool 729379a1e1 Driver: hoist the `wchar_t` handling to the driver
Move the logic for determining the `wchar_t` type information into the
driver.  Rather than passing the single bit of information of
`-fshort-wchar` indicate to the frontend the desired type of `wchar_t`
through a new `-cc1` option of `-fwchar-type` and indicate the
signedness through `-f{,no-}signed-wchar`.  This replicates the current
logic which was spread throughout Basic into the
`RenderCharacterOptions`.

Most of the changes to the tests are to ensure that the frontend uses
the correct type.  Add a new test set under `test/Driver/wchar_t.c` to
ensure that we calculate the proper types for the various cases.

llvm-svn: 315126
2017-10-06 23:09:55 +00:00
Carlo Bertolli ba1487ba69 [OpenMP] Initial implementation of teams distribute code generation
https://reviews.llvm.org/D38371

This patch implements codegen for the combined 'teams distribute" OpenMP pragma and adds regression tests for all its clauses.

llvm-svn: 314905
2017-10-04 14:12:09 +00:00
Walter Lee fc7f8f25f3 Add support for Myriad ma2x8x series of CPUs
Summary:
Also:
- Add support for some older Myriad CPUs that were missing.
- Fix some incorrect compiler defines for exisitng CPUs.

Reviewers: jyknight

Subscribers: fedor.sergeev

Differential Revision: https://reviews.llvm.org/D37551

llvm-svn: 314706
2017-10-02 18:50:57 +00:00
Yaxun Liu 304f349770 [AMDGPU] Allow flexible register names in inline asm constraints
Currently AMDGPU inline asm only allow v and s as register names in constraints.

This patch allows the following register names in constraints: (n, m is unsigned integer, n < m)

v

s

{vn} or {v[n]}

{sn} or {s[n]}

{S} , where S is a special register name

{v[n:m]}

{s[n:m]}

Differential Revision: https://reviews.llvm.org/D37568

llvm-svn: 314452
2017-09-28 19:07:59 +00:00
Davide Italiano 64094f8621 [Targets/X86] Remove unneded `return` in setMaxAtomicWidth(). NFCI.
llvm-svn: 314367
2017-09-28 00:24:20 +00:00
Dylan McKay 74d1e8683c [AVR] Update data layout to match current LLVM trunk
The data layout was changed in r314179 to fix atomic loads and stores.

llvm-svn: 314354
2017-09-27 22:09:01 +00:00
Saleem Abdulrasool 4d321336d0 Basic: support Preserve{Most,All} CC on Windows
Add support for the `preserve_mostcc` and `preserve_allcc` on Windows
x86_64 and AArch64.  This is used by Swift.

llvm-svn: 314236
2017-09-26 19:26:01 +00:00
Vlad Tsyrklevich 2eccdab308 Allow specifying sanitizers in blacklists
Summary:
This is the follow-up patch to D37924.

This change refactors clang to use the the newly added section headers
in SpecialCaseList to specify which sanitizers blacklists entries
should apply to, like so:

  [cfi-vcall]
  fun:*bad_vcall*
  [cfi-derived-cast|cfi-unrelated-cast]
  fun:*bad_cast*

The SanitizerSpecialCaseList class has been added to allow querying by
SanitizerMask, and SanitizerBlacklist and its downstream users have been
updated to provide that information. Old blacklists not using sections
will continue to function identically since the blacklist entries will
be placed into a '[*]' section by default matching against all
sanitizers.

Reviewers: pcc, kcc, eugenis, vsk

Reviewed By: eugenis

Subscribers: dberris, cfe-commits, mgorny

Differential Revision: https://reviews.llvm.org/D37925

llvm-svn: 314171
2017-09-25 22:11:12 +00:00
Michael Zuckerman 35731a0b84 [Clang] Adding missing feature to goldmont
Change-Id: I6c22478d16b8e02ce60dae2f8c80d43bc5ab3a9c
llvm-svn: 314104
2017-09-25 13:49:32 +00:00
Wei Mi b086289787 [Atomic][X8664] set max atomic inline width according to the target
This is to fix PR31620. MaxAtomicInlineWidth is set to 128 for x86_64. However
for target without cx16 support, 128 atomic operation will generate __sync_*
libcalls. The patch set MaxAtomicInlineWidth to 64 if the target doesn't support
cx16.

Differential Revision: https://reviews.llvm.org/D38046

llvm-svn: 313992
2017-09-22 16:30:00 +00:00
Gabor Horvath e350b0a196 Add Cross Translation Unit support library
This patch introduces a class that can help to build tools that require cross
translation unit facilities. This class allows function definitions to be loaded
from external AST files based on an index. In order to use this functionality an
index is required. The index format is a flat text file but it might be
replaced with a different solution in the near future. USRs are used as names to
look up the functions definitions. This class also does caching to avoid
redundant loading of AST files.

Right now only function defnitions can be loaded using this API because this is
what the in progress cross translation unit feature of the Static Analyzer
requires. In to future this might be extended to classes, types etc.

Differential Revision: https://reviews.llvm.org/D34512

llvm-svn: 313975
2017-09-22 11:11:01 +00:00
Craig Topper a98e1e214d [X86] Move even more of our CPU to feature mapping switch to use fallthroughs
This arranges more of the Intel and AMD CPUs into fallthrough positions based on their features. We may be able to merge this new AMD set with the BTVER or BDVER sets but I didn't look that closely.

Differential Revision: https://reviews.llvm.org/D37941

llvm-svn: 313497
2017-09-17 19:05:46 +00:00
Craig Topper 19a0a3ab68 [X86] Remove unnecessary extra encodings from the CPU name enum in clang
Summary:
For a lot of older CPUs we have a 1:1 mapping between CPU name and enum name. But many of them are effectively aliases of each other and as a result are always repeated together at every usage

This patch removes most of the duplication. It also uses StringSwitch::Cases to make the many to one mapping in the StringSwitch more obvious.

Reviewers: RKSimon, spatel, zvi, igorb

Reviewed By: RKSimon

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D37938

llvm-svn: 313462
2017-09-16 16:44:39 +00:00
Douglas Gregor f0b11de279 [Module map] Introduce a private module re-export directive.
Introduce a new "export_as" directive for top-level modules, which
indicates that the current module is a "private" module whose symbols
will eventually be exported through the named "public" module. This is
in support of a common pattern in the Darwin ecosystem where a single
public framework is constructed of several private frameworks, with
(currently) header duplication and some support from the linker.

Addresses rdar://problem/34438420.

llvm-svn: 313316
2017-09-14 23:38:44 +00:00
Yaxun Liu e37793545e [AMDGPU] Change addr space of clk_event_t, queue_t and reserve_id_t to global
Differential Revision: https://reviews.llvm.org/D37703

llvm-svn: 313171
2017-09-13 18:50:42 +00:00
MinSeong Kim 7c2556a895 [Basic] Update CMakeLists.txt to handle repo
Summary:
The find_first_existing_file and find_first_existing_vc_file macros in
lib/Basic/CMakeLists.txt are removed. The macros are also defined in
{LLVM}/cmake/modules/AddLLVM.cmake for the same purpose. This change
serves the following 2 objectives:

    1. To remove the redundant code in clang to use the same
       macros in llvm,
    2. The macros in AddLLVM.cmake can also handle repo for
       displaying correct version information.

Reviewers: jordan_rose, cfe-commits, modocache, hintonda

Reviewed By: hintonda

Subscribers: mgorny

Differential Revision: https://reviews.llvm.org/D35533

llvm-svn: 312865
2017-09-09 14:18:53 +00:00
Richard Smith 6d9bc278ef Fix ownership of the MemoryBuffer in a FrontendInputFile.
This fixes a possible crash on certain kinds of corrupted AST file, but
checking in an AST file corrupted in just the right way will be a maintenance
nightmare because the format changes frequently.

llvm-svn: 312851
2017-09-09 01:14:04 +00:00
Jan Vesely 31ecb4bf60 [OpenCL] Add half load and store builtins
This enables load/stores of half type, without half being a legal type.

Differential Revision: https://reviews.llvm.org/D37231

llvm-svn: 312742
2017-09-07 19:39:10 +00:00
Artem Belevich 8af4e23d1e [CUDA] Added rudimentary support for CUDA-9 and sm_70.
For now CUDA-9 is not included in the list of CUDA versions clang
searches for, so the path to CUDA-9 must be explicitly passed
via --cuda-path=.

On LLVM side NVPTX added sm_70 GPU type which bumps required
PTX version to 6.0, but otherwise is equivalent to sm_62 at the moment.

Differential Revision: https://reviews.llvm.org/D37576

llvm-svn: 312734
2017-09-07 18:14:32 +00:00
Erich Keane 0a539b5859 Change Diagnostic Category size error from runtime to compiletime
Diagnostic Categories are fairly annoying, and are only enforced
by a runtime-debug-only assert. This puts in a touch more work
to get this all done at compile-time with static asserts

Differential Revision: https://reviews.llvm.org/D37122

llvm-svn: 311905
2017-08-28 18:53:17 +00:00
Alex Lorenz d0e27266d8 [Basic] Add a DiagnosticError llvm::ErrorInfo subclass
Clang's DiagnosticError is an llvm::Error payload that stores a partial
diagnostic and its location. I'll be using it in the refactoring engine.

Differential Revision: https://reviews.llvm.org/D36969

llvm-svn: 311778
2017-08-25 15:48:00 +00:00
Petar Jovanovic 5076511ed6 [mips] Introducing option -mabs=[legacy/2008]
In patch r205628 using abs.[ds] instruction is forced, as they should behave
in accordance with flags Has2008 and ABS2008. Unfortunately for revisions
prior mips32r6 and mips64r6, abs.[ds] is not generating correct result when
working with NaNs. To generate a sequence which always produce a correct
result but also to allow user more control on how his code is compiled,
option -mabs is added where user can choose legacy or 2008.
By default legacy mode is used on revisions prior R6. Mips32r6 and mips64r6
use abs2008 mode by default.

Patch by Aleksandar Beserminji

Differential Revision: https://reviews.llvm.org/D35982

llvm-svn: 311669
2017-08-24 16:06:30 +00:00
Coby Tayree 7b49dc9c68 [Clang][x86][Inline Asm] support for GCC style inline asm - Y<x> constraints
This patch is intended to enable the use of basic double letter constraints used in GCC extended inline asm {Yi Y2 Yz Y0 Ym Yt}.
Supersedes D35205
llvm counterpart: D36369

Differential Revision: https://reviews.llvm.org/D36371

llvm-svn: 311643
2017-08-24 09:07:34 +00:00
Yonghong Song c4ea1010c1 bpf: add -mcpu=# support for bpf
-mcpu=# will support:
  . generic: the default insn set
  . v1: insn set version 1, the same as generic
  . v2: insn set version 2, version 1 + additional jmp insns
  . probe: the compiler will probe the underlying kernel to
           decide proper version of insn set.

Examples:
$ clang -target bpf -mcpu=v1 -c t.c
$ clang -target bpf -mcpu=v2 -c t.c
$ clang -target bpf -mcpu=generic -c t.c
$ clang -target bpf -mcpu=probe -c t.c
$ clang -target bpf -mcpu=v3 -c t.c
error: unknown target CPU 'v3'

Signed-off-by: Yonghong Song <yhs@fb.com>
Acked-by: Alexei Starovoitov <ast@kernel.org>
llvm-svn: 311523
2017-08-23 04:26:17 +00:00
Petar Jovanovic 9d1c094670 [mips] Rename getSupportedNanEncoding() to getIEEE754Standard()
Rename the function getSupportedNanEncoding() to getIEEE754Standard(), since
this function will be used for non-nan related features.

Patch by Aleksandar Beserminji.

Differential Revision: https://reviews.llvm.org/D36824

llvm-svn: 311454
2017-08-22 13:35:27 +00:00
Konstantin Zhuravlyov a42719406f AMDGPU: add missing amdgcn processors and tests
- gfx600
  - gfx601
  - gfx703
  - gfx902
  - gfx903

Differential Revision: https://reviews.llvm.org/D36771

llvm-svn: 311141
2017-08-18 01:13:39 +00:00
Sven van Haastregt efb4d4c78c [OpenCL] Allow targets to select address space per type
Generalize getOpenCLImageAddrSpace into getOpenCLTypeAddrSpace, such
that targets can select the address space per type.

No functional changes intended.

Initial patch by Simon Perretta.

Differential Revision: https://reviews.llvm.org/D33989

llvm-svn: 310911
2017-08-15 09:38:18 +00:00
Richard Smith 6c74e32139 [c++2a] Treat 'concept' and 'requires' as keywords, add compat warning for C++17 and before.
llvm-svn: 310803
2017-08-13 21:32:33 +00:00
Martin Storsjo 31cac7a67c [AArch64] Add support for a MinGW AArch64 target
Differential Revision: https://reviews.llvm.org/D36364

llvm-svn: 310798
2017-08-13 19:42:17 +00:00
Stefan Maksimovic 76391b101d Revert r310057
Bring back changes which r304953 introduced since
they were in fact not the cause of failures described
in r310057 commit message.

llvm-svn: 310702
2017-08-11 11:03:54 +00:00
Craig Topper 699ae0c173 [X86] Implement __builtin_cpu_is
This patch adds support for __builtin_cpu_is. I've tried to match the strings supported to the latest version of gcc.

Differential Revision: https://reviews.llvm.org/D35449

llvm-svn: 310657
2017-08-10 20:28:30 +00:00
Craig Topper 41a550ccfa [X86] Support 'avx5124vnniw' and 'avx5124fmaps' for __builtin_cpu_supports.
They still need to be implemented in the intrinsics, the command line, and the backend. But this change isn't dependent on any of that and resolves a TODO.

llvm-svn: 310386
2017-08-08 17:43:44 +00:00
Martin Storsjo c85d26b0f3 [AArch64] Ignore stdcall and similar on aarch64/windows
This is similar to what's done on arm and x86_64, where
these calling conventions are silently ignored, as in
SVN r245076.

Differential Revision: https://reviews.llvm.org/D36105

llvm-svn: 310303
2017-08-07 20:52:04 +00:00
Yaxun Liu 39195062c2 Add OpenCL 2.0 atomic builtin functions as Clang builtin
OpenCL 2.0 atomic builtin functions have a scope argument which is ideally
represented as synchronization scope argument in LLVM atomic instructions.

Clang supports translating Clang atomic builtin functions to LLVM atomic
instructions. However it currently does not support synchronization scope
of LLVM atomic instructions. Without this, users have to use LLVM assembly
code to implement OpenCL atomic builtin functions.

This patch adds OpenCL 2.0 atomic builtin functions as Clang builtin
functions, which supports generating LLVM atomic instructions with
synchronization scope operand.

Currently only constant memory scope argument is supported. Support of
non-constant memory scope argument will be added later.

Differential Revision: https://reviews.llvm.org/D28691

llvm-svn: 310082
2017-08-04 18:16:31 +00:00
Stefan Maksimovic 5c7aaa5ff3 Revert r304953 for release 5.0.0
This is causing failures when compiling clang with -O3
as one of the structures used by clang is passed by
value and uses the fastcc calling convention.

Faliures manifest for stage2 mips build.

llvm-svn: 310057
2017-08-04 12:37:34 +00:00
Walter Lee 4e93a6986e Define _GNU_SOURCE for RTEMS c++
Summary: This is required by the libc++ locale support.

Reviewers: jyknight

Subscribers: fedor.sergeev

Differential Revision: https://reviews.llvm.org/D36121

llvm-svn: 309815
2017-08-02 14:36:52 +00:00
Ilya Biryukov 47035c0255 Use VFS operations in FileManager::makeAbsolutePath.
Summary: It used to call into llvm::sys::fs::make_absolute.

Reviewers: akyrtzi, erikjv, bkramer, krasimir, klimek

Reviewed By: klimek

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D36155

llvm-svn: 309795
2017-08-02 07:25:24 +00:00
Coby Tayree d2bb48f0bd [x86][inline-asm]Allow a pack of Control Debug to be properly picked
Allows the incorporation of legit (x86) Debug Regs within inline asm stataements

Differential Revision: https://reviews.llvm.org/D36074

llvm-svn: 309672
2017-08-01 10:51:09 +00:00
Walter Lee 973131071a Move RTEMS to OSTargets.h
Differential Revision: https://reviews.llvm.org/D36106

llvm-svn: 309626
2017-07-31 21:00:16 +00:00
Martin Storsjo 588a3e5e6c [AArch64] Don't define __LP64__ when targeting Windows
Windows/ARM64 is a LLP64 environment, so don't set this default
define.

Differential Revision: https://reviews.llvm.org/D36098

llvm-svn: 309619
2017-07-31 20:40:53 +00:00
Martin Storsjo e2a247ccb0 [Targets] Move addCygMingDefines into the arch-independent Targets.cpp (NFC)
This fixes a dependency inconsistency, where addMinGWDefines in Targets.cpp
(used from other architectures than X86) called the addCygMingDefines function
in X86.h.

This was inconsistently split in SVN r308791 (D35701).

Differential Revision: https://reviews.llvm.org/D36072

llvm-svn: 309598
2017-07-31 18:17:38 +00:00
Coby Tayree 5ac75b5744 [x86][inline-asm]Allow a pack of Control Regs to be properly picked
Allows the incorporation of legit (x86) Control Regs within inline asm stataements

Differential Revision: https://reviews.llvm.org/D35903

llvm-svn: 309508
2017-07-30 10:19:10 +00:00
Akira Hatanaka c47fcf0ae5 Revert r264998 and r265035.
r303175 made changes to have __cxa_allocate_exception return a 16-byte
aligned pointer, so it's no longer necessary to specify a lower
alignment (8-bytes) for exception objects on Darwin.

rdar://problem/32363695

llvm-svn: 309308
2017-07-27 18:52:44 +00:00
Florian Hahn ef5bbd61da Update to use enum classes for various ARM *Kind enums
Summary: This updates the relevant Clang parts for the LLVM change D35882.

Reviewers: rengolin, chandlerc, javed.absar, rovka

Reviewed By: rovka

Subscribers: aemerson, cfe-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D35884

llvm-svn: 309289
2017-07-27 16:28:39 +00:00
Tim Northover ad4c5db1ef AArch64 & ARM: move TargetInfo functions from .h to .cpp file. NFC.
Most of them are virtual anyway, and the few remaining ones can move to the
.cpp for consistency.

llvm-svn: 308898
2017-07-24 17:06:23 +00:00
Yuka Takahashi b40f4db4af [Bash-autocompletion] Fixed typo and add '-' after -Wno
Summary: -Wno-<warning> was autocompleted as -Wno<warning>, so fixed this typo.

Differential Revision: https://reviews.llvm.org/D35762

llvm-svn: 308824
2017-07-22 12:35:15 +00:00
Erich Keane 2b9657b570 Remove Bitrig: Clang Changes
Bitrig code has been merged back to OpenBSD, thus the OS has been abandoned.

Differential Revision: https://reviews.llvm.org/D35708

llvm-svn: 308797
2017-07-21 22:46:31 +00:00
Erich Keane ebba592682 Break up Targets.cpp into a header/impl pair per target type[NFCI]
Targets.cpp is getting unwieldy, and even minor changes cause the entire thing 
to cause recompilation for everyone. This patch bites the bullet and breaks 
it up into a number of files.

I tended to keep function definitions in the class declaration unless it 
caused additional includes to be necessary. In those cases, I pulled it 
over into the .cpp file. Content is copy/paste for the most part, 
besides includes/format/etc.


Differential Revision: https://reviews.llvm.org/D35701

llvm-svn: 308791
2017-07-21 22:37:03 +00:00
Alexey Bataev fa312f33f8 [OPENMP] Initial support for 'in_reduction' clause.
Parsing/sema analysis for 'in_reduction' clause for task-based
directives.

llvm-svn: 308768
2017-07-21 18:48:21 +00:00
Krzysztof Parzyszek 33e67ad098 [Hexagon] Add inline-asm constraint 'a' for modifier register class
For example
  asm ("memw(%0++%1) = %2" : : "r"(addr),"a"(mod),"r"(val) : "memory")

llvm-svn: 308763
2017-07-21 18:07:15 +00:00
Artem Belevich d7a73824e4 [NVPTX] Add lowering of i128 params.
The patch adds support of i128 params lowering. The changes are quite trivial to
support i128 as a "special case" of integer type. With this patch, we lower i128
params the same way as aggregates of size 16 bytes: .param .b8 _ [16].

Currently, NVPTX can't deal with the 128 bit integers:
* in some cases because of failed assertions like
  ValVTs.size() == OutVals.size() && "Bad return value decomposition"
* in other cases emitting PTX with .i128 or .u128 types (which are not valid [1])
  [1] http://docs.nvidia.com/cuda/parallel-thread-execution/index.html#fundamental-types

Differential Revision: https://reviews.llvm.org/D34555
Patch by: Denys Zariaiev (denys.zariaiev@gmail.com)

llvm-svn: 308675
2017-07-20 21:16:03 +00:00
Benjamin Kramer d515291ffd [vfs] Assert that the status is known in equivalent().
Otherwise we'd silently compare uninitialized data.

llvm-svn: 308604
2017-07-20 11:57:02 +00:00
Craig Topper 9377b9fa69 [X86] Put avx512vpopcntdq in the right spot in the validateCpuSupports string switch.
The validateCpuSupports switch is in the order of the enum defined in CGBuiltin.cpp and libgcc/compiler-rt.

llvm-svn: 308546
2017-07-19 22:58:58 +00:00
Erich Keane 2c748cc756 Add isValidCPUName and isValidFeature to TargetInfo
These two functions are really useful for implementations of attributes 
(including attribute-target), so add the functionality.

llvm-svn: 308530
2017-07-19 21:50:08 +00:00
Alexey Bataev 169d96a203 [OPENMP] Initial support for 'task_reduction' clause.
Parsing/sema analysis of the 'task_reduction' clause.

llvm-svn: 308352
2017-07-18 20:17:46 +00:00
Mandeep Singh Grang daa40b98ef [COFF, ARM64] Set the data type widths and the data layout string
Summary: COFF ARM64 is LLP64 platform. So int is 4 bytes, long is 4 bytes and long long is 8 bytes.

Reviewers: compnerd, ruiu, rnk, efriedma

Reviewed By: compnerd, efriedma

Subscribers: efriedma, javed.absar, cfe-commits, aemerson, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D34859

llvm-svn: 308222
2017-07-17 21:10:45 +00:00
Martin Storsjo 022e782e75 [AArch64] Add support for __builtin_ms_va_list on aarch64
Move builtins from the x86 specific scope into the global
scope. Their use is still limited to x86_64 and aarch64 though.

This allows wine on aarch64 to properly handle variadic functions.

Differential Revision: https://reviews.llvm.org/D34475

llvm-svn: 308218
2017-07-17 20:49:45 +00:00
Brian Gesiak 7873d822f7 [Basic] Detect Git submodule version in CMake
Summary:
When searching for Git version control information, libBasic's CMake
checks for the path '.git/logs/HEAD'. However, when LLVM is included as
a Git submodule, this path does not exist. Instead, it contains a '.git'
file with the following:

```
gitdir: ../../.git/modules/external/llvm
```

Where '../..' is the relative path to the root repository that contains
the LLVM Git submodule.

Because of this discrepancy, `clang --version` does not output source
control information if built from a Git submodule.

To fix, check whether '.git' is a directory or a file. If it's a
directory, simply use the '.git/logs/HEAD' path. If it's a file, read it
and check for the tell-tale sign of a Git submodule: the text "gitdir:".
If it exists, follow that path and use the 'logs/HEAD' at that location
instead. This allows not only the correct revision information to be
retrieved, but also uses a file that will change with each source
control revision.

Test Plan:
1. Before applying this change, build Clang as a Git submodule in a repository
   that places it in external/clang, and confirm no revision information
   is output when `clang --version` is invoked (just "clang 5.0.0" is
   output, no Git hashes).
2. Apply these changes and build Clang as a Git repository nested under
   llvm/tools/clang, and confirm that `clang --version` displays correct
   version information.
3. Apply these changes and build Clang as a Git submodule using the
   structure described in (1), and confirm version control information
   is output as in (2).

Reviewers: jordan_rose, beanz, probinson

Reviewed By: jordan_rose

Subscribers: chapuni, mgorny, cfe-commits

Differential Revision: https://reviews.llvm.org/D34955

llvm-svn: 308205
2017-07-17 19:22:57 +00:00
Ulrich Weigand 76976a7920 [SystemZ] Add support for IBM z14 processor (2/3)
This patch extends the -fzvector language feature to enable the new
"vector float" data type when compiling at -march=z14.  This matches
the updated extension definition implemented by other compilers for
the platform, which is indicated to applications by pre-defining
__VEC__ to 10302 (instead of 10301).

llvm-svn: 308198
2017-07-17 17:46:47 +00:00
Ulrich Weigand cac24ab04c [SystemZ] Add support for IBM z14 processor (1/3)
This patch series adds support for the IBM z14 processor.  This part includes:
- Basic support for the new processor and its features.
- Support for low-level builtins mapped to new LLVM intrinsics.

Support for the -fzvector extension to vector float and the new
high-level vector intrinsics is provided by separate patches.

llvm-svn: 308197
2017-07-17 17:45:57 +00:00
Brad Smith 733fe193d3 Enable TLS support on OpenBSD, but default to the emulatated TLS model.
llvm-svn: 308155
2017-07-17 00:49:31 +00:00
Yuka Takahashi 64918d0b25 [Bash-autocompletion] Add support for -W<warning> and -Wno<warning>
Summary:
`-W[tab]` will autocomplete warnings defined in this link:
https://clang.llvm.org/docs/DiagnosticsReference.html#wweak-vtables

Differential Revision: https://reviews.llvm.org/D35447

llvm-svn: 308139
2017-07-16 15:07:20 +00:00
Craig Topper 3544b3e501 [X86] Add 'movbe' to btver2 CPU.
This probably doesn't change anything because the frotend doesn't do anything with this feature and the backend will infer from the cpu string. So this is just for consistency with other cpus that support movbe.

llvm-svn: 308002
2017-07-14 06:36:17 +00:00
Amara Emerson ebe02904d4 [AArch64] Add support for handling the +sve target feature.
This also adds the appropriate predefine for SVE if enabled.

Differential Revision: https://reviews.llvm.org/D35118

llvm-svn: 307919
2017-07-13 15:36:01 +00:00
Simon Atanasyan 3606ebf6d6 [mips] Create the correct profiling symbol on Linux MIPS
llvm-svn: 307627
2017-07-11 06:19:01 +00:00
Yaxun Liu cbf647cc3a CodeGen: Fix address space of global variable
Certain targets (e.g. amdgcn) require global variable to stay in global or constant address
space. In C or C++ global variables are emitted in the default (generic) address space.
This patch introduces virtual functions TargetCodeGenInfo::getGlobalVarAddressSpace
and TargetInfo::getConstantAddressSpace to handle this in a general approach.

It only affects IR generated for amdgcn target.

Differential Revision: https://reviews.llvm.org/D33842

llvm-svn: 307470
2017-07-08 13:24:52 +00:00
Craig Topper 61395176f9 [X86] Replace 'fallthrough' comments with LLVM_FALLTHROUGH.
llvm-svn: 307420
2017-07-07 18:41:09 +00:00
Sjoerd Meijer 98ee78578b This reverts r305820 (ARMv.2-A FP16 vector intrinsics) because it shows
problems in testing, see comments in D34161 for some more details.
A fix is in progres in D35011, but a revert seems better now as the fix will
probably take some more time to land.

llvm-svn: 307277
2017-07-06 16:37:31 +00:00
Ulrich Weigand 6d6c4808ef [SystemZ] Simplify handling of ISA revisions
This moves determination of the ISA revision from the CPU name to
one single place, removing a bunch of duplicated code.  It also
makes the supported ISA revisions available as feature strings.

No functional change.

llvm-svn: 307156
2017-07-05 13:19:47 +00:00
Yaxun Liu 25d1b4341f [AMDGPU] Fix size and alignment of size_t and pointer types
Differential Revision: https://reviews.llvm.org/D34995

llvm-svn: 307121
2017-07-05 04:58:24 +00:00
Yaxun Liu 3ba4a720ad [AMDGPU] Fix regressions on mesa/clover with libclc due to address space
Currently AMDGPUTargetInfo does not initialize AddrSpaceMap in constructor, which causes regressions in mesa/clover with libclc.

This patch fixes that.

Differential Revision: https://reviews.llvm.org/D34987

llvm-svn: 307105
2017-07-04 19:57:18 +00:00
Hiroshi Inoue 3170de0eb8 fix trivial typos; NFC
llvm-svn: 306954
2017-07-01 08:46:43 +00:00
Yuka Takahashi dc771509a4 Changed Opts.EABIVersion type string to llvm::EABI enum class
Summary:
Changed EABIVersion type from string to llvm::EABI.
It seems it was just a typo and this is intended implementation.

Differential Revision: https://reviews.llvm.org/D34595

llvm-svn: 306953
2017-07-01 07:57:23 +00:00
Craig Topper 9dd7e808b3 [X86] Add RDRND feature to Goldmont. Add MOVBE to all Atom CPUs.
Diffential Revision: https://reviews.llvm.org/D34842

llvm-svn: 306851
2017-06-30 18:14:04 +00:00
Craig Topper 541075ded5 [X86] Add a break to the last case of a few switches to prevent accidents in the future. NFC
llvm-svn: 306850
2017-06-30 18:14:02 +00:00
Craig Topper f458bd2135 [X86] Move all atom CPUs to the same section of the switch and use fallthroughs like we do for other CPU generations. NFC
This is prep work to add MOVBE to all Atom CPUs. This instruction didn't come in to the Nehalem/Westmere/SandyBridge/etc. line until later so there's no natural place to overlap the Atom CPUs into that part of the switch.

llvm-svn: 306849
2017-06-30 18:14:01 +00:00
Sjoerd Meijer cb75f61c1d ARMV8-A archkind and target defines helper functions
This introduces helper functions that set target defines for different ARMV8-A
architecture kinds. It fixes an issue that the v8.1 define ARM_FEATURE_QRDMX
was not set for v8.2. These helper functions make things more “scalable” if we
want to add ARMv8.3 at some point, and a cleanup has been done to hold the
architecture kind in one variable (instead of one for each).

Differential Revision: https://reviews.llvm.org/D34686

llvm-svn: 306805
2017-06-30 08:07:34 +00:00
Michael Zuckerman a046ef4c26 [Clang][X86][Goldmont]Adding new target-cpu: Goldmont
[Clang-side] Connecting the GoldMont processor to his feature.


Reviewers:
1. igorb
2. delena
3. zvi


Differential Revision: https://reviews.llvm.org/D34807

llvm-svn: 306673
2017-06-29 13:41:04 +00:00
Gabor Horvath 7848b388ee Factor out a functionality from isBeforeInTranslationUnit
The first user of this API will be the cross translation unit
functionality of the Static Analyzer which will be committed in a
follow-up patch. 

Differential Revision: https://reviews.llvm.org/D34506

llvm-svn: 306648
2017-06-29 06:53:13 +00:00
Mandeep Singh Grang 2fd6b1651d [COFF, ARM64] Add support for Windows ARM64 COFF format
Summary: This is the clang part of the initial implementation to support Windows ARM64 COFF format.

Reviewers: ruiu, t.p.northover, rnk, compnerd

Reviewed By: ruiu, compnerd

Subscribers: aemerson, kristof.beyls, cfe-commits, llvm-commits

Differential Revision: https://reviews.llvm.org/D34706

llvm-svn: 306489
2017-06-27 23:56:34 +00:00
Christof Douma fb4a0450db Revert "Revert "[NFC] Refactor DiagnosticRenderer to use FullSourceLoc""
This reverts commit r305688 meaning it reintroduces r305684. To repeat:

[NFC] Refactor DiagnosticRenderer to use FullSourceLoc

Move the DiagnosticRenderer and its dependents to using FullSourceLocs
instead of a SourceLocation and SourceManager pointer. The changeset is
rather large but entirely mechanical.

This is step one to allow DiagnosticRenderer to take either
llvm::SMLocs or clang::SourceLocations.

This breaks clang-tidy and clng-query which will be fixed in a commit
soon after.

Patch by Sanne Wouda

Differential Revision: https://reviews.llvm.org/D31709

llvm-svn: 306384
2017-06-27 09:50:38 +00:00
Nikolai Bozhenov 35d3c35bea Reapply "Frontend support for Nios2 target"
Summary:
- Implements TargetInfo class for Nios2 target.
- Enables handling of -march and -mcpu options for Nios2 target.
- Definition of Nios2 builtin functions.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D33356

Author: belickim <mateusz.belicki@intel.com>
llvm-svn: 306383
2017-06-27 09:48:24 +00:00
Richard Smith b4fd6a6141 Remove some redundant setup when preprocessing .pcm files.
Both of these steps are immediately overwritten by the FrontendAction setup.

llvm-svn: 306325
2017-06-26 20:15:21 +00:00
Marina Yatsina 33eb775265 [inline asm][gcc-compatiblity] "=i" output constraint support
Ignore ‘i’,’n’,’E’,’F’ as output constraints in inline assembly (gcc compatibility)

Differential Revision: https://reviews.llvm.org/D31383

llvm-svn: 306297
2017-06-26 15:55:51 +00:00
Ed Schouten 4dabea22d3 Add support for Ananas platform
Ananas is a home-brew operating system, mainly for amd64 machines. After
using GCC for quite some time, it has switched to clang and never looked
back - yet, having to manually patch things is annoying, so it'd be much
nicer if this was in the official tree.

More information:

https://github.com/zhmu/ananas/
https://rink.nu/projects/ananas.html

Submitted by:	Rink Springer
Differential Revision:	https://reviews.llvm.org/D32936

llvm-svn: 306239
2017-06-25 08:29:09 +00:00
Vadzim Dambrouski 00b396c0a0 [MSP430] Fix data layout string.
Summary:
Change data layout string so it would be compatible with MSP430 EABI.

Depends on D34561

Reviewers: asl, awygle

Reviewed By: asl

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D34562

llvm-svn: 306161
2017-06-23 21:12:56 +00:00
Abderrazek Zaafrani f10ca93f34 [AArch64] ADD ARMv.2-A FP16 vector intrinsics
Differential Revision: https://reviews.llvm.org/D34161

llvm-svn: 305820
2017-06-20 18:54:57 +00:00
Richard Smith 9565c75b29 Support non-identifier module names when preprocessing modules.
llvm-svn: 305758
2017-06-19 23:09:36 +00:00
Christof Douma cc1c112806 Revert "[NFC] Refactor DiagnosticRenderer to use FullSourceLoc"
This reverts commit 305684.
This patch breaks extra/tools/clang-tidy

llvm-svn: 305688
2017-06-19 12:41:22 +00:00
Christof Douma f9d86db755 [NFC] Refactor DiagnosticRenderer to use FullSourceLoc
Move the DiagnosticRenderer and its dependents to using FullSourceLocs
instead of a SourceLocation and SourceManager pointer. The changeset is
rather large but entirely mechanical.

This is step one to allow DiagnosticRenderer to take either
llvm::SMLocs or clang::SourceLocations.

Patch by Sanne Wouda

Review: https://reviews.llvm.org/D31709

Change-Id: If351a112cdf6718e2d3ef6721b8da9c6376b32dd
llvm-svn: 305684
2017-06-19 12:05:58 +00:00
Daniel Jasper d078254049 Revert "Define _GNU_SOURCE for rtems c++"
This reverts commit r305399.

This breaks a build in libcxx:
libcxx/src/system_error.cpp:90:16: error: assigning to 'int' from incompatible type 'char *'
    if ((ret = ::strerror_r(ev, buffer, strerror_buff_size)) != 0) {
               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 error generated.

Which makes sense according to:
https://linux.die.net/man/3/strerror_r

Not entirely sure how this needs to be fixed.

llvm-svn: 305456
2017-06-15 09:17:12 +00:00
James Y Knight 02b0e9d97a Define _GNU_SOURCE for rtems c++
This is required by the libc++ locale support.

Patch by Walter Lee.

Differential Revision: https://reviews.llvm.org/D34105

llvm-svn: 305399
2017-06-14 17:01:18 +00:00
Nikolai Bozhenov de57795cc8 Revert of r305066 "Reapply Frontend support for Nios2 target"
llvm-svn: 305068
2017-06-09 12:09:29 +00:00
Nikolai Bozhenov b2de17c734 Reapply "Frontend support for Nios2 target"
Summary:
- Implements TargetInfo class for Nios2 target.
- Enables handling of -march and -mcpu options for Nios2 target.
- Definition of Nios2 builtin functions.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D33356

Author: belickim <mateusz.belicki@intel.com>
llvm-svn: 305066
2017-06-09 10:56:18 +00:00
Nikolai Bozhenov 1c36934883 Revert "Frontend support for Nios2 target"
As it breaks many buildbots.

llvm-svn: 305002
2017-06-08 18:36:35 +00:00
Nikolai Bozhenov 32dc6c8540 Frontend support for Nios2 target.
Summary:
- Implements TargetInfo class for Nios2 target.
- Enables handling of -march and -mcpu options for Nios2 target.
- Definition of Nios2 builtin functions.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D33356

Author: belickim <mateusz.belicki@intel.com>
llvm-svn: 304994
2017-06-08 17:40:30 +00:00
Petar Jovanovic 9b5d3b6a9f Reapply r304929 [mips] Add runtime options to enable/disable madd/sub.fmt
The test in r304929 broke multiple buildbots as it expected mips target to
be registered and available (which is not necessarily true). Updating the
test with this condition.

Original commit:

  [mips] Add runtime options to enable/disable madd.fmt and msub.fmt

  Add options to clang: -mmadd4 and -mno-madd4, use it to enable or disable
  generation of madd.fmt and similar instructions respectively, as per GCC.

  Patch by Stefan Maksimovic.

llvm-svn: 304953
2017-06-07 23:51:52 +00:00
Petar Jovanovic 53900b0221 Revert r304929 [mips] Add runtime options to enable/disable madd/sub.fmt
Revert r304929 since the test broke buildbots.

Original commit:

  [mips] Add runtime options to enable/disable madd.fmt and msub.fmt

  Add options to clang: -mmadd4 and -mno-madd4, use it to enable or disable
  generation of madd.fmt and similar instructions respectively, as per GCC.

  Patch by Stefan Maksimovic.

llvm-svn: 304935
2017-06-07 18:57:56 +00:00
Petar Jovanovic c6d9b04cc3 [mips] Add runtime options to enable/disable madd.fmt and msub.fmt
Add options to clang: -mmadd4 and -mno-madd4, use it to enable or disable
generation of madd.fmt and similar instructions respectively, as per GCC.

Patch by Stefan Maksimovic.

Differential Revision: https://reviews.llvm.org/D33401

llvm-svn: 304929
2017-06-07 17:17:57 +00:00
Florian Hahn cc524bf6ac [CodeGen] Add thumb-mode to target-features for arm/thumb triples.
Summary:
The thumb-mode target feature is used to force Thumb or ARM code
generation on a per-function basis. Explicitly adding +thumb-mode to
functions for thumbxx triples enables mixed ARM/Thumb code generation in
places where compilation units with thumbxx and armxx triples are merged
together (e.g. the IR linker or LTO).

For armxx triples, -thumb-mode is added in a similar fashion.

Reviewers: echristo, t.p.northover, kristof.beyls, rengolin

Reviewed By: echristo

Subscribers: rinon, aemerson, mehdi_amini, javed.absar, cfe-commits

Differential Revision: https://reviews.llvm.org/D33448

llvm-svn: 304897
2017-06-07 11:50:45 +00:00
Javed Absar 15b80a5b23 [ARM] Fix Neon vector type alignment to 64-bit
This is restricted version of patch - https://reviews.llvm.org/D33205
that I reverted as it was leading to ABI breaks on darwin etc.
This patch restricts the fix to AAPCS (Android remains 128-bit).
Reviewed by: Renato Golin, Stephen Hines
Differential Revision: https://reviews.llvm.org/D33786

llvm-svn: 304889
2017-06-07 10:02:02 +00:00
Dan Gohman 7dee171f69 [WebAssembly] Set MaxAtomicInlineWidth to 64.
The WebAssembly threads proposal has changed such that C++
implementations can now declare that atomics up to 64 bits are
"lock free" in C++'s terms.

llvm-svn: 304859
2017-06-07 02:22:40 +00:00
Florian Hahn 28f03bbcbb [ARM] Add support for target("arm") and target("thumb").
Summary:
This patch adds support for the target("arm") and target("thumb")
attributes, which can be used to force the compiler to generated ARM or
Thumb code for a function.

In LLVM, ARM or Thumb code generation can be controlled by the
thumb-mode target feature. But GCC already uses target("arm") and
target("thumb"), so we have to substitute "arm" with -thumb-mode and
"thumb" with +thumb-mode.


Reviewers: echristo, pcc, kristof.beyls

Reviewed By: echristo

Subscribers: ahatanak, aemerson, javed.absar, kristof.beyls, cfe-commits

Differential Revision: https://reviews.llvm.org/D33721

llvm-svn: 304781
2017-06-06 09:26:15 +00:00
Richard Smith f878a84cc4 Fix memory leak exposed by r304726.
When giving a ContentCache a null buffer, ignore the DoNotFree flag rather than
inheriting it onto whatever buffer we end up using for the file. Also ensure
that the main buffer is properly destroyed.

llvm-svn: 304740
2017-06-05 22:05:31 +00:00
Richard Smith ab75597dda Rather than rejecting attempts to run preprocessor-only actions on AST files,
replay the steps taken to create the AST file with the preprocessor-only action
installed to produce preprocessed output.

This can be used to produce the preprocessed text for an existing .pch or .pcm
file.

llvm-svn: 304726
2017-06-05 18:10:11 +00:00
Galina Kistanova ddcd2812f5 Added missing break.
llvm-svn: 304653
2017-06-03 06:40:10 +00:00
Galina Kistanova 96088f4d41 Added LLVM_FALLTHROUGH to address warning: this statement may fall through. NFC.
llvm-svn: 304652
2017-06-03 06:38:22 +00:00
Richard Smith 040e12662a Support lazy stat'ing of files referenced by module maps.
This patch adds support for a `header` declaration in a module map to specify
certain `stat` information (currently, size and mtime) about that header file.
This has two purposes:

- It removes the need to eagerly `stat` every file referenced by a module map.
  Instead, we track a list of unresolved header files with each size / mtime
  (actually, for simplicity, we track submodules with such headers), and when
  attempting to look up a header file based on a `FileEntry`, we check if there
  are any unresolved header directives with that `FileEntry`'s size / mtime and
  perform deferred `stat`s if so.

- It permits a preprocessed module to be compiled without the original files
  being present on disk. The only reason we used to need those files was to get
  the `stat` information in order to do header -> module lookups when using the
  module. If we're provided with the `stat` information in the preprocessed
  module, we can avoid requiring the files to exist.

Unlike most `header` directives, if a `header` directive with `stat`
information has no corresponding on-disk file the enclosing module is *not*
marked unavailable (so that behavior is consistent regardless of whether we've
resolved a header directive, and so that preprocessed modules don't get marked
unavailable). We could actually do this for all `header` directives: the only
reason we mark the module unavailable if headers are missing is to give a
diagnostic slightly earlier (rather than waiting until we actually try to build
the module / load and validate its .pcm file).

Differential Revision: https://reviews.llvm.org/D33703

llvm-svn: 304515
2017-06-02 01:55:39 +00:00
Vedant Kumar a44a6ac81f Revert "[AArch64] Add ARMv8.2-A FP16 vefctor intrinsics"
This reverts commit r304493. It breaks all the Darwin bots:
http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental_check/37168

Failure:
Failing Tests (2):
    Clang :: CodeGen/aarch64-v8.2a-neon-intrinsics.c
    Clang :: CodeGen/arm_neon_intrinsics.c

llvm-svn: 304509
2017-06-02 01:22:14 +00:00
Abderrazek Zaafrani a44e5f601d [AArch64] Add ARMv8.2-A FP16 vefctor intrinsics
llvm-svn: 304493
2017-06-01 23:22:29 +00:00
Vedant Kumar 85a83c2ced [Modules] Handle sanitizer feature mismatches when importing modules
This patch makes it an error to have a mismatch between the enabled
sanitizers in a CU, and in any module being imported into the CU. Only
mismatches between non-modular sanitizers are treated as errors.

This patch also includes non-modular sanitizers in module hashes, in
order to ensure module rebuilds occur when -fsanitize=X is toggled on
and off for non-modular sanitizers, and to cut down on module rebuilds
when the option is toggled for modular sanitizers.

This fixes a longstanding issue with implicit modules and sanitizers,
which Duncan originally diagnosed.

When building with implicit modules it's possible to hit a scenario
where modules are built without -fsanitize=address, and are subsequently
imported into CUs with -fsanitize=address enabled. This causes strange
failures at runtime. The case Duncan found affects libcxx, since its
vector implementation behaves differently when ASan is enabled.

Implicit module builds should "just work" when -fsanitize=X is toggled
on and off across multiple compiler invocations, which is what this
patch does.

Differential Revision: https://reviews.llvm.org/D32724

llvm-svn: 304463
2017-06-01 20:01:01 +00:00
Pekka Jaaskelainen fc2629a65a [OpenCL] Makes kernels use the SPIR_KERNEL CC by default.
Rationale: OpenCL kernels are called via an explicit runtime API
with arguments set with clSetKernelArg(), not as normal sub-functions.
Return SPIR_KERNEL by default as the kernel calling convention to ensure
the fingerprint is fixed such way that each OpenCL argument gets one
matching argument in the produced kernel function argument list to enable
feasible implementation of clSetKernelArg() with aggregates etc. In case
we would use the default C calling conv here, clSetKernelArg() might
break depending on the target-specific conventions; different targets
might split structs passed as values to multiple function arguments etc.

https://reviews.llvm.org/D33639

llvm-svn: 304389
2017-06-01 07:18:49 +00:00
Javed Absar 089f678784 Reverting Neon vector type 64-alignment fix
The patch caused ABI breaks on darwin/others.
Reverting to come back with a more restrictive patch.

llvm-svn: 304220
2017-05-30 17:09:47 +00:00
Javed Absar 3d92d7ab36 [ARM] Fix Neon vector type alignment to 64-bit
The maximum alignment for ARM NEON data types should be 64-bits as specified
in ARM procedure call standard document Sec. A.2 Notes.
This patch fixes it from its current larger natural default values, except
for Android (so as not to break existing ABI).
Reviewed by: Stephen Hines, Renato Golin.
Differential Revision: https://reviews.llvm.org/D33205

llvm-svn: 304201
2017-05-30 10:12:15 +00:00
Eric Fiselier e38cea026b [coroutines] Support "coroutines" feature in module map requires clause
Summary: In order for libc++ to add `<experimental/coroutine>` to its module map, there has to be a feature that can be used to detect if coroutines support is enabled in Clang. 

Reviewers: rsmith

Reviewed By: rsmith

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D33538

llvm-svn: 304107
2017-05-28 21:07:22 +00:00
Eric Fiselier 9208dd63ef Revert "[coroutines] Support "coroutines" feature in module map requires clause"
This reverts commit r304054.

llvm-svn: 304057
2017-05-27 03:04:51 +00:00
Eric Fiselier 0bb3bcd0ef [coroutines] Support "coroutines" feature in module map requires clause
Summary: In order for libc++ to add `<experimental/coroutine>` to its module map, there has to be a feature that can be used to detect if coroutines support is enabled in Clang. 

Reviewers: rsmith

Reviewed By: rsmith

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D33538

llvm-svn: 304054
2017-05-27 02:46:17 +00:00
Reid Kleckner a40b38a637 Only define __SIZEOF_FLOAT128__ on x86 as intended in r304012
GCC only defines it on x86.

llvm-svn: 304013
2017-05-26 17:48:01 +00:00
Reid Kleckner 9eabbb6066 Enable __float128 for mingw for GCC compatibility and define __SIZEOF_FLOAT128__ on x86
GCC defines __FLOAT128__ on Power and __SIZEOF_FLOAT128__ on x86. We're
just following the inconsistency for now so users have some way to test.

Effectively merges this patch as requested by Martell Malone:
https://github.com/Alexpux/MINGW-packages/blob/master/mingw-w64-clang/0107-enable-__float128-for-X86-MinGW.patch

llvm-svn: 304012
2017-05-26 17:38:15 +00:00
Oren Ben Simhon 140c1fb9ec [X86] Adding avx512_vpopcntdq feature set and its intrinsics
AVX512_VPOPCNTDQ is a new feature set that was published by Intel.
The patch represents the Clang side of the addition of six intrinsics for two new machine instructions (vpopcntd and vpopcntq).
It also includes the addition of the new feature set.

Differential Revision: https://reviews.llvm.org/D33170

llvm-svn: 303857
2017-05-25 13:44:11 +00:00
Saleem Abdulrasool b6e946b164 Basic: fix whitespace in file header (NFC)
llvm-svn: 303804
2017-05-24 20:27:09 +00:00
Dean Michael Berris 170429e290 [XRay][clang] Allow imbuing arg1 logging attribute via -fxray-always-instrument=
Summary:
This change allows us to add arg1 logging support to functions through
the special case list provided through -fxray-always-instrument=. This
is useful for adding arg1 logging to functions that are either in
headers that users don't have control over (i.e. cannot change the
source) or would rather not do.

It only takes effect when the pattern is matched through the "fun:"
special case, as a category. As in:

  fun:*pattern=arg1

Reviewers: pelikan, rnk

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D33392

llvm-svn: 303719
2017-05-24 05:46:36 +00:00
Galina Kistanova 3677c0f1d8 Removed fallthrough annotation which does not directly precede switch label.
llvm-svn: 303653
2017-05-23 16:56:10 +00:00
Galina Kistanova 078b301bcc Added LLVM_FALLTHROUGH to address gcc warning: this statement may fall through.
llvm-svn: 303649
2017-05-23 16:33:07 +00:00
Yaxun Liu af3d4db64b [AMDGPU] Do not require opencl triple environment for OpenCL
A recent change requires opencl triple environment for compiling OpenCL
program, which causes regressions in libclc.

This patch fixes that. Instead of deducing language based on triple
environment, it checks LangOptions.

Differential Revision: https://reviews.llvm.org/D33445

llvm-svn: 303644
2017-05-23 16:15:53 +00:00
Reid Kleckner eb00ee07be Give files from #line the characteristics of the current file
This allows #line directives to appear in system headers that have code
that clang would normally warn on. This is compatible with GCC, which is
easy to test by running `gcc -E`.

Fixes PR30752

llvm-svn: 303582
2017-05-22 21:42:58 +00:00
Yaxun Liu 6d96f16347 CodeGen: Cast alloca to expected address space
Alloca always returns a pointer in alloca address space, which may
be different from the type defined by the language. For example,
in C++ the auto variables are in the default address space. Therefore
cast alloca to the expected address space when necessary.

Differential Revision: https://reviews.llvm.org/D32248

llvm-svn: 303370
2017-05-18 18:51:09 +00:00
James Y Knight eb96e44aea [SPARC] Support 'f' and 'e' inline asm constraints.
Patch by Patrick Boettcher.

Differential Revision: https://reviews.llvm.org/D29117

llvm-svn: 302913
2017-05-12 16:01:23 +00:00
Simon Pilgrim 3511348dbb [X86][LWP] Add clang support for LWP instructions.
This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4).

Differential Revision: https://reviews.llvm.org/D32770

llvm-svn: 302418
2017-05-08 12:09:45 +00:00
Weiming Zhao be380c711c [ARM] Limit the diagnose when an ISR calls a regular function
Summary:
When the function is compiled with soft-float or on CPU with no FPU, we
don't need to diagnose for a call from an ISR to a regular function.

Reviewers: jroelofs, eli.friedman

Reviewed By: jroelofs

Subscribers: aemerson, rengolin, javed.absar, cfe-commits

Differential Revision: https://reviews.llvm.org/D32918

llvm-svn: 302274
2017-05-05 19:25:29 +00:00
Alex Lorenz ce4518f21d DiagnosticsEngine should clear DelayedDiagID before reporting the
delayed diagnostic

This fix avoids an infinite recursion that was uncovered in one of our internal
tests by r301992. The testcase is the most reduced version of that
auto-generated test.

This is an improved version of the reverted commit r302037. The previous fix
actually managed to expose another subtle bug whereby `fatal_too_many_errors`
error was reported twice, with the second report setting the
`FatalErrorOccurred` flag. That prevented the notes that followed the diagnostic
the caused `fatal_too_many_errors` to be emitted. This commit ensures that notes
that follow `fatal_too_many_errors` but that belong to the diagnostic that
caused `fatal_too_many_errors` won't be emitted by setting the
`FatalErrorOccurred` when emitting `fatal_too_many_errors`.

rdar://31962618

llvm-svn: 302151
2017-05-04 13:56:51 +00:00
Alex Lorenz 5191e80b87 Revert r302037
The commit caused the following two buildbot failures:

    Clang :: Misc/error-limit-multiple-notes.cpp
    Clang :: Misc/error-limit.c

llvm-svn: 302046
2017-05-03 16:22:16 +00:00
Alex Lorenz d7dfec818b DiagnosticsEngine should clear DelayedDiagID before reporting the
delayed diagnostic

This avoids an infinite loop that was uncovered in one of our internal tests
by r301992. The testcase is the most reduced version of that auto-generated
test.

rdar://31962618

llvm-svn: 302037
2017-05-03 15:41:16 +00:00
Richard Smith e37391c4fe [modules] Round-trip -Werror flag through explicit module build.
The intent for an explicit module build is that the diagnostics produced within
the module are those that were configured when the module was built, not those
that are enabled within a user of the module. This includes diagnostics that
don't actually show up until the module is used (for instance, diagnostics
produced during template instantiation and weird cases like -Wpadded).

We serialized and restored the diagnostic state for individual warning groups,
but previously did not track the state for flags like -Werror and -Weverything,
which are implemented as separate bits rather than as part of the diagnostics
mapping information.

llvm-svn: 301992
2017-05-03 00:28:49 +00:00
Duncan P. N. Exon Smith 16b1ac950b Darwin: Define __STDC_NO_THREADS__ on Darwin targets
Darwin doesn't support C11 threads.h.  Define `__STDC_NO_THREADS__` so
that users can check for it.

rdar://problem/18461003

llvm-svn: 301508
2017-04-27 01:47:22 +00:00
Carlo Bertolli ffafe10fac [OpenMP] Prepare sema to support combined constructs with omp distribute and omp for
https://reviews.llvm.org/D32237

This patch prepares sema with additional fields to support all those composite and combined constructs of OpenMP that include pragma 'distribute' and 'for', such as 'distribute parallel for'. It also extends the regression tests for 'distribute parallel for' and adds a new one.

llvm-svn: 300802
2017-04-20 00:39:39 +00:00
Alex Lorenz 9e7bf161ea Add #pragma clang attribute
This is a recommit of r300539 that was reverted in r300543 due to test failures.
The original commit message is displayed below:

The new '#pragma clang attribute' directive can be used to apply attributes to
multiple declarations. An attribute must satisfy the following conditions to
be supported by the pragma:
- It must have a subject list that's defined in the TableGen file.
- It must be documented.
- It must not be late parsed.
- It must have a GNU/C++11 spelling.

Differential Revision: https://reviews.llvm.org/D30009

llvm-svn: 300556
2017-04-18 14:33:39 +00:00
Oliver Stannard 233310f3e6 [ARM,AArch64] Define __ELF__ for arm-none-eabihf and AArch64
This macro is defined for arm-none-eabi as of r266625, but it should also be
defined for eabihf and aarch64.

llvm-svn: 300549
2017-04-18 13:12:36 +00:00