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1672 Commits

Author SHA1 Message Date
Jim Laskey 527c12f8e6 Make it easier for gdb to find the return address. 
llvm-svn: 32277
 2006-12-06 17:42:06 +00:00
Jim Laskey e4f4d048dd Restoration of the stack pointer after a deallocation of a alloca was not 
updating the SP link.

llvm-svn: 32202
 2006-12-04 22:04:42 +00:00
Evan Cheng 022030a425 Add weak reference directive. 
llvm-svn: 32091
 2006-12-01 20:47:11 +00:00
Evan Cheng b689d32b20 Copy and paste error. An initialized global cannot be a weak reference. 
llvm-svn: 32075
 2006-12-01 17:39:22 +00:00
Jim Laskey 1b0bc794e6 1. In ppc64 mode we need only use one GPR. 
2. Float values need to be promoted to double when they are vararg.

llvm-svn: 32074
 2006-12-01 16:30:47 +00:00
Jim Laskey 311622f912 ExternalWeak case in wrong location. 
llvm-svn: 32073
 2006-12-01 14:37:39 +00:00
Evan Cheng 5fb2c76d59 A initialized global variable cannot be extern weak. However, if a global value's initializer is itself a external weak symbol, emit the weak reference. 
llvm-svn: 32069
 2006-12-01 09:13:26 +00:00
Evan Cheng fa54c0b6fb Darwin PPC external weak linkage support. 
llvm-svn: 32068
 2006-12-01 07:56:37 +00:00
Chris Lattner 09ed0ff2ac Fix the CodeGen/PowerPC/vec_constants.ll regression. 
llvm-svn: 32057
 2006-12-01 01:45:39 +00:00
Evan Cheng aafeaef8c8 MachineInstr::setOpcode -> MachineInstr::setInstrDescriptor 
llvm-svn: 32034
 2006-11-30 07:12:03 +00:00
Chris Lattner 2f648fc55d Fix bug codegen'ing FP constant vectors with integer splats. Make sure the 
created intrinsics have the right integer types.  This fixes
PowerPC/2006-11-29-AltivecFPSplat.ll

llvm-svn: 32024
 2006-11-29 19:58:49 +00:00
Jim Laskey 152671f0bf Offset for load of 32-bit arg in 64-bit world was incorrect. 
llvm-svn: 32019
 2006-11-29 13:37:09 +00:00
Jim Laskey 40182179b6 Remove debug code. 
llvm-svn: 31970
 2006-11-28 18:27:02 +00:00
Jim Laskey ec05b046c7 Prime text sections to improve branch locality in large object files. 
llvm-svn: 31969
 2006-11-28 18:21:52 +00:00
Jim Laskey f4e2e009d9 32-bit int space was not accounted for properly in lowerCall. 
llvm-svn: 31966
 2006-11-28 14:53:52 +00:00
Evan Cheng 20350c4025 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 
of opcode and number of operands.

llvm-svn: 31947
 2006-11-27 23:37:22 +00:00
Reid Spencer 6968c497de Add newline at end of file. 
llvm-svn: 31902
 2006-11-25 05:41:02 +00:00
Chris Lattner ec5dbccdcf in ppc64-mode, don't allocate the 32-bit version of r13 either. 
llvm-svn: 31884
 2006-11-20 20:48:05 +00:00
Chris Lattner ac36360348 r13 is the thread pointer on darwin/ppc64, don't allocate it. 
llvm-svn: 31882
 2006-11-20 19:33:51 +00:00
Chris Lattner 2cca385fbb on ppc64, float arguments take 8-byte stack slots not 4-byte stack slots. 
Also, valist should create a pointer RC reg class value, not a GPRC value.

llvm-svn: 31840
 2006-11-18 01:57:19 +00:00
Chris Lattner 572e238c14 make sure to safe LR8 in the right stack slot for PPC64 
llvm-svn: 31839
 2006-11-18 01:34:43 +00:00
Chris Lattner 9ca15c8914 Pretty print 'rldicr r2, r2, 2, 61' as 'sldi r2, r2, 2'. 
llvm-svn: 31838
 2006-11-18 01:23:56 +00:00
Chris Lattner 542dfd5510 Rewrite the branch selector to be correct in the face of large functions. 
The algorithm it used before wasn't 100% correct, we now use an iterative
expansion model.  This fixes assembler errors when compiling 403.gcc with
tail merging enabled.

Change the way the branch selector works overall: Now, the isel generates
PPC::BCC instructions (as it used to) directly, and these BCC instructions
are emitted to the output or jitted directly if branches don't need
expansion.  Only if branches need expansion are instructions rewritten
and created.  This should make branch select faster, and eliminates the
Bxx instructions from the .td file.

llvm-svn: 31837
 2006-11-18 00:32:03 +00:00
Chris Lattner 33fc1d45e5 add encoding for BCC, after finally wrestling strange ppc/tblgen endianness 
issues to the ground.

llvm-svn: 31836
 2006-11-17 23:53:28 +00:00
Chris Lattner be9377a1e3 convert PPC::BCC to use the 'pred' operand instead of separate predicate 
value and CR reg #.  This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(

llvm-svn: 31835
 2006-11-17 22:37:34 +00:00
Chris Lattner e0263794f4 rename PPC::COND_BRANCH to PPC::BCC 
llvm-svn: 31834
 2006-11-17 22:14:47 +00:00
Chris Lattner 8c6a41ea12 start using PPC predicates more consistently. 
llvm-svn: 31833
 2006-11-17 22:10:59 +00:00
Jim Laskey 73106b5e2a Assert unhandled case. 
llvm-svn: 31828
 2006-11-17 18:49:39 +00:00
Jim Laskey 1823346b3e 1. Ignore the -disable-fp-elim when the routine is a leaf. 
2. Offsets on 64-bit stores are still in bytes.

llvm-svn: 31824
 2006-11-17 16:09:31 +00:00
Jim Laskey 91542a4f2d Typo. Fix the nightly tests. 
llvm-svn: 31823
 2006-11-17 14:06:41 +00:00
Chris Lattner 3b7261b18e implement a todo: change a map into a vector 
llvm-svn: 31805
 2006-11-17 01:52:23 +00:00
Chris Lattner be1a4d80b3 fix typo 
llvm-svn: 31799
 2006-11-17 00:49:36 +00:00
Chris Lattner a715288b40 implicit_def_vrrc doesn't generate code. 
llvm-svn: 31797
 2006-11-16 23:49:52 +00:00
Jim Laskey 48850c10c0 This is a general clean up of the PowerPC ABI. Address several problems and 
bugs including making sure that the TOS links back to the previous frame,
that the maximum call frame size is not included twice when using frame
pointers, no longer growing the frame on calls, double storing of SP and
a cleaner/faster dynamic alloca.

llvm-svn: 31792
 2006-11-16 22:43:37 +00:00
Chris Lattner 30055b9208 fix a regression that I introduced. stdu should scale the offset by 4 
before printing it.

llvm-svn: 31791
 2006-11-16 21:45:30 +00:00
Chris Lattner 96d7386006 add a statistic 
llvm-svn: 31785
 2006-11-16 18:13:49 +00:00
Chris Lattner a7ff5162b0 fix broken encoding 
llvm-svn: 31778
 2006-11-16 01:01:28 +00:00
Chris Lattner e742d9a4b7 add ppc64 r+i stores with update. 
llvm-svn: 31776
 2006-11-16 00:57:19 +00:00
Chris Lattner 6f5840c409 add patterns for ppc32 preinc stores. ppc64 next. 
llvm-svn: 31775
 2006-11-16 00:41:37 +00:00
Chris Lattner 3a494989a6 switch these back to the 'bad old way' 
llvm-svn: 31774
 2006-11-16 00:33:34 +00:00
Chris Lattner b4e911d15a Fix ppc64 epilog bug. 
llvm-svn: 31771
 2006-11-15 23:35:30 +00:00
Chris Lattner 5771156be0 Stop using isTwoAddress, switching to operand constraints instead. 
Tell the codegen emitter that specific operands are not to be encoded, fixing
JIT regressions w.r.t. pre-inc loads and stores (e.g. lwzu, which we generate
even when general preinc loads are not enabled).

llvm-svn: 31770
 2006-11-15 23:24:18 +00:00
Evan Cheng dc2c8748a7 Properly transfer kill / dead info. 
llvm-svn: 31765
 2006-11-15 20:58:11 +00:00
Chris Lattner 474b5b7c95 fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memri 
addrmodes.

llvm-svn: 31757
 2006-11-15 19:55:13 +00:00
Chris Lattner 0e117c7e9d Fix the PPC regressions last night 
llvm-svn: 31752
 2006-11-15 17:40:51 +00:00
Chris Lattner 1396961e85 Switch loads over to use memri as the operand instead of a reg/imm operand 
pair for cleanliness.  Add instructions for PPC32 preinc-stores with commented
out patterns.  More improvement is needed to enable the patterns, but we're
getting close.

llvm-svn: 31749
 2006-11-15 02:43:19 +00:00
Chris Lattner e79a451475 group load and store instructions together. No functionality change. 
llvm-svn: 31736
 2006-11-14 19:19:53 +00:00
Chris Lattner 44dbdbe5cf Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 calls 
clobber.  This allows LR8 to be save/restored correctly as a 64-bit quantity,
instead of handling it as a 32-bit quantity.  This unbreaks ppc64 codegen when
the code is actually located above the 4G boundary.

llvm-svn: 31734
 2006-11-14 18:44:47 +00:00
Chris Lattner b542925b22 remove a ton of custom selection logic no longer needed 
llvm-svn: 31733
 2006-11-14 18:43:11 +00:00
Chris Lattner 97ff46b3cc lower "X = seteq Y, Z" to '(shr (ctlz (xor Y, Z)), 5)' instead of 
'(shr (ctlz (sub Y, Z)), 5)'.

The use of xor better exposes the operation to bit-twiddling logic in the
dag combiner.  For example, this:

typedef struct {
  unsigned prefix : 4;
  unsigned code : 4;
  unsigned unsigned_p : 4;
} tree_common;

int foo(tree_common *a, tree_common *b) {
  return a->code == b->code;
}

Now compiles to:

_foo:
        lwz r2, 0(r4)
        lwz r3, 0(r3)
        xor r2, r3, r2
        rlwinm r2, r2, 28, 28, 31
        cntlzw r2, r2
        srwi r3, r2, 5
        blr

instead of:

_foo:
        lbz r2, 3(r4)
        lbz r3, 3(r3)
        srwi r2, r2, 4
        srwi r3, r3, 4
        subf r2, r2, r3
        cntlzw r2, r2
        srwi r3, r2, 5
        blr

saving a cycle.

llvm-svn: 31725
 2006-11-14 05:28:08 +00:00