fed3d088ce
correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics
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llvm-svn: 91313
2009-12-14 19:24:11 +00:00
20ac87de13
add Thumb2 atomic and memory barrier instruction definitions
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llvm-svn: 91310
2009-12-14 18:56:47 +00:00
2522908653
Materialize global addresses via movt/movw pair, this is always better
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than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
llvm-svn: 89720
2009-11-24 00:44:37 +00:00
f890f51666
80 column violations
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llvm-svn: 89718
2009-11-24 00:20:27 +00:00
04c0e76772
fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.
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llvm-svn: 89694
2009-11-23 20:35:53 +00:00
bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
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llvm-svn: 89478
2009-11-20 19:57:15 +00:00
207b246650
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
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load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
llvm-svn: 86304
2009-11-06 23:52:48 +00:00
b376ce0169
Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.
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llvm-svn: 85965
2009-11-03 23:13:34 +00:00
1c66e8a6b7
Put BlockAddresses into ARM constant pools.
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llvm-svn: 85824
2009-11-02 20:59:23 +00:00
5ac6f244fd
Fix schedule model for BFC.
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llvm-svn: 85809
2009-11-02 17:28:36 +00:00
cdbb70c065
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
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llvm-svn: 85643
2009-10-31 03:39:36 +00:00
1cf0b03064
Add ARM codegen for indirect branches.
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clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
llvm-svn: 85577
2009-10-30 05:45:42 +00:00
453d64c9f5
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
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bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
b02bdb4552
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
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llvm-svn: 85184
2009-10-27 00:08:59 +00:00
a93ca3c637
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
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immediate operands when they will fit into the using instruction.
llvm-svn: 84778
2009-10-21 20:44:34 +00:00
786b15fe12
Match more patterns to movt.
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llvm-svn: 84751
2009-10-21 08:15:52 +00:00
423e42b371
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
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llvm-svn: 84009
2009-10-13 18:59:48 +00:00
1b2b64f618
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
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ld / st pairs, etc.
llvm-svn: 83197
2009-10-01 08:22:27 +00:00
3bbc6c3ae6
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
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llvm-svn: 83191
2009-10-01 01:33:39 +00:00
bcad0c8421
Add "isBarrier = 1" to return instructions.
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Patch by Sylvere Teissier.
llvm-svn: 83135
2009-09-30 01:35:11 +00:00
83e0d481ae
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
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instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
llvm-svn: 82982
2009-09-28 09:14:39 +00:00
7c2b1e71c1
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
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This should be better than single load from constpool.
llvm-svn: 82948
2009-09-27 23:52:58 +00:00
a6b9cab822
Enable pre-regalloc load / store multiple pass for Thumb2.
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llvm-svn: 82893
2009-09-27 09:46:04 +00:00
5f582b7290
RRX reads CPSR.
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llvm-svn: 80699
2009-09-01 18:32:09 +00:00
4047b53a40
Print a nl before pic labels so they start at a new line. This makes assembly more readable.
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llvm-svn: 80350
2009-08-28 06:59:37 +00:00
ceffeb6abd
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
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several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
llvm-svn: 79676
2009-08-21 21:58:55 +00:00
a7c2dfbca1
Update Cortex-A8 instruction itineraries for integer instructions.
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llvm-svn: 79436
2009-08-19 18:00:44 +00:00
dd406177de
Fix revsh pattern.
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llvm-svn: 79318
2009-08-18 05:43:23 +00:00
db73d68cbe
Shrink ADR and LDR from constantpool late during constantpool island pass.
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llvm-svn: 78970
2009-08-14 00:32:16 +00:00
eba70d85cf
Add missing defs of R2 and D1.
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llvm-svn: 78918
2009-08-13 16:59:44 +00:00
a9c2aad939
Finalize itineraries for cortex-a8 integer multiply
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llvm-svn: 78908
2009-08-13 15:51:13 +00:00
695e1c6087
Remove unnecessary newline
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llvm-svn: 78905
2009-08-13 15:12:16 +00:00
c96e88f8a5
Correct comment wording
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llvm-svn: 78904
2009-08-13 15:11:43 +00:00
b369ee4c48
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
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llvm-svn: 78827
2009-08-12 18:31:53 +00:00
a5fdfac6ca
register naming cleanup (s/ip/r12/)
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llvm-svn: 78806
2009-08-12 15:21:13 +00:00
608d92c943
Remove an Darwin assembler workaround.
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llvm-svn: 78777
2009-08-12 01:56:42 +00:00
cc9ca3500d
Shrinkify Thumb2 load / store multiple instructions.
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llvm-svn: 78717
2009-08-11 21:11:32 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
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the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
841850ed26
Add Thumb2 eh_sjlj_setjmp implementation
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llvm-svn: 78701
2009-08-11 19:42:21 +00:00
d4d352c663
80 column violation.
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llvm-svn: 78657
2009-08-11 08:47:46 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
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llvm-svn: 78610
2009-08-10 22:56:29 +00:00
51cbd2d6c4
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
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llvm-svn: 78550
2009-08-10 02:37:24 +00:00
cfed3005e5
Use subclassing to print lane-like immediates (w/o hash) eliminating
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'no_hash' modifier. Hopefully this will make Daniel happy :)
llvm-svn: 78514
2009-08-08 23:10:41 +00:00
6e130db3b7
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
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llvm-svn: 78410
2009-08-07 21:19:10 +00:00
b972e5633f
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
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This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
b062c236c5
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
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llvm-svn: 78321
2009-08-06 16:52:47 +00:00
7cc6aca1e6
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
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llvm-svn: 78126
2009-08-04 23:47:55 +00:00
03eb0e3c33
Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
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llvm-svn: 78030
2009-08-04 01:41:15 +00:00
e64f48ba8b
Workaround a couple of Darwin assembler bugs.
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llvm-svn: 77781
2009-08-01 06:13:52 +00:00
e6e8289d72
Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
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llvm-svn: 77764
2009-08-01 01:43:45 +00:00
Jim Grosbach