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86 Commits

Author SHA1 Message Date
Venkatraman Govindaraju 9a3da52ea2 [Sparc] Handle atomic loads/stores in sparc backend. 
llvm-svn: 198286
 2014-01-01 22:11:54 +00:00
Venkatraman Govindaraju acf0233a46 [SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does. 
llvm-svn: 198280
 2014-01-01 19:00:10 +00:00
Venkatraman Govindaraju 3e3a29a2e9 [SparcV9] Use separate instruction patterns for 64 bit arithmetic instructions instead of reusing 32 bit instruction patterns. 
This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot.

llvm-svn: 198157
 2013-12-29 07:15:09 +00:00
Venkatraman Govindaraju 9c338504e5 [Sparc]: Implement LEA pattern for sparcv9. 
llvm-svn: 195575
 2013-11-24 20:07:35 +00:00
Venkatraman Govindaraju 5ae77f7564 [SparcV9] Handle i64 <-> float conversions in sparcv9 mode. 
llvm-svn: 193957
 2013-11-03 12:28:40 +00:00
Venkatraman Govindaraju 2ea4c2880c [Sparc] Implement JIT for SPARC. 
No new testcases. However, this patch makes all supported JIT testcases in 
test/ExecutionEngine  pass on Sparc.

llvm-svn: 192176
 2013-10-08 07:15:22 +00:00
Venkatraman Govindaraju 8223c553cf [Sparc] Do not hardcode nop in the delay slot of TLS_CALL. Use DelaySlotFiller to fill the delay slot instead. 
llvm-svn: 192160
 2013-10-08 02:50:29 +00:00
Venkatraman Govindaraju f482d3d338 [Sparc] Do not emit nop after fcmp* instruction with V9. 
llvm-svn: 192056
 2013-10-06 07:06:44 +00:00
Venkatraman Govindaraju 1230342fd2 [Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx. 
addx/subx does not modify conditional codes whereas addxcc/subxx does.

llvm-svn: 192053
 2013-10-06 02:11:10 +00:00
Venkatraman Govindaraju 94629eb861 [Sparc] Use correct instruction pattern for CMPri. 
llvm-svn: 191180
 2013-09-22 18:54:54 +00:00
Venkatraman Govindaraju 51270837aa [Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter. 
llvm-svn: 191168
 2013-09-22 09:54:42 +00:00
Venkatraman Govindaraju 709d154d69 [Sparc] Clean up MOVcc instructions so that TableGen can encode them correctly. No functionality change intended. 
llvm-svn: 191167
 2013-09-22 09:18:26 +00:00
Venkatraman Govindaraju 2fb440fbad [Sparc] Clean up branch instructions, so that TableGen can encode branch conditions as well. No functionality change intended. 
llvm-svn: 191166
 2013-09-22 08:51:55 +00:00
Venkatraman Govindaraju cb1dca602c [Sparc] Add support for TLS in sparc. 
llvm-svn: 191164
 2013-09-22 06:48:52 +00:00
Venkatraman Govindaraju 59039dc1bf [Sparc] Add support for soft long double (fp128). 
llvm-svn: 189780
 2013-09-03 04:11:59 +00:00
Venkatraman Govindaraju 35e0c382d5 [Sparc] Add long double (f128) instructions to sparc backend. 
llvm-svn: 189198
 2013-08-25 18:30:06 +00:00
Jakob Stoklund Olesen 0c00704f27 Use register masks on SPARC call instructions. 
llvm-svn: 189085
 2013-08-23 02:33:47 +00:00
Venkatraman Govindaraju f625773bca [Sparc] Use HWEncoding instead of unused Num field in Sparc register definitions. Also, correct the definitions of RETL and RET instructions. 
llvm-svn: 188738
 2013-08-20 01:26:14 +00:00
Venkatraman Govindaraju 7dae9ce021 [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. 
llvm-svn: 183613
 2013-06-08 15:32:59 +00:00
Venkatraman Govindaraju dc82ac0dcc [Sparc]: Use cmp instruction instead of subcc to compare integers. 
llvm-svn: 183463
 2013-06-07 00:03:36 +00:00
Venkatraman Govindaraju a54533ed78 Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 
llvm-svn: 183243
 2013-06-04 18:33:25 +00:00
Venkatraman Govindaraju f80d72f149 Sparc: Add support for indirect branch and blockaddress in Sparc backend. 
llvm-svn: 183094
 2013-06-03 05:58:33 +00:00
Venkatraman Govindaraju 774fe2e29a Sparc: When storing 0, use %g0 directly in the store instruction instead of 
using two instructions (sethi and store).

llvm-svn: 183090
 2013-06-03 00:21:54 +00:00
Jakob Stoklund Olesen 4a78c86a6a Implement SPselectfcc for i64 operands. 
Also clean up the arguments to all the MOVCC instructions so the
operands always are (true-val, false-val, cond-code).

llvm-svn: 182221
 2013-05-19 20:20:54 +00:00
Jakob Stoklund Olesen ead983cec9 Handle i64 FrameIndex nodes in SPARC v9 mode. 
llvm-svn: 182216
 2013-05-19 19:14:24 +00:00
Jakob Stoklund Olesen 65d3287282 Fix the SETHIimm pattern for 64-bit code. 
Don't ignore the high 32 bits of the immediate.

llvm-svn: 179985
 2013-04-21 21:18:03 +00:00
Jakob Stoklund Olesen dc1ed57858 Fix patterns for 64-bit pointers. 
This fixes the pic32 code model for SPARC v9.

llvm-svn: 179469
 2013-04-14 01:53:23 +00:00
Jakob Stoklund Olesen 8cfaffaade Add SPARC v9 support for select on 64-bit compares. 
This requires v9 cmov instructions using the %xcc flags instead of the
%icc flags.

Still missing:
- Select floats on %xcc flags.
- Select i64 on %fcc flags.

llvm-svn: 178737
 2013-04-04 03:08:00 +00:00
Jakob Stoklund Olesen d9bbdfd3cc Add 64-bit compare + branch for SPARC v9. 
The same compare instruction is used for 32-bit and 64-bit compares. It
sets two different sets of flags: icc and xcc.

This patch adds a conditional branch instruction using the xcc flags for
64-bit compares.

llvm-svn: 178621
 2013-04-03 04:41:44 +00:00
Jakob Stoklund Olesen c1d1a4816e Add 64-bit shift instructions. 
SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right
instructions are still usable as zero and sign extensions.

This adds new F3_Sr and F3_Si instruction formats that probably should
be used for the 32-bit shifts as well. They don't really encode an
simm13 field.

llvm-svn: 178525
 2013-04-02 04:09:12 +00:00
Jakob Stoklund Olesen 739d722ef7 Add predicates for distinguishing 32-bit and 64-bit modes. 
The 'sparc' architecture produces 32-bit code while 'sparcv9' produces
64-bit code.

It is also possible to run 32-bit code using SPARC v9 instructions with:

  llc -march=sparc -mattr=+v9

llvm-svn: 178524
 2013-04-02 04:09:06 +00:00
Jakob Stoklund Olesen 5ad3b35377 Add an I64Regs register class for 64-bit registers. 
We are going to use the same registers for 32-bit and 64-bit values, but
in two different register classes. The I64Regs register class has a
larger spill size and alignment.

The addition of an i64 register class confuses TableGen's type
inference, so it is necessary to clarify the type of some immediates and
the G0 register.

In 64-bit mode, pointers are i64 and should use the I64Regs register
class. Implement getPointerRegClass() to dynamically provide the pointer
register class depending on the subtarget. Use ptr_rc and iPTR for
memory operands.

Finally, add the i64 type to the IntRegs register class. This register
class is not used to hold i64 values, I64Regs is for that. The type is
required to appease TableGen's type checking in output patterns like this:

  def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>;

SPARC v9 uses the same ADDrr instruction for i32 and i64 additions, and
TableGen doesn't know to check the type of register sub-classes.

llvm-svn: 178522
 2013-04-02 04:08:54 +00:00
Jakob Stoklund Olesen 9619fc0bd1 Clean up Sparc patterns. 
The types of register variables no longer need to be specified in output
patterns.

llvm-svn: 177845
 2013-03-24 19:37:04 +00:00
Jakob Stoklund Olesen 83aa671f09 Give Sparc instruction patterns direct types instead of register classes. 
Also update the documentation since Sparc is the nicest backend, and
used as an example in WritingAnLLVMBackend.

llvm-svn: 177835
 2013-03-24 00:56:20 +00:00
Jakob Stoklund Olesen b1f7c28765 Use direct types in Sparc def : Pat patterns. 
The SelectionDAG graph has MVT type labels, not register classes, so
this makes it clearer what is happening.

This notation is also robust against adding more types to the IntRegs
register class.

llvm-svn: 177829
 2013-03-23 20:35:05 +00:00
Jakob Stoklund Olesen ef8bf3cd1f Move MRI liveouts to Sparc return instructions. 
llvm-svn: 174413
 2013-02-05 18:16:58 +00:00
Jakob Stoklund Olesen acf7c47e64 Add missing SDNP properties on the flushw node. 
llvm-svn: 162515
 2012-08-24 00:31:13 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Venkatraman Govindaraju a82203f875 Generate correct Sparc32 ABI compliant code for functions that return a struct. 
llvm-svn: 126108
 2011-02-21 03:42:44 +00:00
Venkatraman Govindaraju 7a0c350079 Added ICC, FCC as uses of movcc instruction to generate correct code when -mattr=v9 is used. 
llvm-svn: 124027
 2011-01-22 11:36:24 +00:00
Venkatraman Govindaraju ef8cf45eb1 Sparc backend: 
Rename FLUSH to FLUSHW.
 Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used.

llvm-svn: 123997
 2011-01-21 22:00:00 +00:00
Venkatraman Govindaraju 058e12476c Sparc backend: Implements a delay slot filler that attempt to fill delay slots 
with useful instructions.

llvm-svn: 123884
 2011-01-20 05:08:26 +00:00
Venkatraman Govindaraju d964580fea Implement RETURNADDR and FRAMEADDR lowering in SPARC backend. 
llvm-svn: 123310
 2011-01-12 05:08:36 +00:00
Venkatraman Govindaraju ee347f8091 Remove SPARC backend getpcx instruction's Uses. Also, insert an assert to 
ensure %o7 is not assigned as the destination of getpcx instruction.

llvm-svn: 123304
 2011-01-12 03:52:59 +00:00
Venkatraman Govindaraju 3b71b0ae3d Fix SPARC backend call instruction so that arguments passed through registers 
are correctly marked as used instead of passing all possible argument registers
as used.  

llvm-svn: 123301
 2011-01-12 03:18:21 +00:00
Venkatraman Govindaraju 4d6ade0e31 SPARC backend: correct ICC/FCC uses for ADDX and SELECT_CC 
llvm-svn: 123281
 2011-01-11 22:38:28 +00:00
Venkatraman Govindaraju 2f15503d5a Multiple SPARC backend fixes: added Y register; updated select_cc, subx, subxcc defs/uses; 
and fixed CustomInserter.

llvm-svn: 122607
 2010-12-28 20:39:17 +00:00
Chris Lattner 2a0a3b43d7 Flag -> Glue, the ongoing saga 
llvm-svn: 122513
 2010-12-23 18:28:41 +00:00
Jakob Stoklund Olesen f02b4a686a Don't call Predicate_* methods directly from Sparc target. 
Modernize predicates a bit.

The Predicate_* methods are not used by TableGen any longer. They are only
emitted for the sake of legacy code.

llvm-svn: 111263
 2010-08-17 18:17:12 +00:00
Eric Christopher d7a7356be6 Remove isTwoAddress from Sparc. 
llvm-svn: 106466
 2010-06-21 20:22:35 +00:00