3 Commits

Author	SHA1	Message	Date
Matt Arsenault	4b1f6cdbf9	AMDGPU: Don't run indexing mode switches with exec = 0 ... Add mode defs rather than special casing this like some of the other instructions.	2020-06-02 13:47:48 -04:00
Stanislav Mekhanoshin	677929e352	[AMDGPU] Process V_MOV_B32_indirect in SET_GPR_IDX optimization ... Differential Revision: https://reviews.llvm.org/D80256	2020-05-19 21:37:14 -07:00
Stanislav Mekhanoshin	7d16a22eb0	[AMDGPU] Peephole adjacent equivalent S_SET_GPR_IDX_ON ... Differential Revision: https://reviews.llvm.org/D79907	2020-05-14 15:44:33 -07:00