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104 Commits

Author SHA1 Message Date
David Goodwin 5f582b7290 RRX reads CPSR. 
llvm-svn: 80699
 2009-09-01 18:32:09 +00:00
Evan Cheng 4047b53a40 Print a nl before pic labels so they start at a new line. This makes assembly more readable. 
llvm-svn: 80350
 2009-08-28 06:59:37 +00:00
Bob Wilson ceffeb6abd Rename ARM "lane_cst" operands to "nohash_imm" since they are used for 
several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.

llvm-svn: 79676
 2009-08-21 21:58:55 +00:00
David Goodwin a7c2dfbca1 Update Cortex-A8 instruction itineraries for integer instructions. 
llvm-svn: 79436
 2009-08-19 18:00:44 +00:00
Evan Cheng dd406177de Fix revsh pattern. 
llvm-svn: 79318
 2009-08-18 05:43:23 +00:00
Evan Cheng db73d68cbe Shrink ADR and LDR from constantpool late during constantpool island pass. 
llvm-svn: 78970
 2009-08-14 00:32:16 +00:00
Jim Grosbach eba70d85cf Add missing defs of R2 and D1. 
llvm-svn: 78918
 2009-08-13 16:59:44 +00:00
David Goodwin a9c2aad939 Finalize itineraries for cortex-a8 integer multiply 
llvm-svn: 78908
 2009-08-13 15:51:13 +00:00
Jim Grosbach 695e1c6087 Remove unnecessary newline 
llvm-svn: 78905
 2009-08-13 15:12:16 +00:00
Jim Grosbach c96e88f8a5 Correct comment wording 
llvm-svn: 78904
 2009-08-13 15:11:43 +00:00
David Goodwin b369ee4c48 Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one. 
llvm-svn: 78827
 2009-08-12 18:31:53 +00:00
Jim Grosbach a5fdfac6ca register naming cleanup (s/ip/r12/) 
llvm-svn: 78806
 2009-08-12 15:21:13 +00:00
Evan Cheng 608d92c943 Remove an Darwin assembler workaround. 
llvm-svn: 78777
 2009-08-12 01:56:42 +00:00
Evan Cheng cc9ca3500d Shrinkify Thumb2 load / store multiple instructions. 
llvm-svn: 78717
 2009-08-11 21:11:32 +00:00
Owen Anderson 9f94459d24 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while 
the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713
 2009-08-11 20:47:22 +00:00
Jim Grosbach 841850ed26 Add Thumb2 eh_sjlj_setjmp implementation 
llvm-svn: 78701
 2009-08-11 19:42:21 +00:00
Evan Cheng d4d352c663 80 column violation. 
llvm-svn: 78657
 2009-08-11 08:47:46 +00:00
Owen Anderson 53aa7a960c Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 
llvm-svn: 78610
 2009-08-10 22:56:29 +00:00
Evan Cheng 51cbd2d6c4 Add support to reduce most of 32-bit Thumb2 arithmetic instructions. 
llvm-svn: 78550
 2009-08-10 02:37:24 +00:00
Anton Korobeynikov cfed3005e5 Use subclassing to print lane-like immediates (w/o hash) eliminating 
'no_hash' modifier. Hopefully this will make Daniel happy :)

llvm-svn: 78514
 2009-08-08 23:10:41 +00:00
Evan Cheng 6e130db3b7 Thumb2 32-bit ldm / stm needs .w suffix if submode is ia. 
llvm-svn: 78410
 2009-08-07 21:19:10 +00:00
Evan Cheng b972e5633f It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. 
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361
 2009-08-07 00:34:42 +00:00
David Goodwin b062c236c5 Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary. 
llvm-svn: 78321
 2009-08-06 16:52:47 +00:00
Evan Cheng 7cc6aca1e6 Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode. 
llvm-svn: 78126
 2009-08-04 23:47:55 +00:00
Evan Cheng 03eb0e3c33 Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction. 
llvm-svn: 78030
 2009-08-04 01:41:15 +00:00
Evan Cheng e64f48ba8b Workaround a couple of Darwin assembler bugs. 
llvm-svn: 77781
 2009-08-01 06:13:52 +00:00
Evan Cheng e6e8289d72 Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate. 
llvm-svn: 77764
 2009-08-01 01:43:45 +00:00
Evan Cheng 6ab54fdb0a Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same 
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.

llvm-svn: 77756
 2009-08-01 00:16:10 +00:00
Evan Cheng 9eb3f88048 Thumb2 movcc need .w suffix. 
llvm-svn: 77743
 2009-07-31 22:21:55 +00:00
David Goodwin 0bfc8312c2 Darwin assembler now recognizes "orn", so remove workaround. 
llvm-svn: 77627
 2009-07-30 21:51:41 +00:00
David Goodwin ce774e2383 Darwin assembler now supports "rrx", so remove workaround. 
llvm-svn: 77625
 2009-07-30 21:38:40 +00:00
David Goodwin cab137d294 Add missing D* register clobbers for Thumb-2 call. 
llvm-svn: 77611
 2009-07-30 18:01:09 +00:00
Evan Cheng 175bd14967 Make sure Thumb2 uses the right call instructions. 
llvm-svn: 77507
 2009-07-29 21:26:42 +00:00
Evan Cheng 0d98d8b8b3 - Fix an obvious copy and paste error. 
- Darwin Thumb2 call clobbers r9.

llvm-svn: 77500
 2009-07-29 20:10:36 +00:00
Evan Cheng c6d70ae063 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. 
llvm-svn: 77422
 2009-07-29 02:18:14 +00:00
Evan Cheng c8bed03349 In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
llvm-svn: 77364
 2009-07-28 20:53:24 +00:00
David Goodwin 68bb69d6e3 Remove support for ORN to workaround <rdar://problem/7096522>. 
llvm-svn: 77363
 2009-07-28 20:51:25 +00:00
David Goodwin 865c6298d7 Add workaround for <rdar://problem/7098328>. 
llvm-svn: 77340
 2009-07-28 18:15:38 +00:00
David Goodwin e82862e24e Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag. 
llvm-svn: 77329
 2009-07-28 17:06:49 +00:00
Evan Cheng 780748d565 - More refactoring. This gets rid of all of the getOpcode calls. 
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300
 2009-07-28 05:48:47 +00:00
David Goodwin 57b51d9f82 ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM. 
llvm-svn: 77275
 2009-07-27 23:34:12 +00:00
David Goodwin 007031d1b4 Thumb-2 does not have RSC. 
llvm-svn: 77201
 2009-07-27 16:39:05 +00:00
David Goodwin 782f242fd7 Add ".w" suffix for wide thumb-2 instructions. 
llvm-svn: 77199
 2009-07-27 16:31:55 +00:00
Evan Cheng f3a1fce8ae Change Thumb2 jumptable codegen to one that uses two level jumps: 
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024
 2009-07-25 00:33:29 +00:00
Evan Cheng c64ce30c67 Uh. It would be useful to actually print the operand. 
llvm-svn: 77004
 2009-07-24 20:47:38 +00:00
Evan Cheng 666c912ce3 Make sure thumb2 jumptable entries are aligned. 
llvm-svn: 76986
 2009-07-24 18:20:44 +00:00
David Goodwin cdd405d804 Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen. 
llvm-svn: 76919
 2009-07-24 00:16:18 +00:00
Evan Cheng dc99f07113 Thumb2 does not allow the use of "pc" register as part of the load / store address. 
llvm-svn: 76909
 2009-07-23 23:09:51 +00:00
Evan Cheng 95a73e2eab Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address. 
Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.

llvm-svn: 76889
 2009-07-23 18:26:03 +00:00
David Goodwin 6deba28c6f Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset. 
llvm-svn: 76883
 2009-07-23 17:06:46 +00:00