6572e0f203
Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those.
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llvm-svn: 145927
2011-12-06 09:04:59 +00:00
51416d5f00
test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it.
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FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)
llvm-svn: 145925
2011-12-06 06:48:26 +00:00
e303e24d77
ARM mode 'mul' operand ordering tweak.
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Same as r145922, just for ARM mode.
llvm-svn: 145923
2011-12-06 05:28:00 +00:00
5f143be8c5
Thumb2: MUL two-operand form encoding operand order fix.
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Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
llvm-svn: 145922
2011-12-06 05:03:45 +00:00
bf41eb3a98
Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted.
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llvm-svn: 145921
2011-12-06 04:59:07 +00:00
175c7d0da5
Thumb2 encoding choice correction for PLD.
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Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
llvm-svn: 145919
2011-12-06 04:49:29 +00:00
5bdc0fbabd
test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM.
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MC/MachO assumes x86.
llvm-svn: 145916
2011-12-06 03:56:05 +00:00
5df9096584
LSR: prune undesirable formulae early.
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It's always good to prune early, but formulae that are unsatisfactory
in their own right need to be removed before running any other pruning
heuristics. We easily avoid generating such formulae, but we need them
as an intermediate basis for forming other good formulae.
llvm-svn: 145906
2011-12-06 03:13:31 +00:00
c77830d21e
[arm-fast-isel] Doublewords only require word-alignment.
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rdar://10528060
llvm-svn: 145891
2011-12-06 01:44:17 +00:00
2e05db2fa0
Align ARM constant pool islands via their basic block.
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Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment
is set on the basic block.
This is in preparation of supporting ARM constant pool islands with
different alignments.
llvm-svn: 145890
2011-12-06 01:43:02 +00:00
9105085b4a
Fix ARM handling of tBcc branch relaxation.
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rdar://10069056
llvm-svn: 145885
2011-12-06 01:08:19 +00:00
8abf65a130
Probably not a good idea to convert a single vector load into a memcpy. We
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don't do this now, but add a test case to prevent this from happening in the
future.
Additional test for rdar://9892684
llvm-svn: 145879
2011-12-06 00:19:08 +00:00
19446a07a7
Make the MemCpyOptimizer a bit more aggressive. I can't think of a scenerio
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where this would be bad as the backend shouldn't have a problem inlining small
memcpys.
rdar://10510150
llvm-svn: 145865
2011-12-05 22:37:00 +00:00
b8c719ccc6
Tweak ADDrr fix. Bad check for explicit .w
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llvm-svn: 145863
2011-12-05 22:27:04 +00:00
8b5e92577b
Update tests for r145860. Add a few new ones.
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llvm-svn: 145861
2011-12-05 22:21:28 +00:00
20cee2eba1
Add definitions of 64-bit extract and insert instrucions and make
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PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.
llvm-svn: 145853
2011-12-05 21:26:34 +00:00
ec9ba98299
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
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rdar://10529348
llvm-svn: 145851
2011-12-05 21:06:26 +00:00
34e3df76f9
Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 and
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O32 with relocation-model=pic too.
llvm-svn: 145850
2011-12-05 21:03:03 +00:00
fdf9e1587a
ARM assembly parsing for the rest of the VMUL data type aliases.
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Finish up rdar://10522016.
llvm-svn: 145846
2011-12-05 20:29:59 +00:00
97a6028b3a
Add test case - this input used to crash because of duplicate generation of SPILL_CRs
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llvm-svn: 145820
2011-12-05 17:55:22 +00:00
8f6834dfa5
enable PPC register scavenging by default (update tests and remove some FIXMEs)
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llvm-svn: 145819
2011-12-05 17:55:17 +00:00
e18c72689c
remove wasted space for extra bit copies of CR2 subregs
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llvm-svn: 145817
2011-12-05 17:55:06 +00:00
e6efe405de
test/CodeGen/X86/pointer-vector.ll: Add explicit -mtriple=i686-linux.
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llvm-svn: 145805
2011-12-05 07:54:57 +00:00
3924cb0267
Add support for vectors of pointers.
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llvm-svn: 145801
2011-12-05 06:29:09 +00:00
965e0c6de2
Emit the ctors in the proper order on ARM/EABI.
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Maybe some targets should use this as well.
Patch by Evgeniy Stepanov!
llvm-svn: 145781
2011-12-03 23:49:37 +00:00
6dae604f50
Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since
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AnalyzeBranch doesn't change the successor, just the order.
llvm-svn: 145779
2011-12-03 21:24:48 +00:00
006e43bcc0
Check for stack space more intelligently.
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libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit. This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit. This should result in lesser calls to __morestack.
llvm-svn: 145766
2011-12-03 09:32:07 +00:00
165ca1d4ba
Fix a bug in the x86-32 code generated for segmented stacks.
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Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp. This isn't correct since __morestack expects the call
to be followed directly by a ret.
This commit also adjusts the relevant test-case.
llvm-svn: 145765
2011-12-03 09:21:07 +00:00
ec3b77e00d
[arm-fast-isel] Unaligned stores of floats require special care.
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rdar://10510150
llvm-svn: 145742
2011-12-03 02:21:57 +00:00
e03fe83d98
Fixed deadstoreelimination bug where negative indices were incorrectly causing the optimisation to occur
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Turns out long long + unsigned long long is unsigned. Doh!
Fixes http://llvm.org/bugs/show_bug.cgi?id=11455
llvm-svn: 145731
2011-12-03 00:04:30 +00:00
0155a63513
Add support for constant folding the pow intrinsic.
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rdar://10514247
llvm-svn: 145730
2011-12-03 00:00:03 +00:00
430f917fbe
Test cases for 64-bit multiplication and division.
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llvm-svn: 145717
2011-12-02 22:31:36 +00:00
bbc5555bee
Fix test cases to use FileCheck.
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llvm-svn: 145716
2011-12-02 22:28:09 +00:00
7276397f41
ARM tests for VLD1 single lane w/ writeback.
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llvm-svn: 145713
2011-12-02 22:03:52 +00:00
9fd0e55e91
[arm-fast-isel] After promoting a function parameter be sure to update the
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argument value type. Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467
llvm-svn: 145701
2011-12-02 20:25:18 +00:00
d87f7af1f3
specify cpu for test to fix failure on some darwin systems with a g4+ cpu
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llvm-svn: 145699
2011-12-02 19:38:17 +00:00
e7dcbc8691
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
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Add the 16-bit lane variants while I'm at it.
llvm-svn: 145693
2011-12-02 18:52:30 +00:00
abeb79eee3
Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors.
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llvm-svn: 145680
2011-12-02 07:16:01 +00:00
9286705955
adjust the instruction ordering in some PPC tests: changes due to postRA haz. rec.
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llvm-svn: 145678
2011-12-02 04:58:12 +00:00
3367123b12
Prevent library calls from being folded if -fno-builtin has been specified.
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rdar://10500969
llvm-svn: 145639
2011-12-01 22:14:50 +00:00
fdddc27143
Improved fix for abs(val) != 0 to check other similar case. Also fixed style issues and confusing comment
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llvm-svn: 145618
2011-12-01 19:13:26 +00:00
9da7f305a4
For 64-bit the rest of the general regs are ok for the q constraint. Make
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sure we can emit both the high and low versions of those registers.
Fixes rdar://10392864
llvm-svn: 145579
2011-12-01 08:12:41 +00:00
d61887dd0a
Pass AVX vectors which are arguments to varargs functions on the stack. <rdar://problem/10463281>.
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llvm-svn: 145573
2011-12-01 04:49:21 +00:00
3b7f35bf08
Removed use of grep from test and moved it to be with other icmp tests
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llvm-svn: 145570
2011-12-01 04:35:26 +00:00
bc5c524b71
Added instcombine pattern to spot comparing -val or val against 0.
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(val != 0) == (-val != 0) so "abs(val) != 0" becomes "val != 0"
Fixes <rdar://problem/10482509>
llvm-svn: 145563
2011-12-01 03:58:40 +00:00
9430e284a9
Support for encoding all FMA4 instructions and tablegen patterns for all
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remaining FMA4 instructions and intrinsics with tests.
llvm-svn: 145525
2011-11-30 22:09:42 +00:00
6cff9df298
Make GlobalMerge honor the preferred alignment on globals without an explicitly specified alignment.
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<rdar://problem/10497732>.
llvm-svn: 145523
2011-11-30 21:54:15 +00:00
7d8517b1d4
Add some tests for all-lanes VLD1 parsing.
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llvm-svn: 145512
2011-11-30 19:37:38 +00:00
0a1801015c
Add test arch to make it pass on non x86 targets
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llvm-svn: 145498
2011-11-30 17:34:28 +00:00
66427bcce9
Add a tripple to the test
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llvm-svn: 145489
2011-11-30 11:20:56 +00:00
Craig Topper