Commit Graph

402092 Commits

Author SHA1 Message Date
Simon Pilgrim ac1c0dd317 [ADT] Add some basic APInt::isPowerOf2() unit test coverage 2021-10-18 15:01:28 +01:00
rkayaith d5429a13da [mlir][python] Add 'loc' property to ops
Add a read-only `loc` property to Operation and OpView

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D111972
2021-10-18 16:01:12 +02:00
Raphael Isemann 366fb53948 [lldb] Fix missing dependency on libc++ from LLDB test suite on non-Darwin platforms
Right now we only set a dependency on libc++ when the host is Darwin, which
means that libc++ in the build directory is in some undefined state when running
the test suite (it can be fully built, out-of-date or missing). Depending on
whether we have a system libc++ (which LLDB also supports running the libc++
tests against), the outcome is that we sometimes skip the libc++ tests or we run
the tests against a mix of ToT-libc++/system-libc++ (e.g., we compile against
the ToT-libc++ headers and link against the system libc++ library).

This can be demonstrated via `export LIT_FILTER=TestDataFormatterLibcxxSet ninja
check-lldb-api` (or any other libc++ test) and then gradually building parts of
libc++ in the same build (which will slowly change the test behaviour from
`UNSUPPORTED` to various failures to passing depending on how much of libcxx is
built at test time).

Note that this effectively re-enables the (unintentionally) disabled libc++
formatter tests on Linux. Don't revert this if it breaks a libc++ LLDB test,
instead please @skipIf decorate the failing test (as it was probably already
failing before this commit).

Reviewed By: labath

Differential Revision: https://reviews.llvm.org/D111981
2021-10-18 15:59:34 +02:00
Peter Waller ee7ca88a3e [InstCombine][DebugInfo] Remove superflous assertion, add test [2/2]
Accidentally committed a prior version of this patch. This is the
correct version.
2021-10-18 13:48:23 +00:00
Kerry McLaughlin ac4e01ea0e [SVE][CodeGen] Fix predicate for add/sub + element count patterns
The patterns added in D111441 should use the HasSVEorStreamingSVE
predicate. This changes one incorrect use of HasSVE with the new
patterns.
2021-10-18 14:42:29 +01:00
Andrew Wei f5056c8c16 [AArch64] Improve shuffle vector by using wider types
Try to widen element type to get a new mask value for a better permutation
sequence, so that we can use NEON shuffle instructions, such as zip1/2,
UZP1/2, TRN1/2, REV, INS, etc.
For example:
  shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 2, i32 3>
is equivalent to:
  shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 3, i32 1>
Finally, we can get:
  mov     v0.d[0], v1.d[1]

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D111619
2021-10-18 21:24:45 +08:00
Pavel Labath 1ef6bd9b1b [lldb] Delete TestStandardUnwind
It's been broken (not failing, but not testing anything either) for
quite some time now, and nobody noticed. It also (by design) tests
stepping through libc code, which makes it completely non-hermetic.

It's not worth reviving such a test.
2021-10-18 15:22:10 +02:00
Sanjay Patel 2a3cc4d461 [Analysis] add utility function for unary shuffle mask creation
This is NFC-intended for the callers. Posting in case there are
other potential users that I missed.
I would also use this from VectorCombine in a patch for:
https://llvm.org/PR52178 ( D111901 )

Differential Revision: https://reviews.llvm.org/D111891
2021-10-18 09:00:39 -04:00
Balazs Benics 72d04d7b2b [analyzer] Allow matching non-CallExprs using CallDescriptions
Fallback to stringification and string comparison if we cannot compare
the `IdentifierInfo`s, which is the case for C++ overloaded operators,
constructors, destructors, etc.

Examples:
  { "std", "basic_string", "basic_string", 2} // match the 2 param std::string constructor
  { "std", "basic_string", "~basic_string" }  // match the std::string destructor
  { "aaa", "bbb", "operator int" } // matches the struct bbb conversion operator to int

Reviewed By: martong

Differential Revision: https://reviews.llvm.org/D111535
2021-10-18 14:57:24 +02:00
Balazs Benics 3ec7b91141 [analyzer][NFC] Refactor CallEvent::isCalled()
Refactor the code to make it more readable.

It will set up further changes, and improvements to this code in
subsequent patches.
This is a non-functional change.

Reviewed By: martong

Differential Revision: https://reviews.llvm.org/D111534
2021-10-18 14:57:24 +02:00
Balazs Benics 5644d15257 [analyzer][NFC] Add unittests for CallDescription and split the old ones
This NFC change accomplishes three things:
1) Splits up the single unittest into reasonable segments.
2) Extends the test infra using a template to select the AST-node
   from which it is supposed to construct a `CallEvent`.
3) Adds a *lot* of different tests, documenting the current
   capabilities of the `CallDescription`. The corresponding tests are
   marked with `FIXME`s, where the current behavior should be different.

Both `CXXMemberCallExpr` and `CXXOperatorCallExpr` are derived from
`CallExpr`, so they are matched by using the default template parameter.
On the other hand, `CXXConstructExpr` is not derived from `CallExpr`.
In case we want to match for them, we need to pass the type explicitly
to the `CallDescriptionAction`.

About destructors:
They have no AST-node, but they are generated in the CFG machinery in
the analyzer. Thus, to be able to match against them, we would need to
construct a CFG and walk on that instead of simply walking the AST.

I'm also relaxing the `EXPECT`ation in the
`CallDescriptionConsumer::performTest()`, to check the `LookupResult`
only if we matched for the `CallDescription`.
This is necessary to allow tests in which we expect *no* matches at all.

Reviewed By: martong

Differential Revision: https://reviews.llvm.org/D111794
2021-10-18 14:57:24 +02:00
Sylvestre Ledru cbf778a592 Remove also Block-ABI-Apple.txt from the Makefile 2021-10-18 14:56:23 +02:00
Simon Pilgrim f041338153 [X86][Costmodel] Add SSE2 sub-128bit vXi32/f32 stride 2 interleaved store costs
Differential Revision: https://reviews.llvm.org/D111941
2021-10-18 13:46:10 +01:00
Simon Pilgrim c850d5c5c8 [X86][Costmodel] Add SSE2 sub-128bit vXi8/16 stride 2 interleaved store costs
Differential Revision: https://reviews.llvm.org/D111941
2021-10-18 13:15:14 +01:00
Pavel Labath b37efed957 [lldb] Fix PDB/compilands.test for a3939e1 2021-10-18 14:11:47 +02:00
@vladaindjic 59a994e8da [OpenMP][OMPT] thread_num determination for programs with explicit tasks
__ompt_get_task_info_internal is now able to determine the right value of the
“thread_num” argument during the execution of an explicit task.

During the execution of a while loop that iterates over the ancestor tasks
hierarchy, the “prev_team” variable was always set to “team” variable at the
beginning of each loop iteration.

Assume that the program contains a parallel region which encloses an explicit
task executed by the worker thread of the region. Also assume that the tool
inquires the “thread_num” of a worker thread for the implicit task that
corresponds to the region (task at “ancestor_level == 1”) and expects to
receive the value of “thread_num > 0”.
After the loop finishes, both “team” and “prev_team” variables are equal and
point to the team information of the parallel region.
The “thread_num” is set to “prev_team->t.t_master_tid”, that is equal to
“team->t.t_master_tid”. In this case, “team->t.t_master_tid” is 0, since
the master thread of the region is the initial master thread of the program.
This leads to a contradiction.

To prevent this, “prev_team” variable is set to “team” variable only at the
time when the loop that has already encountered the implicit task (“taskdata”
variable contains the information about an implicit task) continues iterating
over the implicit task’s ancestors, if any.

After the mentioned loop finishes, the “prev_team” variable might be equal to
NULL. This means that the task at requested “ancestor_level” belongs to the
innermost parallel region, so the “thread_num” will be determined by calling
the “__kmp_get_tid”.

To prove that this patch works, the test case “explicit_task_thread_num.c” is
provided.
It contains the example of the program explained earlier in the summary.

Differential Revision: https://reviews.llvm.org/D110473
2021-10-18 13:54:22 +02:00
Joachim Protze c93fb143b9 [OpenMP][Tests][NFC] Work around ICC bug
Older intel compilers miss the privatization of nested loop variables for
doacross loops. Declaring the variable in the loop makes the test more
robust.
2021-10-18 13:54:15 +02:00
Joachim Protze 5918688248 [OpenMP][Tests][NFC] Flagging OMPT tests as XFAIL for Intel compilers
With Intel 19 compiler the teams tests fail to link while trying to link
liboffload.
2021-10-18 13:50:03 +02:00
Simon Pilgrim 3b3509b3cb [Sema] haveSameParameterTypes - replace repeated isNull() test with assertions
As reported on https://pvs-studio.com/en/blog/posts/cpp/0771/ (Snippet 2) - (and mentioned on rGdc4259d5a38409) we are repeating the T1.isNull() check instead of checking T2.isNull() as well, and at this point neither should be null - so we're better off with an assertion.

Differential Revision: https://reviews.llvm.org/D107347
2021-10-18 12:36:44 +01:00
Stephen Tozer b9ca73e1a8 [DebugInfo] Correctly handle arrays with 0-width elements in GEP salvaging
Fixes an issue where GEP salvaging did not properly account for GEP
instructions which stepped over array elements of width 0 (effectively a
no-op). This unnecessarily produced long expressions by appending
`... + (x * 0)` and potentially extended the number of SSA values used
in the dbg.value. This also erroneously triggered an assert in the
salvage function that the element width would be strictly positive.
These issues are resolved by simply ignoring these useless operands.

Reviewed By: aprantl

Differential Revision: https://reviews.llvm.org/D111809
2021-10-18 12:01:12 +01:00
Peter Waller c0782ba898 [AArch64][SVE][CodeGen] Add tests for RSHRN{T,B} instructions
Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D111735
2021-10-18 11:00:01 +00:00
Peter Waller c4603a8a43 [InstCombine][DebugInfo] Remove superflous assertion, add test
When this code was added, an unnecessary assertion slipped in which we
now hit in real code.

Add a test to defend against it firing again.
2021-10-18 11:00:01 +00:00
Jay Foad d55db4b033 [AMDGPU] Remove unused VirtRegMap analysis. NFC. 2021-10-18 11:55:40 +01:00
Jeremy Morse c4ede6d608 [DebugInfo][InstrRef] Avoid a crash during DBG_PHI maintenence
With D110105, the isDebug flag for register uses is now a proxy for whether
the instruction is a debug instruction; that causes DBG_PHIs to have their
operands updated by calls to updateDbgUsersToReg, which is the correct
behaviour. However: that function only expects to receive DBG_VALUE
instructions and asserts such.

This patch splits the updating-action into a lambda, and applies it to the
appropriate operands for each kind of debug instruction. Tested with an
ARM test that stimulates this function: I've added some DBG_PHI
instructions that should be updated in the same way as DBG_VALUEs.

Differential Revision: https://reviews.llvm.org/D108641
2021-10-18 11:52:45 +01:00
Michał Górny d8bc7e40ce [lldb] [lldb-server] Refactor ConnectToRemote()
Refactor ConnectToRemote() to improve readability and make future
changes easier:

1. Replace static buffers with std::string.
2. When handling errors, prefer reporting the actual error over dumb
   'connection status is not success'.
3. Move host/port parsing directly into reverse_connection condition
   that is its only user, and simplify it to make its purpose (verifying
   that a valid port is provided) clear.
4. Use llvm::errs() and llvm::outs() instead of fprintf().

Differential Revision: https://reviews.llvm.org/D11196
2021-10-18 12:17:43 +02:00
Max Kazantsev baad10c09e Revert "[NFC] [LoopPeel] Change the way DT is updated for loop exits"
This reverts commit fa16329ae0.

See comments in discussion. Merged by mistake, not entirely getting what
the problem was.
2021-10-18 17:14:11 +07:00
Shivam Gupta c773f6501d [NFC] Remove Block-ABI-Apple.txt
This file was rewritten in rst format in clang/docs/Block-ABI-Apple.rst
2021-10-18 15:42:31 +05:30
Lasse Folger ee691fbc3d [lldb][NFC] clang format change
clang format on some demangling files

Reviewed By: teemperor

Differential Revision: https://reviews.llvm.org/D111934
2021-10-18 12:00:32 +02:00
Pavel Labath d914aa4ead [lldb] Fix SymbolFilePDBTests for a3939e1 2021-10-18 11:59:01 +02:00
Jan Svoboda a2d805c020 [clang][modules] Delay creating `IdentifierInfo` for names of explicit modules
When using explicit Clang modules, some declarations might unexpectedly become invisible.

This is caused by the mechanism that loads PCM files passed via `-fmodule-file=<path>` and creates an `IdentifierInfo` for the module name. The `IdentifierInfo` creation takes place when the `ASTReader` is in a weird state, with modules that are loaded but not yet set up properly. This patch delays the creation of `IdentifierInfo` until the `ASTReader` is done with reading the PCM.

Note that the `-fmodule-file=<name>=<path>` form of the argument doesn't suffer from this issue, since it doesn't create `IdentifierInfo` for the module name.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D111543
2021-10-18 11:50:29 +02:00
Jay Foad a129932b0d [AMDGPU] Add link to bug 2021-10-18 10:33:42 +01:00
Jeremy Morse ea970661dc Fix signed/unsigned comparison after b5426ced71
gcc11 warns that this counter causes a signed/unsigned comaprison when it's
later compared with a SmallVector::difference_type. gcc appears to be
correct, clang does not warn one way or the other.
2021-10-18 10:28:52 +01:00
Jay Foad 012248b0bc Remove the verifyAfter mechanism that was replaced by D111397
Differential Revision: https://reviews.llvm.org/D111872
2021-10-18 10:26:46 +01:00
Jay Foad 36deb9a670 Add new MachineFunction property FailsVerification
TargetPassConfig::addPass takes a "bool verifyAfter" argument which lets
you skip machine verification after a particular pass. Unfortunately
this is used in generic code in TargetPassConfig itself to skip
verification after a generic pass, only because some previous target-
specific pass damaged the MIR on that specific target. This is bad
because problems in one target cause lack of verification for all
targets.

This patch replaces that mechanism with a new MachineFunction property
called "FailsVerification" which can be set by (usually target-specific)
passes that are known to introduce problems. Later passes can reset it
again if they are known to clean up the previous problems.

Differential Revision: https://reviews.llvm.org/D111397
2021-10-18 10:26:46 +01:00
Piotr Sobczak d869921004 [AMDGPU] Add patterns for i8/i16 local atomic load/store
Add patterns for i8/i16 local atomic load/store.

Added tests for new patterns.

Copied atomic_[store/load]_local.ll to GlobalISel directory.

Differential Revision: https://reviews.llvm.org/D111869
2021-10-18 11:23:10 +02:00
Kai Luo 9635168083 [AIX][cmake] Set atomics related macros when build with xlclang
Set `HAVE_CXX_ATOMICS_WITHOUT_LIB` or `HAVE_LIBATOMIC` when build LLVM with xlclang. With these macros set, libraries like libLLVMSupport are able to know whether it's necessary to add `-latomic` to dependent system libs. If `HAVE_LIBATOMIC` is set, `llvm-config --system-libs` appends `-latomic` to its output.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D111782
2021-10-18 09:18:05 +00:00
Fraser Cormack 3d850d03ae [SelectionDAG] Fix illegal widening of scalable-vector loads
The process of widening simple vector loads attempts to use a load of a
wider vector type if the original load is sufficiently aligned to avoid
memory faults.

However this optimization is only legal when performed on fixed-length
vector types. For scalable vector types this is invalid (unless vscale
happens to be 1).

This patch does increase the likelihood of compiler crashes (from
`FindMemType` failing to find a suitable type) but this now better
matches how widening non-simple loads, insufficiently-aligned loads, and
scalable-vector stores are handled.

Patches will be introduced later by which loads and stores can be
widened on targets with support for masked or predicated operations.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D111885
2021-10-18 10:00:00 +01:00
Luo, Yuanke 942536ac08 [X86] Prefer VEX encoding in X86 assembler.
This patch is to order the AVX instructions ahead of AVX512 instructions
in the matching table so that the AVX instructions can be matched first.
Thanks Craig and Shengchen for the idea.

Differential Revision: https://reviews.llvm.org/D111538
2021-10-18 16:54:11 +08:00
Michał Górny 239b4d62b6 [lldb] [Utility] Remove Status::WasInterrupted() along with its only use
Remove Status::WasInterrupted() that checks whether the underlying error
code matches EINTR.  ProcessGDBRemote::ConnectToDebugserver() is its
only call site, and it does not seem correct there.  After all, EINTR
is precisely when we want to retry, not stop retrying.  Furthermore,
it should not really matter since we should be catching EINTR
immediately via llvm::sys::RetryAfterSignal() but that's another story.

Differential Revision: https://reviews.llvm.org/D111908
2021-10-18 10:50:25 +02:00
Florian Hahn e9ff7d250e
[AArch64][GISel] Add 8/16 bit uaddo lowering tests.
Precommit tests for D111888.
2021-10-18 09:48:43 +01:00
Stanislav Mekhanoshin 7cdb1df8c7 [AMDGPU] Divergence driven selection for fused bitlogic
The change adds divergence predicates for fused logical operations.
The problem with selecting a scalar fused op such as S_NOR_B32 is
that it does not have a VALU counterpart and will be split in
moveToVALU. At the same time it prevents selection of a better
opcode on the VALU side (such as V_OR3_B32) which does not have a
counterpart on SALU side.

XNOR opcodes are left as is and selected as scalar to get advantage
of the SIInstrInfo::lowerScalarXnor() code which can commute
operations to keep one of two opcodes on SALU if possible. See
xnor.ll test for this.

Differential Revision: https://reviews.llvm.org/D111907
2021-10-18 01:44:25 -07:00
Adrian Kuegel 605efd5dd5 Fix bazel build.
This is a temporary fix, better would be to avoid including
llvm/Option/ArgList.h from a Support source file.

Differential Revision: https://reviews.llvm.org/D111974
2021-10-18 10:22:41 +02:00
Pavel Labath a3939e159f [lldb] Return StringRef from PluginInterface::GetPluginName
There is no reason why this function should be returning a ConstString.

While modifying these files, I also fixed several instances where
GetPluginName and GetPluginNameStatic were returning different strings.

I am not changing the return type of GetPluginNameStatic in this patch, as that
would necessitate additional changes, and this patch is big enough as it is.

Differential Revision: https://reviews.llvm.org/D111877
2021-10-18 10:14:42 +02:00
Raphael Isemann de4d2f80b7 Fix cyclic header dependency between Support<->Option due to RISCVISAInfo
This was introduced in D105168 which added RISCVISAInfo.h.
2021-10-18 10:06:11 +02:00
Haojian Wu 6e63f96e11 [Parse] Improve diagnostic and recovery when there is an extra override in the outline method definition.
The clang behavior was poor before this patch:

```
void B::foo() override {}
// Before: clang emited "expcted function body after function
// declarator", and skiped all contents until it hits a ";", the
// following function f() is discarded.

// VS

// Now "override is not allowed" with a remove fixit, and following f()
// is retained.
void f();
```

Differential Revision: https://reviews.llvm.org/D111883
2021-10-18 10:00:21 +02:00
Jingu Kang 3f0b178de2 [AArch64] Fixed a bug on AArch64MIPeepholeOpt
Create new virtual register for the definition of new AND instruction and
replace old register by the new one to keep SSA form.

Differential Revision: https://reviews.llvm.org/D109963
2021-10-18 08:55:42 +01:00
Bing1 Yu f383c53311 [MachineSink] Compile time improvement for large testcases which has many kill flags
We did a experiment and observed dramatic decrease on compilation time which spent on clearing kill flags.
Before:
Number of BasicBlocks:33357
Number of Instructions:162067
Number of Cleared Kill Flags:32869
Time of handling kill flags(ms):1.607509e+05

After:
Number of BasicBlocks:33357
Number of Instructions:162067
Number of Cleared Kill Flags:32869
Time of handling kill flags:3.987371e+03

Reviewed By: MatzeB

Differential Revision: https://reviews.llvm.org/D111688
2021-10-18 15:44:07 +08:00
Qiu Chaofan 67c64d8337 [PowerPC] Implement scheduling model for Power10
Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D110855
2021-10-18 15:27:49 +08:00
Lang Hames 8b7cc93e9d [JITLink] Add comments, rename types for visitExistingEdges utility.
The "Fixers" name was a hangover from an earlier draft of the patch. "Visitors"
fits the function name(s).
2021-10-17 22:59:44 -07:00
Max Kazantsev fa16329ae0 [NFC] [LoopPeel] Change the way DT is updated for loop exits
When peeling a loop, we assume that the latch has a `br` terminator and
that all loop exits are either terminated with an `unreachable` or have
a terminating deoptimize call. So when we peel off the 1st iteration, we
change the IDom of all loop exits to the peeled copy of
`NCD(IDom(Exit), Latch)`. This works now, but if we add logic to support
loops with exits that are followed by a block with an `unreachable` or a
terminating deoptimize call, changing the exit's idom wouldn't be enough
and DT would be broken.

For example, let `Exit1` and `Exit2` are loop exits, and each of them
unconditionally branches to the same `unreachable` terminated block. So
neither of the exits dominates this unreachable block. If we change the
IDoms of the exits to some peeled loop block, we don't update the
dominators of the unreachable block. Currently we just don't get to the
peeling logic, saying that we can't peel such loops.

With this NFC we just insert edges from cloned exiting blocks to their
exits after peeling each iteration (we accumulate the insertion updates
and then after peeling apply the updates to DT).

This patch was a part of D110922.

Patch by Dmitry Makogon!

Differential Revision: https://reviews.llvm.org/D111611
Reviewed By: mkazantsev
2021-10-18 10:23:05 +07:00