ac17552138
s/SequeuentiallyConsistent/SequentiallyConsistent/g
...
llvm-svn: 139481
2011-09-11 15:50:05 +00:00
bdf62403d9
Fix verb tense agreement.
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llvm-svn: 139480
2011-09-11 15:30:08 +00:00
b873b18721
CR fixes per Bruno's request.
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Undo the changes from r139285 which added custom lowering to vselect.
Add tablegen lowering for vselect.
llvm-svn: 139479
2011-09-11 15:02:23 +00:00
501f541b45
Really un-XFAIL the testcase, like I said I would in r139458.
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llvm-svn: 139459
2011-09-10 02:02:27 +00:00
7f50e00203
r139454 activates an assert in a case where we were doing the right thing anyway. Make that explicit, and un-XFAIL the testcase.
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llvm-svn: 139458
2011-09-10 02:01:42 +00:00
74996f2a79
Fix the asserts in lib/Target/X86/X86ELFWriterInfo.cpp and
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lib/ExecutionEngine/MCJIT/MCJIT.cpp from:
assert("error");
to:
assert(0 && "error");
llvm-svn: 139456
2011-09-10 01:42:07 +00:00
d9917bef6c
Fixed an assert from:
...
assert("not implemented for target shuffle node");
to:
assert(0 && "not implemented for target shuffle node");
This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.
llvm-svn: 139454
2011-09-10 01:26:21 +00:00
c7868bf064
[disable-iv-rewrite] Allow WidenIV to handle NSW/NUW operations
...
better.
Don't immediately give up when an add operation can't be trivially
sign/zero-extended within a loop. If it has NSW/NUW flags, generate a
new expression with sign extended (non-recurrent) operand. As before,
if SCEV says that all sign extends are loop invariant, then we can
widen the operation.
llvm-svn: 139453
2011-09-10 01:24:17 +00:00
a51d74fc35
Set NSW/NUW flags on SCEVAddExpr when the operation is flagged as
...
such.
I'm doing this now for completeness because I can't think of/remember
any reason that it was left out. I'm not sure it will help anything,
but if we don't do it we need to explain why in comments.
llvm-svn: 139450
2011-09-10 01:09:50 +00:00
78a812bf2d
Fix asserts in CodeGen from:
...
assert("error");
to:
assert(0 && "error");
llvm-svn: 139449
2011-09-10 01:07:54 +00:00
b908b7af31
Thumb2 parsing and encoding for MOV(immediate).
...
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
llvm-svn: 139440
2011-09-10 00:15:36 +00:00
5624707684
Fix test cases.
...
Generate code for Mips32r1 unless a Mips32r2 feature is tested.
llvm-svn: 139433
2011-09-09 23:14:58 +00:00
53db43b560
LDM writeback is not allowed if Rn is in the target register list.
...
llvm-svn: 139432
2011-09-09 23:13:33 +00:00
eb3f0fbdce
Fix an ambiguously nested if.
...
llvm-svn: 139431
2011-09-09 23:13:02 +00:00
93cd31869b
Fix buildbot breakage caused by r139415. I missed one instance of a manually create ARM::tB.
...
llvm-svn: 139429
2011-09-09 23:05:14 +00:00
5bfb0e0a85
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
...
llvm-svn: 139422
2011-09-09 22:24:36 +00:00
8b983d9773
O64 will not be supported.
...
llvm-svn: 139421
2011-09-09 22:22:48 +00:00
be159b5f2d
Make F31 and D15 non-reserved registers.
...
llvm-svn: 139420
2011-09-09 22:11:26 +00:00
e74e0c8020
tidy up a bit
...
llvm-svn: 139419
2011-09-09 22:06:59 +00:00
29cfe6c368
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
...
llvm-svn: 139415
2011-09-09 21:48:23 +00:00
8726d330f1
Update Clang AST attribute reader tblgen generation to match with ASTReader change
...
llvm-svn: 139414
2011-09-09 21:37:29 +00:00
9d5f9278e3
Mips32 does not reserve even-numbered floating point registers.
...
llvm-svn: 139412
2011-09-09 21:31:46 +00:00
b7910b79f5
Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897.
...
llvm-svn: 139407
2011-09-09 21:04:06 +00:00
4444daeec5
Drop support for Mips1 and Mips2.
...
llvm-svn: 139405
2011-09-09 20:45:50 +00:00
de838daefd
Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type
...
llvm-svn: 139400
2011-09-09 20:29:17 +00:00
62c33955e2
Thumb2 assembly parsing and encoding for MLA and MLS.
...
llvm-svn: 139399
2011-09-09 20:24:45 +00:00
eee3fca1c0
Don't tack "Instruction not interpretable yet!" onto the end of
...
the instruction.
llvm-svn: 139398
2011-09-09 20:22:48 +00:00
b4c32d92ea
Thumb2 assembly parsing and encoding for MCR, MCR2, MCRR, MCRR2.
...
llvm-svn: 139397
2011-09-09 20:19:28 +00:00
54175d519e
Tidy up formatting a bit.
...
llvm-svn: 139396
2011-09-09 20:17:49 +00:00
89b1775256
Thumb2 assembly parsing and encoding for LSL.
...
llvm-svn: 139395
2011-09-09 20:05:38 +00:00
2119a62aae
Thumb2 assembly parsing and encoding for LDRT.
...
llvm-svn: 139393
2011-09-09 20:02:15 +00:00
9b11580719
Thumb2 assembly parsing and encoding for LDRSHT.
...
llvm-svn: 139392
2011-09-09 20:01:18 +00:00
d2165b829f
Thumb2 assembly parsing and encoding for LDRSH.
...
llvm-svn: 139391
2011-09-09 19:54:30 +00:00
f1b71de4ea
Thumb2 assembly parsing and encoding for LDRSBT.
...
llvm-svn: 139390
2011-09-09 19:49:06 +00:00
779a2bee7b
Thumb2 assembly parsing and encoding for LDRSB.
...
llvm-svn: 139389
2011-09-09 19:42:40 +00:00
5af572426d
Thumb2 assembly parsing and encoding for LDRH.
...
llvm-svn: 139386
2011-09-09 19:13:53 +00:00
732f90a61c
Shuffle a bit.
...
llvm-svn: 139385
2011-09-09 19:09:54 +00:00
d22a1c6c95
Drop support for Allegrex. Allegrex implements a variant of Mips2.
...
llvm-svn: 139383
2011-09-09 19:00:51 +00:00
a05627ebaf
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
...
llvm-svn: 139381
2011-09-09 18:37:27 +00:00
278bf02581
Reapply r139247: Cache intermediate results during traceSiblingValue.
...
In some cases such as interpreters using indirectbr, the CFG can be very
complicated, and live range splitting may be forced to insert a large
number of phi-defs. When that happens, traceSiblingValue can spend a
lot of time zipping around in the CFG looking for defs and reloads.
This patch causes more information to be cached in SibValues, and the
cached values are used to terminate searches early. This speeds up
spilling by 20x in one interpreter test case. For more typical code,
this is just a 10% speedup of spilling.
The previous version had bugs that caused miscompilations. They have
been fixed.
llvm-svn: 139378
2011-09-09 18:11:41 +00:00
465f42ff67
Comment formatting.
...
llvm-svn: 139375
2011-09-09 17:35:10 +00:00
24a674bfc7
Update docs to reflect recent addition of new CompileUnit elements.
...
llvm-svn: 139374
2011-09-09 17:07:15 +00:00
a042ed5cae
Add FIXME.
...
llvm-svn: 139371
2011-09-09 16:45:31 +00:00
ba60b04148
Mark the eh.typeid.for intrinsic as being 'const', which it is inside
...
any given function. As pointed out by John McCall, this is needed to
have redundant eh.typeid.for tests be eliminated in the presence of
cleanups.
llvm-svn: 139360
2011-09-09 07:50:37 +00:00
e812f9eed5
Add disassembler test for Intel syntax. Tests r139353.
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llvm-svn: 139356
2011-09-09 06:35:44 +00:00
5d5134014f
Fix handling of Intel syntax disassembling of movs and stos to stop being blank. Also fixed scas, and cmps to always print size suffix in Intel syntax since its abiguous without arguments. Fixes PR10875.
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llvm-svn: 139353
2011-09-09 05:40:53 +00:00
df1df7edf1
Change default target architecture from Mips1 to Mips32r1 in preparation for
...
removing support for Mips1 and Mips2.
This change and the ones that follow have been discussed with and approved by
Bruno.
llvm-svn: 139344
2011-09-09 01:13:27 +00:00
eba0b40384
Remove dead code.
...
llvm-svn: 139343
2011-09-09 00:22:05 +00:00
940b598f6f
Fix release build:
...
MachOObjectFile.cpp:524: error: unused variable 'NumLoadCommands' [-Wunused-variable]
llvm-svn: 139341
2011-09-09 00:16:50 +00:00
d5f2d8c341
gold plugin: report errors occured in lto_module_create_from_*
...
llvm-svn: 139340
2011-09-09 00:14:04 +00:00
Nick Lewycky