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22 Commits

Author SHA1 Message Date
Krzysztof Parzyszek 60aed6a4e5 [Hexagon] Add prev65 subtarget feature 
There was a change to trap1 instruction between v62 and v65. This
feature will allow the assembler/disassembler to handle different
variants depending on the CPU version.
 2020-01-17 09:27:27 -06:00
Krzysztof Parzyszek 8ee2d16896 [Hexagon] Add a target feature to disable compound instructions 
This affects the following instructions:
Tag: M4_mpyrr_addr     Syntax: Ry32 = add(Ru32,mpyi(Ry32,Rs32))
Tag: M4_mpyri_addr_u2  Syntax: Rd32 = add(Ru32,mpyi(#u6:2,Rs32))
Tag: M4_mpyri_addr     Syntax: Rd32 = add(Ru32,mpyi(Rs32,#u6))
Tag: M4_mpyri_addi     Syntax: Rd32 = add(#u6,mpyi(Rs32,#U6))
Tag: M4_mpyrr_addi     Syntax: Rd32 = add(#u6,mpyi(Rs32,Rt32))
Tag: S4_addaddi        Syntax: Rd32 = add(Rs32,add(Ru32,#s6))
Tag: S4_subaddi        Syntax: Rd32 = add(Rs32,sub(#s6,Ru32))
Tag: S4_or_andix       Syntax: Rx32 = or(Ru32,and(Rx32,#s10))
Tag: S4_andi_asl_ri    Syntax: Rx32 = and(#u8,asl(Rx32,#U5))
Tag: S4_ori_asl_ri     Syntax: Rx32 = or(#u8,asl(Rx32,#U5))
Tag: S4_addi_asl_ri    Syntax: Rx32 = add(#u8,asl(Rx32,#U5))
Tag: S4_subi_asl_ri    Syntax: Rx32 = sub(#u8,asl(Rx32,#U5))
Tag: S4_andi_lsr_ri    Syntax: Rx32 = and(#u8,lsr(Rx32,#U5))
Tag: S4_ori_lsr_ri     Syntax: Rx32 = or(#u8,lsr(Rx32,#U5))
Tag: S4_addi_lsr_ri    Syntax: Rx32 = add(#u8,lsr(Rx32,#U5))
Tag: S4_subi_lsr_ri    Syntax: Rx32 = sub(#u8,lsr(Rx32,#U5))
 2020-01-16 12:37:30 -06:00
Chandler Carruth 2946cd7010 Update the file headers across all of the LLVM projects in the monorepo 
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351636
 2019-01-19 08:50:56 +00:00
Krzysztof Parzyszek 545a68ca4b [Hexagon] Add instruction definitions for Hexagon V66 
llvm-svn: 348411
 2018-12-05 21:01:07 +00:00
Krzysztof Parzyszek 6290a73f29 [Hexagon] Update timing classes 
llvm-svn: 348183
 2018-12-03 20:13:18 +00:00
Krzysztof Parzyszek 6bfc6577f2 [Hexagon] Remove support for V4 
llvm-svn: 344791
 2018-10-19 17:31:11 +00:00
Krzysztof Parzyszek 75c2ca3638 [Hexagon] Map ISD::TRAP to J2_trap0(#0) 
llvm-svn: 339365
 2018-08-09 18:03:45 +00:00
Krzysztof Parzyszek d8b780dcd6 [Hexagon] Remove 'T' from HasVNN predicates, NFC 
Patch by Sumanth Gundapaneni.

llvm-svn: 335124
 2018-06-20 13:56:09 +00:00
Krzysztof Parzyszek c5e0ed109d [Hexagon] Add trap1 instruction 
llvm-svn: 326492
 2018-03-01 21:54:08 +00:00
Krzysztof Parzyszek 22a21d4c5d [Hexagon] Add guest registers 
llvm-svn: 326450
 2018-03-01 17:03:26 +00:00
Krzysztof Parzyszek a8ab1b75cb [Hexagon] Add support for Hexagon V65 
llvm-svn: 320404
 2017-12-11 18:57:54 +00:00
Krzysztof Parzyszek 8c53c95137 [Hexagon] Mark vector loads as predicable, update instruction mappings 
All loads of form V6_vL32b_{,cur,nt,tmp,nt_cur,nt_tmp}_{ai,pi,ppu} are
predicable on v62 (but not on v60). Mark them all as predicable in the
instruction definitions, and handle the v60 case in HII::isPredicable.

llvm-svn: 316098
 2017-10-18 17:36:46 +00:00
Krzysztof Parzyszek 557729761c [Hexagon] Switch to parameterized register classes for HVX 
This removes the duplicate HVX instruction set for the 128-byte mode.
Single instruction set now works for both modes (64- and 128-byte).

llvm-svn: 313362
 2017-09-15 15:46:05 +00:00
Krzysztof Parzyszek 9c084fc55d [Hexagon] Add intrinsics for data cache operations 
This is the LLVM part, adding definitions for
  void @llvm.hexagon.Y2.dccleana(i8*)
  void @llvm.hexagon.Y2.dccleaninva(i8*)
  void @llvm.hexagon.Y2.dcinva(i8*)
  void @llvm.hexagon.Y2.dczeroa(i8*)
  void @llvm.hexagon.Y4.l2fetch(i8*, i32)
  void @llvm.hexagon.Y5.l2fetch(i8*, i64)
The clang part will follow.

llvm-svn: 308032
 2017-07-14 15:58:48 +00:00
Krzysztof Parzyszek 2af5037d34 [Hexagon] Use automatically-generated scheduling information for HVX 
Patch by Jyotsna Verma.

llvm-svn: 302073
 2017-05-03 20:10:36 +00:00
Krzysztof Parzyszek 4a1c3f0aaa [Hexagon] Replace CVI_VM_CUR_LD type with CVI_VM_LD 
A .cur instruction can be identified by checking isCVINew() && mayLoad().

Patch by Colin LeMahieu.

llvm-svn: 301829
 2017-05-01 20:16:35 +00:00
Krzysztof Parzyszek 058abf1a4a [Hexagon] Change the vector scaling for vector offsets 
Keep full offset value on MI-level instructions, but have it scaled down
in the MC-level instructions.

llvm-svn: 299664
 2017-04-06 17:28:21 +00:00
Krzysztof Parzyszek 1aaf41af54 [Hexagon] Start using regmasks on calls 
Reapply r295371 with a fix for the Windows bot failures.

llvm-svn: 295504
 2017-02-17 22:14:51 +00:00
Rafael Espindola 6eab4044b9 Revert "[Hexagon] Start using regmasks on calls" 
This reverts commit r295371.

It broke windows bots:

http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio

llvm-svn: 295402
 2017-02-17 02:08:58 +00:00
Krzysztof Parzyszek fb9503c080 [Hexagon] Start using regmasks on calls 
All the cool targets are doing it...

llvm-svn: 295371
 2017-02-16 20:25:23 +00:00
Krzysztof Parzyszek f9015e62fd [Hexagon] Introduce Hexagon V62 
llvm-svn: 294805
 2017-02-10 23:46:45 +00:00
Krzysztof Parzyszek a72fad980c [Hexagon] Replace instruction definitions with auto-generated ones 
llvm-svn: 294753
 2017-02-10 15:33:13 +00:00