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Author SHA1 Message Date
Artyom Skrobov d3ae09bcc8 Recommit r248154: [ARM] Handle DSP feature as an ArchExtKind 
Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in
a hand-rolled tricky condition block in lib/Basic/Targets.cpp, with a FIXME:
attached.

http://reviews.llvm.org/D12937 moved the handling of the DSP feature over to
ARMTargetParser.def in LLVM, to be in line with other architecture extensions.

This is the corresponding patch to clang, to clear the FIXME: and update
the tests.

Differential Revision: http://reviews.llvm.org/D12938

llvm-svn: 248521
 2015-09-24 17:34:05 +00:00
James Molloy 93bd4e9979 Revert "[ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def" 
This was committed without the code review (http://reviews.llvm.org/D12938) being approved.

This reverts commit r248154.

llvm-svn: 248173
 2015-09-21 16:34:58 +00:00
Artyom Skrobov 7428f1ef64 [ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def 
Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in
a hand-rolled tricky condition block in lib/Basic/Targets.cpp, with a FIXME:
attached.

http://reviews.llvm.org/D12937 moved the handling of +t2dsp over to
ARMTargetParser.def in LLVM, to be in line with other architecture extensions.

This is the corresponding patch to clang, to clear the FIXME: and update
the tests.

Differential Revision: http://reviews.llvm.org/D12938

llvm-svn: 248154
 2015-09-21 13:19:25 +00:00
Alexandros Lamprineas 3834d2ca08 [ARM] "cortex-r5f" and "cortex-m4f" are unknown names for clang. 
The tests in test/CodeGen/arm-target-features.c are currently
passing but warning messages are suppressed. These tests are now
synchronized with the corresponding changes in Target Parser.

This patch will fix the regressions in clang caused by r247136

Differential Revision: http://reviews.llvm.org/D12722

llvm-svn: 247138
 2015-09-09 11:29:06 +00:00
Alexandros Lamprineas 94d75dba14 Refactoring of how ARMTargetInfo handles default target features. 
Differential Revision: http://reviews.llvm.org/D11299

llvm-svn: 246946
 2015-09-06 16:15:45 +00:00
Eric Christopher 2374a7cba8 Use a stable sort to guarantee target feature ordering in the IR 
in order to make testing somewhat more feasible. Has the advantage
of making it easier to find target features as well.

llvm-svn: 241134
 2015-07-01 01:07:12 +00:00
Tim Northover f9b517c159 ARM: merge Cyclone into other ARMv8 CPUs and add tests for features. 
Cyclone actually supports all the goodies you'd expect to come with an AArch64
CPU, so it doesn't need its own clause. Also we should probably be testing
these clauses.

llvm-svn: 236349
 2015-05-01 21:17:25 +00:00