Commit Graph

161888 Commits

Author SHA1 Message Date
Sanjay Patel e235942a1e [InstSimplify] fp_binop X, NaN --> NaN
We propagate the existing NaN value when possible.

Differential Revision: https://reviews.llvm.org/D44521

llvm-svn: 328140
2018-03-21 19:31:53 +00:00
Craig Topper f2ab05c432 [TableGen] Remove unnecessary map lookup and shadowing of a variable. NFCI
We already have an OldSCIdx variable in the outer loop here. And we already did the map lookup in the loop that populated ClassInstrs. And the outer OldSCIdx got it from ClassInstrs.

llvm-svn: 328139
2018-03-21 19:30:33 +00:00
Craig Topper 9fbbe5d9ca [TableGen] Use range-based for loops. NFC
llvm-svn: 328138
2018-03-21 19:30:31 +00:00
Craig Topper 06d783765a [TableGen] Use count_if instead of a manual loop. NFC
llvm-svn: 328137
2018-03-21 19:30:30 +00:00
Craig Topper 2854dc93e1 [X86] Rewrite getOperandBias in X86BaseInfo.h to be a little more structured and update comments to be more clear about what it does. NFC
llvm-svn: 328136
2018-03-21 19:30:28 +00:00
David Blaikie 8820929011 Sink Analysis/ObjectUtil(canBeOmittedFromSymbolTable) into IR so it can be legitimately be used by Object/IRSymtab
llvm-svn: 328135
2018-03-21 19:23:45 +00:00
Matthew Simpson b17fff79f0 [SLP] Add test case for a gather sequence with multiple uses
llvm-svn: 328133
2018-03-21 19:13:14 +00:00
Mircea Trofin 71349ff07d [InstrProf] Support for external functions in text format.
Summary:
External functions appearing as indirect call targets could not be
found in the SymTab, and the value:counter record was represented,
in the text format, using an empty string for the name. This would
then cause a silent parsing error when reading.

This CL:
- adds explicit support for such functions
- fixes the places where we would not propagate errors when reading
- addresses a performance issue due to eager resorting of the SymTab.

Reviewers: xur, eraman, davidxl

Reviewed By: davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D44717

llvm-svn: 328132
2018-03-21 19:06:06 +00:00
David Blaikie c72984f802 Ensure that DataTypes.h is installed now that it's moved to llvm-c
llvm-svn: 328130
2018-03-21 18:21:57 +00:00
Andrea Di Biagio 12ef5260ea [llvm-mca] Move the logic that computes the register file usage to the BackendStatistics view.
With this patch, the "instruction dispatched" event now provides information
related to the number of microarchitectural registers used in each register
file. Similarly, the "instruction retired" event is now able to tell how may
registers are freed in each register file.

Currently, the BackendStatistics view is the only consumer of register
usage/pressure information. BackendStatistics uses that info to print out a few
general statistics (i.e. max number of mappings used; total mapping created).
Before this patch, the BackendStatistics was forced to query the Backend to
obtain the register pressure information.

This helps removes that dependency. Now views are completely independent from
the Backend.  As a consequence, it should be easier to address PR36663 and
further modularize the pipeline.

Added a couple of test cases in the BtVer2 specific directory.

llvm-svn: 328129
2018-03-21 18:11:05 +00:00
Simon Pilgrim 949437e882 [SchedModel] Use CodeGenSchedClass::getSchedClassIdx helper directly. NFCI.
llvm-svn: 328128
2018-03-21 18:09:34 +00:00
Simon Pilgrim 4cca3b190b [SchedModel] Use CodeGenSchedClass::isKeyEqual instead of duplicating code. NFCI.
llvm-svn: 328126
2018-03-21 17:57:21 +00:00
Craig Topper 02a114aab4 [Docs] Remove some WIP X86 documentation I accidentally leaked into r328031.
I didn't mean to commit it, but I guess I failed to switch branches or stash it in my local tree.

llvm-svn: 328124
2018-03-21 17:32:57 +00:00
David Blaikie 99e172532c Reapply Support layering fixes.
Compiler.h is used by Demangle (which Support depends on) - so sink it
into Demangle to avoid a circular dependency

DataTypes.h is used by llvm-c (which Support depends on) - so sink it
into llvm-c.

DataTypes.h could probably be fixed the other way - making llvm-c depend
on Support instead of Support depending on llvm-c - if anyone feels
that's the better option, happy to work with them on that.

I /think/ this'll address the layering issues that previous attempts to
commit this have triggered in the Modules buildbot, but I haven't been
able to reproduce that build so can't say for sure. If anyone's having
trouble with this - it might be worth taking a look to see if there's a
quick fix/something small I missed rather than revert, but no worries.

llvm-svn: 328123
2018-03-21 17:31:49 +00:00
David Blaikie e70cbb03b0 Add missing #includes to Analysis/MustExecute.h
llvm-svn: 328122
2018-03-21 17:31:45 +00:00
Eugene Zelenko c132f8840f [Documentation] Fix markup problems in X86Usage.rst
llvm-svn: 328121
2018-03-21 17:24:04 +00:00
Krzysztof Parzyszek b4bb75d6ad [Hexagon] Generalize DAG mutation for function calls
Add barrier edges to check for any physical register. The previous code
worked for the function return registers: r0/d0, v0/w0.

Patch by Brendon Cahoon.

llvm-svn: 328120
2018-03-21 17:23:32 +00:00
Sanjay Patel 778032f39d [InstCombine] add folds for xor-of-icmp signbit tests (PR36682)
This is part of solving:
https://bugs.llvm.org/show_bug.cgi?id=36682

There's also a leftover improvement from the long-ago-closed:
https://bugs.llvm.org/show_bug.cgi?id=5438

https://rise4fun.com/Alive/dC1

llvm-svn: 328119
2018-03-21 17:17:13 +00:00
Nicolai Haehnle 87aec1b194 TableGen: Remove redundant loop in ListInit::resolveReferences
Summary:
Recursive lookups are handled by the Resolver, so the loop was purely
a waste of runtime.

Change-Id: I2bd23a68b478aea0bbac1a86ca7635adffa28688

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D44624

llvm-svn: 328118
2018-03-21 17:13:10 +00:00
Nicolai Haehnle 420e28c78c TableGen: Streamline how defs are instantiated
Summary:
Instantiating def's and defm's needs to perform the following steps:

- for defm's, clone multiclass def prototypes and subsitute template args
- for def's and defm's, add subclass definitions, substituting template
  args
- clone the record based on foreach loops and substitute loop iteration
  variables
- override record variables based on the global 'let' stack
- resolve the record name (this should be simple, but unfortunately it's
  not due to existing .td files relying on rather silly implementation
  details)
- for def(m)s in multiclasses, add the unresolved record as a multiclass
  prototype
- for top-level def(m)s, resolve all internal variable references and add
  them to the record keeper and any active defsets

This change streamlines how we go through these steps, by having both
def's and defm's feed into a single addDef() method that handles foreach,
final resolve, and routing the record to the right place.

This happens to make foreach inside of multiclasses work, as the new
test case demonstrates. Previously, foreach inside multiclasses was not
forbidden by the parser, but it was de facto broken.

Another side effect is that the order of "instantiated from" notes in error
messages is reversed, as the modified test case shows. This is arguably
clearer, since the initial error message ends up pointing directly to
whatever triggered the error, and subsequent notes will point to increasingly
outer layers of multiclasses. This is consistent with how C++ compilers
report nested #includes and nested template instantiations.

Change-Id: Ica146d0db2bc133dd7ed88054371becf24320447

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D44478

llvm-svn: 328117
2018-03-21 17:12:53 +00:00
Eugene Zelenko 3507b0489f [Documentation] Fix markup problem in AMDGPUUsage.rst.
llvm-svn: 328116
2018-03-21 17:09:35 +00:00
Krzysztof Parzyszek c715a5d2b8 [Hexagon] Eliminate subregisters from PHI nodes before pipelining
The pipeliner needs to remove instructions from the SlotIndexes
structure when they are deleted. Otherwise, the SlotIndexes map
has stale data, and an assert will occur when adding new
instructions.

This patch also changes the pipeliner to make the back-edge of
a loop carried dependence 1 cycle. The 1 cycle latency is added
to the anti-dependence that represents the back-edge. This
changes eliminates a couple of hacks added to the pipeliner to
handle the latency of the back-edge. It is needed to correctly
pipeline the test case for the sub-register elimination pass.

llvm-svn: 328113
2018-03-21 16:39:11 +00:00
Reid Kleckner 18574836f9 [WebAssembly] Suppress unused function warning for register name matcher
llvm-svn: 328112
2018-03-21 16:20:58 +00:00
Simon Pilgrim ec2f878779 [X86][Haswell] Merge multiple InstrRW entries that map to the same SchedWriteRes group (NFCI) (PR35955)
I've also merged some VEX/non-VEX instregex strings with a (V?) prefix or (Y?) ymm variant - there are still a lot more of these to do.

llvm-svn: 328111
2018-03-21 16:19:03 +00:00
Simon Pilgrim 96b605d34c [X86][SandyBridge] Merge more VEX/non-VEX instregex patterns (NFCI) (PR35955)
llvm-svn: 328110
2018-03-21 16:05:58 +00:00
Sanjay Patel 3da85ae5a5 [InstCombine] move/add tests for xor-of-icmps (PR36682); NFC
llvm-svn: 328109
2018-03-21 15:54:48 +00:00
Sanjay Patel bab6ce018f [LangRef] add note about format of FP types
llvm-svn: 328105
2018-03-21 15:22:09 +00:00
Alex Bradbury 65d6ea5e68 [RISCV] Codegen support for RV32F floating point comparison operations
This patch also includes extensive tests targeted at select and br+fcmp IR
inputs. A sequence of br+fcmp required support for FPR32 registers to be added
to RISCVInstrInfo::storeRegToStackSlot and
RISCVInstrInfo::loadRegFromStackSlot.

llvm-svn: 328104
2018-03-21 15:11:02 +00:00
Alex Bradbury 77d5927a1c [RISCV] Add tests missed from r327979
llvm-svn: 328102
2018-03-21 14:50:27 +00:00
Alexander Richardson 3056a8424e Change DT_* value definitions to macros in a separate file
Summary:
I recently added a new dynamic tag to our fork of LLVM and when adding it
to llvm-readobj I noticed that not all DT_ values were being handled there.

Using macros in a .def file that can be included by both ELFDumper.cpp and
the ELF.h header ensures that the two don't get out of sync when new values
are added.

Reviewers: grimar, pcc, davide, espindola

Reviewed By: grimar, espindola

Subscribers: srhines, llvm-commits

Differential Revision: https://reviews.llvm.org/D44558

llvm-svn: 328099
2018-03-21 14:17:50 +00:00
Sanjay Patel 85fa9ef626 [LangRef] more hyphens: always write "floating-point"
We were inconsistent, sometimes even within a single sentence.
The consensus seems clear that the FP we're looking for is
spelled "floating-point". Without the hyphen, it's a 
"surprisingly fine" jazz album.

llvm-svn: 328098
2018-03-21 14:15:33 +00:00
Daniel Neilson 6f1eb58e92 [MemCpyOpt] Update to new API for memory intrinsic alignment
Summary:
This change is part of step five in the series of changes to remove alignment argument from
memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the
MemCpyOpt pass to cease using:
1) The old getAlignment() API of MemoryIntrinsic in favour of getting source & dest specific
alignments through the new API.
2) The old IRBuilder CreateMemCpy/CreateMemMove single-alignment APIs in favour of the new
API that allows setting source and destination alignments independently.

We also add a few tests to fill gaps in the testing of this pass.

Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626, rL324642, rL324653, rL324654, rL324773, rL324774,
rL324781, rL324784, rL324955, rL324960, rL325816, rL327398, rL327421 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.

Reference
   http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
   http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html

llvm-svn: 328097
2018-03-21 14:14:55 +00:00
Justin Lebar 038cbc5c13 Re-re-land: Teach CorrelatedValuePropagation to reduce the width of udiv/urem instructions.
Summary:
If the operands of a udiv/urem can be proved to fit within a smaller
power-of-two-sized type, reduce the width of the udiv/urem.

Backed out for causing performance regressions.  Re-landing
because we've determined that these regressions were noise.

Original Differential Revision: https://reviews.llvm.org/D44102

llvm-svn: 328096
2018-03-21 14:08:21 +00:00
Jonas Devlieghere daf69ac2b2 Revert "Move DataTypes.h from Support to llvm-c to fix layering."
This reverts r328065.

I missed this one in r328085 and the bots were still failing.

llvm-svn: 328095
2018-03-21 13:28:37 +00:00
Andrea Di Biagio 43e8f7dacc [llvm-mca] Clean up some code. NFC
Removed a couple of methods from DispatchUnit.

llvm-svn: 328094
2018-03-21 12:49:07 +00:00
Pavel Labath 646ab4113f Fix build broken by r328090
- constexpr is needed for out-of-class definition of the Type static
  member by some compilers
- MSVC is confused by the initialization of the static constexpr char[]
  member when it happens in a template specialization. Explicitly
  specifying the length of the array seems to be enough to help it
  figure things out.

llvm-svn: 328093
2018-03-21 12:18:03 +00:00
Pavel Labath 9025f9559d [dwarf] Unify unknown dwarf enum formatting code
Summary:
We have had at least three pieces of code (in DWARFAbbreviationDeclaration,
DWARFAcceleratorTable and DWARFDie) that have hand-rolled support for
dumping unknown dwarf enum values. While not terrible, they are a bit
distracting and enable small differences to creep in (Unknown_ffff vs.
Unknown_0xffff). I ended up needing to add a fourth place
(DWARFVerifier), so it seems it would be a good time to centralize.

This patch creates an alternative to the XXXString dumping functions in
the BinaryFormat library, which formats an unknown value as
DW_TYPE_unknown_1234, instead of just an empty string. It is based on
the formatv function, as that allows us to avoid materializing the
string for unknown values (and because this way I don't have to invent a
name for the new functions :P).

In this patch I add formatters for dwarf attributes, forms, tags, and
index attributes as these are the ones in use currently, but adding
other enums is straight-forward.

Reviewers: dblaikie, JDevlieghere, aprantl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D44570

llvm-svn: 328090
2018-03-21 11:46:37 +00:00
Jonas Devlieghere 2fdda6882f Revert layering changes
This reverts:
  r328072 "Move Compiler.h from Support to Demangler to fix layering."
  r328073 "Fix the actual user of DataTypes.h in llvm-c to avoid the circular dependency"

Failing bots:
  http://green.lab.llvm.org/green/job/clang-stage2-coverage-R/
  http://green.lab.llvm.org/green/job/clang-stage2-configure-Rlto/

llvm-svn: 328085
2018-03-21 10:35:09 +00:00
Bjorn Pettersson 5c25f88536 [SelectionDAG] Support multiple dangling debug info for one value
Summary:
When building the selection DAG we sometimes need to postpone
the handling of a dbg.value until the value it should refer to
is created. This is done by using the DanglingDebugInfoMap.
In the past this map has been limited to hold one dangling
dbg.value per value. This patch removes that restriction.

Reviewers: aprantl, rnk, probinson, vsk

Reviewed By: aprantl

Subscribers: Ka-Ka, llvm-commits, JDevlieghere

Tags: #debug-info

Differential Revision: https://reviews.llvm.org/D44610

llvm-svn: 328084
2018-03-21 09:44:34 +00:00
George Rimar 2b88406e7b Fix build bot after r328078 "llvm-readobj] - Teach llvm-readobj to dump .note.gnu.property sections."
BB was: http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/27058/steps/test/logs/stdio

llvm-svn: 328080
2018-03-21 08:48:44 +00:00
George Rimar 6a14c02431 [llvm-readobj] - Teach llvm-readobj to dump .note.gnu.property sections.
NT_GNU_PROPERTY_TYPE_0 is a recently added type of .note.gnu.property
section specified in Linux Extensions to gABI.
(https://github.com/hjl-tools/linux-abi/wiki/Linux-Extensions-to-gABI)

Patch teach tool to print such notes properly.

Differential revision: https://reviews.llvm.org/D44469

llvm-svn: 328078
2018-03-21 08:34:55 +00:00
Craig Topper 5a69a0011b [X86][Broadwell] Merge multiple InstrRW entries that map to the same SchedWriteRes group (NFCI) (PR35955)
llvm-svn: 328076
2018-03-21 06:28:42 +00:00
Craig Topper e26118473e [TableGen] Remove a defaulted function argument that is never called with another value. NFC
llvm-svn: 328075
2018-03-21 05:13:04 +00:00
Craig Topper 6f2cc9b107 [TableGen] Move a function from llvm namespace and make it a static function. NFC
It's only called from one place and is defined just above that use.

llvm-svn: 328074
2018-03-21 05:13:01 +00:00
David Blaikie c27da9a996 Fix the actual user of DataTypes.h in llvm-c to avoid the circular dependency
(follow-up to r328065)

llvm-svn: 328073
2018-03-21 04:07:07 +00:00
David Blaikie 6336aedd39 Move Compiler.h from Support to Demangler to fix layering.
Support depends on Demangle (Support/Unix/Signals.inc), so Demangle
including Support/Compiler.h created a circular dependency.

Leave a forwarding shim of Compiler.h because it makes more sense for
users (a deeper fix might involve splitting Support into lower and upper
Support - but that also sounds a bit weird/awkward) than thinking about
the dependency on the Demangler.

llvm-svn: 328072
2018-03-21 04:07:05 +00:00
Craig Topper 137a4dd84d [X86] Fix the SchedRW for XOP vpcom register form instructions to not be marked as loads.
llvm-svn: 328071
2018-03-21 03:41:33 +00:00
Craig Topper f19eacfe0b [TableGen] Use SmallMapVector to simplify some code that was trying to keep a vector unique
Summary:
This code previously had a SmallVector of std::pairs containing an unsigned and another SmallVector. The outer vector was using the unsigned effectively as a key to decide which SmallVector to add into. So each time something new needed to be added the out vector needed to be scanned. If it wasn't found a new entry needed to be added to be added. This sounds very much like a map, but the next loop iterates over the outer vector to get a deterministic order.

We can simplify this code greatly if use SmallMapVector instead. This uses more stack space since we now have a vector and a map, but the searching and creating new entries all happens behind the scenes. It should also make the search more efficient though usually there are only a few entries so that doesn't matter much.

We could probably get determinism by just using std::map which would iterate over the unsigned key, but that would generate different output from what we get with the current implementation.

Reviewers: RKSimon, dblaikie

Reviewed By: dblaikie

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D44711

llvm-svn: 328070
2018-03-21 02:48:34 +00:00
David Blaikie 1963e4b9c5 Move DataTypes.h from Support to llvm-c to fix layering.
Support depends on llvm-c (a few typedefs, macros, etc - Types.h,
Disassembler.h, and TargetMachine.h.

This could be done the other way - those macros/typedefs/etc could be
moved into Support and used from llvm-c instead. If someone feels that's
a better direction to go, happy to discuss it/try it out/etc.

llvm-svn: 328065
2018-03-21 00:48:05 +00:00
Craig Topper d25f1acf67 [X86] Change PMULLD to 10 cycles on Skylake per Agner's tables and llvm-exegesis.
Also restrict to port 0 and 1 for SkylakeClient. It looks like the scheduler models don't account for client not having a full vector ALU on port 5 like server.

Fixes PR36808.

llvm-svn: 328061
2018-03-20 23:39:48 +00:00
Philip Reames 37a1a29fcb [MustExecute] Shwo the effect of using full loop info variant
Most basic possible test for the logic used by LICM.

Also contains a speculative build fix for compiles which complain about a definition of a stuct K; followed by a declaration as class K;

llvm-svn: 328058
2018-03-20 23:00:54 +00:00
Derek Schuff 73a98f5eea [WebAssembly] Update torture compile test expectations
The tests compile after r328049

llvm-svn: 328057
2018-03-20 23:00:13 +00:00
Philip Reames 164b1b4e21 [MustExecute] Add simplest possible test for LoopSafetyOnfo
(Currently showing without, will enable and check in diff to show impact)

llvm-svn: 328056
2018-03-20 22:55:20 +00:00
Philip Reames 23aed5ef6f [MustExecute] Move isGuaranteedToExecute and related rourtines to Analysis
Next step is to actually merge the implementations and get both implementations tested through the new printer.

llvm-svn: 328055
2018-03-20 22:45:23 +00:00
Simon Pilgrim 75cc2f9e1f [SchedModel] Simplify InstRegexOp::apply. NFCI.
As discussed on D44687, there was no need for 2 separate for loops for collecting the Regex and then matching against instructions.

llvm-svn: 328052
2018-03-20 22:20:28 +00:00
Derek Schuff 39b5367cba [WebAssembly] Strip threadlocal attribute from globals in single thread mode
The default thread model for wasm is single, and in this mode thread-local
global variables can be lowered identically to non-thread-local variables.

Differential Revision: https://reviews.llvm.org/D44703

llvm-svn: 328049
2018-03-20 22:01:32 +00:00
Simon Pilgrim 572bfa562a [X86] Drop unnecessary InstRW overrides for WriteFMA
As noticed on D44687, these already match the WriteFMA def so can be removed.

llvm-svn: 328045
2018-03-20 21:15:23 +00:00
Craig Topper 0f110a88be [ReachingDefAnalysis] Fix what I assume to be a typo ReachingDedDefaultVal->ReachingDefDefaultVal.
Unless Ded has some many I don't know about.

llvm-svn: 328043
2018-03-20 20:53:21 +00:00
Shoaib Meenai 3f689c8632 [ObjCARC] Add funclet token to ARC marker
The inline assembly generated for the ARC autorelease elision marker
must have a funclet token if it's emitted inside a funclet, otherwise
the inline assembly (and all subsequent code in the funclet) will be
marked unreachable by WinEHPrepare.

Note that this only applies for the non-O0 case, since at O0, clang
emits the autorelease elision marker itself rather than deferring to the
backend. The fix for clang is handled in a separate change.

Differential Revision: https://reviews.llvm.org/D44641

llvm-svn: 328042
2018-03-20 20:45:41 +00:00
Martin Storsjo 07589fc496 [X86] Don't use the MSVC stack protector names on mingw
Mingw uses the same stack protector functions as GCC provides
on other platforms as well.

Patch by Valentin Churavy!

Differential Revision: https://reviews.llvm.org/D27296

llvm-svn: 328039
2018-03-20 20:37:51 +00:00
Kevin Enderby 85b7a66eee For llvm-objdump and Mach-O files, fix the printing of module init and
term sections from .o files to look to see if the pointers have a relocation
entry and if so print the symbol name from the relocation entry.  If not fall
back to the existing code and use the pointer value to look up that value
in the symbol table.

rdar://38337506

llvm-svn: 328037
2018-03-20 20:29:52 +00:00
Abderrazek Zaafrani 4c60c222e4 [AArch64] Add vmulxh_lane fp16 vector intrinsic
https://reviews.llvm.org/D44591

llvm-svn: 328035
2018-03-20 20:25:40 +00:00
Craig Topper f611425916 [TableGen] Use range based for loop. NFC
llvm-svn: 328034
2018-03-20 20:24:16 +00:00
Craig Topper 1f57456c78 [TableGen] Use vector::append instead of looping and calling push_back. NFC
Both vectors contain unsigned so we can just use append to do the copying. Not only is this shorter, but it should be able to predict the final size and only grow the vector once if needed.

llvm-svn: 328033
2018-03-20 20:24:14 +00:00
Craig Topper 1970e95575 [TableGen] Use llvm::transform to simplify some loops. NFCI
llvm-svn: 328032
2018-03-20 20:24:12 +00:00
Craig Topper b5ed275025 [TableGen] Pass result of std::unique to vector::erase instead of calculating a size and calling resize.
llvm-svn: 328031
2018-03-20 20:24:10 +00:00
Alexey Bataev 858a7dd6d7 [DEBUGINFO] Add -no-dwarf-debug-ranges option.
Summary:
Added option -no-dwarf-debug-ranges option to disable emission of
.debug_ranges section.

Reviewers: probinson, echristo

Subscribers: aprantl, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D44384

llvm-svn: 328030
2018-03-20 20:21:38 +00:00
Andrea Di Biagio 04de0b4340 [llvm-mca] add keyword override to a couple of methods in BackendStatistics.
This should fix the buildbots after r328011.

llvm-svn: 328029
2018-03-20 20:18:36 +00:00
Derek Schuff e4825975d8 [WebAssembly] Added initial AsmParser implementation.
It uses the MC framework and the tablegen matcher to do the
heavy lifting. Can handle both explicit and implicit locals
(-disable-wasm-explicit-locals). Comes with a small regression
test.

This is a first basic implementation that can parse most llvm .s
output and round-trips most instructions succesfully, but in order
to keep the commit small, does not address all issues.

There are a fair number of mismatches between what MC / assembly
matcher think a "CPU" should look like and what WASM provides,
some already have workarounds in this commit (e.g. the way it
deals with register operands) and some that require further work.
Some of that further work may involve changing what the
Disassembler outputs (and what s2wasm parses), so are probably
best left to followups.

Some known things missing:
- Many directives are ignored and not emitted.
- Vararg calls are parsed but extra args not emitted.
- Loop signatures are likely incorrect.
- $drop= is not emitted.
- Disassembler does not output SIMD types correctly, so assembler
  can't test them.

Patch by Wouter van Oortmerssen

Differential Revision: https://reviews.llvm.org/D44329

llvm-svn: 328028
2018-03-20 20:06:35 +00:00
Evandro Menezes 36afbee1d8 [AArch64] Adjust the cost model for Exynos M3
Fix typo in the number of integer dividers.

llvm-svn: 328027
2018-03-20 20:00:29 +00:00
Alexander Shaposhnikov e34104d16c [llvm-objcopy] Revert the tests from r328012
Temporarily revert the tests from r328012 as well.

llvm-svn: 328026
2018-03-20 19:50:14 +00:00
Alexander Shaposhnikov 3b24ed7f21 [llvm-objcopy] Revert r328012
Temporarily revert r328012 (since it broke down the big-endian bots),
will resubmit an updated version later.

llvm-svn: 328024
2018-03-20 19:46:00 +00:00
Krzysztof Parzyszek 4094ab73cc [Hexagon] Add a few more lit tests, NFC
llvm-svn: 328023
2018-03-20 19:35:09 +00:00
Krzysztof Parzyszek 65059ee284 [Hexagon] Add heuristic to exclude critical path cost for scheduling
Patch by Brendon Cahoon.

llvm-svn: 328022
2018-03-20 19:26:27 +00:00
Krzysztof Parzyszek 9315c0de9b [Hexagon] Fix fall-through warnings in HexagonMCDuplexInfo.cpp
llvm-svn: 328021
2018-03-20 19:23:18 +00:00
Nirav Dave ce71989188 [MC,X86] Cleanup some X86 parser functions to use MCParser helpers. NFCI.
llvm-svn: 328019
2018-03-20 19:12:41 +00:00
Andrea Di Biagio 847accd001 [llvm-mca] Remove const from a bunch of ArrayRef. NFC
llvm-svn: 328018
2018-03-20 19:06:34 +00:00
Craig Topper c2dbd677bd [PowerPC][LegalizeFloatTypes] Move the PPC hacks for (i32 fp_to_sint/fp_to_uint (ppcf128 X)) out of LegalizeFloatTypes and into PPC specific code
I'm not entirely sure these hacks are still needed. If you remove the hacks completely, the name of the library call that gets generated doesn't match the grep the test previously had. So the test wasn't really checking anything.

If the hack is still needed it belongs in PPC specific code. I believe the FP_TO_SINT code here is the only place in the tree where a FP_ROUND_INREG node is created today. And I don't think its even being used correctly because the legalization returned a BUILD_PAIR with the same value twice. That doesn't seem right to me. By moving the code entirely to PPC we can avoid creating the FP_ROUND_INREG at all.

I replaced the grep in the existing test with full checks generated by hacking update_llc_test_check.py to support ppc32 just long enough to generate it.

Differential Revision: https://reviews.llvm.org/D44061

llvm-svn: 328017
2018-03-20 18:49:28 +00:00
Krzysztof Parzyszek eb0c510ecd [X86] Add phony registers for high halves of regs with low halves
Registers E[A-D]X, E[SD]I, E[BS]P, and EIP have 16-bit subregisters
that cover the low halves of these registers. This change adds artificial
subregisters for the high halves in order to differentiate (in terms of
register units) between the 32- and the low 16-bit registers.

This patch contains parts that aim to preserve the calculated register
pressure. This is in order to preserve the current codegen (minimize the
impact of this patch). The approach of having artificial subregisters
could be used to fix PR23423, but the pressure calculation would need
to be changed.

Differential Revision: https://reviews.llvm.org/D43353

llvm-svn: 328016
2018-03-20 18:46:55 +00:00
Philip Reames ce998adf0a [MustExecute] Use the annotation style printer
As suggested in the original review (https://reviews.llvm.org/D44524), use an annotation style printer instead.

Note: The switch from -analyze to -disable-output in tests was driven by the fact that seems to be the idiomatic style used in annoation passes.  I tried to keep both working, but the old style pass API for printers really doesn't make this easy.  It invokes (runOnFunction, print(Module)) repeatedly.  I decided the extra state wasn't worth it given the old pass manager is going away soonish anyway.
llvm-svn: 328015
2018-03-20 18:43:44 +00:00
Zachary Turner fced530650 Revert "Resubmit "Support embedding natvis files in PDBs.""
This is still failing on a different bot this time due to some
issue related to hashing absolute paths.  Reverting until I can
figure it out.

llvm-svn: 328014
2018-03-20 18:37:03 +00:00
Alexander Shaposhnikov 43b8acdfd7 [llvm-objcopy] Implement support for section groups
This diff adds support for SHT_GROUP sections to llvm-objcopy.
Some sections are interrelated and comprise a group.
For example, a definition of an inline function might require, 
in addition to the section containing its instructions, 
a read-only data section containing literals referenced inside the function.
A section of the type SHT_GROUP contains the indices of the group members,
therefore, it needs to be updated whenever the indices change.
Similarly, the fields sh_link, sh_info should be recalculated as well.

Test plan: make check-all

Differential revision: https://reviews.llvm.org/D43996

llvm-svn: 328012
2018-03-20 18:20:42 +00:00
Andrea Di Biagio a3f2e483dd [llvm-mca] Move the logic that computes the scheduler's queue usage to the BackendStatistics view.
This patch introduces two new callbacks in the event listener interface to
handle the "buffered resource reserved" event and the "buffered resource
released" event. Every time a buffered resource is used, an event is generated.

Before this patch, the Scheduler (with the help of the ResourceManager) was
responsible for tracking the scheduler's queue usage. However, that design
forced the Scheduler to 'publish' scheduler's queue pressure information through
the Backend interface.

The goal of this patch is to break the dependency between the BackendStatistics
view, and the Backend. Now the Scheduler knows how to notify "buffer
reserved/released" events.  The scheduler's queue usage analysis has been moved
to the BackendStatistics.

Differential Revision: https://reviews.llvm.org/D44686

llvm-svn: 328011
2018-03-20 18:20:39 +00:00
Artem Belevich 914d4babec [NVPTX] Make tensor load/store intrinsics overloaded.
This way we can support address-space specific variants without explicitly
encoding the space in the name of the intrinsic. Less intrinsics to deal with ->
less boilerplate.

Added a bit of tablegen magic to match/replace an intrinsics with a pointer
argument in particular address space with the space-specific instruction
variant.

Updated tests to use non-default address spaces.

Differential Revision: https://reviews.llvm.org/D43268

llvm-svn: 328006
2018-03-20 17:18:59 +00:00
Philip Reames 89f2241770 Add an analysis printer for must execute reasoning
Many of our loop passes make use of so called "must execute" or "guaranteed to execute" facts to prove the legality of code motion. The basic notion is that we know (by assumption) an instruction didn't fault at it's original location, so if the location we move it to is strictly post dominated by the original, then we can't have introduced a new fault.

At the moment, the testing for this logic is somewhat adhoc and done mostly through LICM. Since I'm working on that code, I want to improve the testing. This patch is the first step in that direction. It doesn't actually test the variant used by the loop passes - I need to move that to the Analysis library first - but instead exercises an alternate implementation used by SCEV. (I plan on merging both implementations.)

Note: I'll be replacing the printing logic within this with an annotation based version in the near future.  Anna suggested this in review, and it seems like a strictly better format.  

Differential Revision: https://reviews.llvm.org/D44524

llvm-svn: 328004
2018-03-20 17:09:21 +00:00
Rafael Espindola 52c55896c6 MC: fix layering violation introduced in r325139.
Move AsmToken from MC/MCParser/MCAsmLexer.h into MC/MCAsmMacro.h in
order to avoid MCAsmMacro definition depending on MCParser.

Patch by Roger Pau Monné <royger@freebsd.org>.

llvm-svn: 328003
2018-03-20 17:07:25 +00:00
Zachary Turner 132d7a134f Resubmit "Support embedding natvis files in PDBs."
The issue causing this to fail in certain configurations
should be fixed.

It was due to the fact that DIA apparently expects there to be
a null string at ID 1 in the string table.  I'm not sure why this
is important but it seems to make a difference, so set it.

llvm-svn: 328002
2018-03-20 17:06:39 +00:00
Sanjay Patel ec95e0eed9 [LangRef] fix link formatting
llvm-svn: 328001
2018-03-20 17:05:19 +00:00
Krzysztof Parzyszek 4c6b65f685 [Hexagon] Correct the computation of TopReadyCycle and BotReadyCycle of SU
TopReadyCycle and BotReadyCycle were off by one cycle when an SU is either
the first instruction or the last instruction in a packet.

Patch by Ikhlas Ajbar.

llvm-svn: 328000
2018-03-20 17:03:27 +00:00
Michael Zolotukhin fb3f509e01 [XRay] Lazily compute MachineLoopInfo instead of requiring it.
Summary:
Currently X-Ray Instrumentation pass has a dependency on MachineLoopInfo
(and thus on MachineDominatorTree as well) and we have to compute them
even if X-Ray is not used. This patch changes it to a lazy computation
to save compile time by avoiding these redundant computations.

Reviewers: dberris, kubamracek

Subscribers: llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D44666

llvm-svn: 327999
2018-03-20 17:02:29 +00:00
Sanjay Patel 54b161e47f [LangRef] describe the default FP environment
Follow-up for D44216: add a section and examples to describe the FP env.
Also, add pointers from the FP instructions to this new section to reduce
bloat.

Differential Revision: https://reviews.llvm.org/D44318

llvm-svn: 327998
2018-03-20 16:38:22 +00:00
Krzysztof Parzyszek 73be83dec5 [Hexagon] Check weak dependences when only 1 instruction is available
Patch by Brendon Cahoon.

llvm-svn: 327997
2018-03-20 16:22:06 +00:00
Sanjay Patel 5a9210e651 [AArch64] add fabs tests for PR36600; NFC
llvm-svn: 327995
2018-03-20 16:08:47 +00:00
Alexey Bataev 648ed2dedb [DEBUGINFO] Add flag -no-dwarf-pub-sections to disable pub sections.
Summary:
Added a flag -no-dwarf-pub-sections, which allows to disable
emission of DWARF public sections.

Reviewers: probinson, echristo

Subscribers: aprantl, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D44385

llvm-svn: 327994
2018-03-20 16:04:40 +00:00
Simon Pilgrim 62690e9d0e [X86][Haswell][Znver1] Fix typo in fldl instregexs
Missing comma was casing 2 instregex entries to be concatenated together by mistake.

Found while investigating PR35548

llvm-svn: 327992
2018-03-20 15:44:47 +00:00
Sjoerd Meijer c77e5d0dfa [Kaleidoscope] doc fix
This fixes the compile command of the example in Chapter 2.

Differential Revision: https://reviews.llvm.org/D43196

llvm-svn: 327989
2018-03-20 15:37:15 +00:00
Krzysztof Parzyszek 5ffd808a27 [Hexagon] Improve scheduling heuristic for large basic blocks
This patch changes the isLatencyBound heuristic to look at the
path length based upon the number of packets needed to schedule
a basic block. For small basic blocks, the heuristic uses a small
threshold for isLatencyBound. For large basic blocks, the
heuristic uses a large threshold.

The goal is to increase the priority of an instruction in a small
basic block that has a large height or depth relative to the code
size. For large functions, the height and depth are ignored
because it increases the live range of a register and causes more
spills. That is, for large functions, it is more important to
schedule instructions when available, and attempt to keep the defs
and uses closer together.

Patch by Brendon Cahoon.

llvm-svn: 327987
2018-03-20 14:54:01 +00:00
Geoff Berry 0b64402adb [AArch64][Falkor] Correct load/store increment scheduling details
llvm-svn: 327982
2018-03-20 13:46:35 +00:00
Krzysztof Parzyszek 2c4231d888 [Hexagon] Fix division by zero in machine scheduler
llvm-svn: 327980
2018-03-20 13:28:46 +00:00
Alex Bradbury 80c8eb7696 [RISCV] Add codegen for RV32F floating point load/store
As part of this, add support for load/store from the constant pool. This is
used to materialise f32 constants.

llvm-svn: 327979
2018-03-20 13:26:12 +00:00
Andrea Di Biagio 7b3d162fba [llvm-mca] Use llvm::make_unique in a few places. NFC
Also, clang-format a couple of DEBUG functions.

llvm-svn: 327978
2018-03-20 12:58:34 +00:00
Alex Bradbury 76c29ee815 [RISCV] Add codegen for RV32F arithmetic and conversion operations
Currently, only a soft floating point ABI is supported.

llvm-svn: 327976
2018-03-20 12:45:35 +00:00
Krzysztof Parzyszek dca383123f [Hexagon] Improve scheduling based on register pressure
Patch by Brendon Cahoon.

llvm-svn: 327975
2018-03-20 12:28:43 +00:00
Simon Pilgrim 4a83f802cc [X86][SandyBridge] Merge multiple InstrRW entries that map to the same SchedWriteRes group (NFCI) (PR35955)
I've also merged some VEX/non-VEX instregex strings with a (V?) prefix - there are still a lot more of these to do.

llvm-svn: 327974
2018-03-20 12:26:55 +00:00
Andrea Di Biagio 4704f0386b [llvm-mca] Move the routine that computes processor resource masks to its own file.
Function computeProcResourceMasks is used by the ResourceManager (owned by the
Scheduler) to compute resource masks for processor resources.  Before this
refactoring, there was an implicit dependency between the Scheduler and the
InstrBuilder. That is because InstrBuilder has to know about resource masks when
computing the set of processor resources consumed by a new instruction.

With this patch, the functionality that computes resource masks has been
extracted from the ResourceManager, and moved to a separate file (Support.h). 
This helps removing the dependency between the Scheduler and the InstrBuilder.

No functional change intended.

llvm-svn: 327973
2018-03-20 12:25:54 +00:00
Xin Tong a713ebea24 [MergeICmps] Break eargerly out of loop
llvm-svn: 327972
2018-03-20 12:03:25 +00:00
Xin Tong bdbd97ed9a [MergeICmp] Fix a bug in entry block shuffled to middle of the chain
Summary: Fix a bug in entry block shuffled to middle of the chain.

Reviewers: davide, courbet

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D44642

llvm-svn: 327971
2018-03-20 11:57:54 +00:00
Igor Laevsky 3ce2d7f270 [llvm-opt-fuzzer] Add irce to the fuzzing options
llvm-svn: 327969
2018-03-20 11:32:13 +00:00
Jonas Devlieghere aefa14fcd1 Revert "Fix layering between llvm-c and Support by factoring out some typedefs into Support"
This reverts r327940 because it fails on several GreenDragon bots.

  http://green.lab.llvm.org/green/job/clang-stage2-configure-Rlto/
  http://green.lab.llvm.org/green/job/clang-stage2-coverage-R/

llvm-svn: 327968
2018-03-20 11:26:50 +00:00
Dylan McKay 212841b7ad [AVR] Add a regression test for struct return lowering
The test is taken from
https://github.com/avr-rust/rust/issues/57

The originally implementation of struct return lowering was made in
r325474.

Patch by Peter Nimmervoll

llvm-svn: 327967
2018-03-20 11:23:03 +00:00
Andrea Di Biagio ce63362ef8 [Release Notes] Add release note for llvm-mca.
Differential Revision: https://reviews.llvm.org/D44636

llvm-svn: 327965
2018-03-20 10:25:36 +00:00
Bjorn Pettersson bf3213e485 [CGP] Avoid segmentation fault when doing PHI node simplifications
Summary:
Made PHI node simplifiations more robust in several ways:

- Minor refactoring to let the SimplificationTracker own the
sets with new PHI/Select nodes that are introduced. This is
maybe not mapping to the original intention with the
SimplificationTracker, but IMHO it encapsulates the logic behind
those sets a little bit better.

- MatchPhiNode can sometimes populate the Matched set with
several entries, where it maps one PHI node to different candidates
for replacement. The Matched set is changed into a SmallSetVector
to make sure we get a deterministic iteration when doing
the replacements.

- As described above we may get several different replacements
for a single PHI node. The loop in MatchPhiSet that is doing
the replacements could end up calling eraseFromParent several
times for the same PHI node, resulting in segmentation faults.
This problem was supposed to be fixed in rL327250, but due to
the non-determinism(?) it only appeared to be fixed (I still
got crashes sometime when turning on/off -print-after-all etc
to get different iteration order in the DenseSets).
With this patch we follow the deterministic ordering in the
Matched set when replacing the PHI nodes. If we find a new
replacement for an already replaced PHI node we replace the
new replacement by the old replacement instead. This is quite
similar to what happened in the rl327250 patch, but here we
also recursively verify that the old replacement hasn't been
replaced already.

- It was really hard to track down the fault described above
(segementation fault due to doing eraseFromParent multiple
times for the same instruction). The fault was intermittent and
small changes in the code, or simply turning on -print-after-all
etc could make the problem go away. This was basically due to
the iteration over PhiNodesToMatch in MatchPhiSet no being
deterministic. Therefore I've changed the data structure for
the SimplificationTracker::AllPhiNodes into an SmallSetVector.
This gives a deterministic behavior.

Reviewers: skatkov, john.brawn

Reviewed By: skatkov

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D44571

llvm-svn: 327961
2018-03-20 09:06:37 +00:00
Andrei Elovikov 8b8253fdc7 [LV] Let recordVectorLoopValueForInductionCast to check if IV was created from the cast.
Summary:
It turned out to be error-prone to expect the callers to handle that - better to
leave the decision to this routine and make the required data to be explicitly
passed to the function.

This handles the case that was missed in the r322473 and fixes the assert
mentioned in PR36524.

Reviewers: dorit, mssimpso, Ayal, dcaballe

Reviewed By: dcaballe

Subscribers: Ka-Ka, hiraditya, dneilson, hsaito, llvm-commits

Differential Revision: https://reviews.llvm.org/D43812

llvm-svn: 327960
2018-03-20 09:04:39 +00:00
Jonas Paulsson 8ad035d8e5 [SystemZ] Add "REQUIRES: asserts" to test case to fix build bots.
llvm-svn: 327958
2018-03-20 08:29:19 +00:00
Martin Storsjo 802b434156 [X86] Properly implement the calling convention for f80 for mingw/x86_64
In these cases, both parameters and return values are passed
as a pointer to a stack allocation.

MSVC doesn't use the f80 data type at all, while it is used
for long doubles on mingw.

Normally, this part of the calling convention is handled
within clang, but for intrinsics that are lowered to libcalls,
it may need to be handled within llvm as well.

Differential Revision: https://reviews.llvm.org/D44592

llvm-svn: 327957
2018-03-20 06:19:38 +00:00
Lang Hames 2c83285716 [ORC] Don't fully qualify explicit destructor call -- it confuses some compilers.
This should fix the builder failure at
http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/19224

llvm-svn: 327955
2018-03-20 05:56:58 +00:00
Craig Topper ad7c685791 [X86] Rename MOVSX32_NOREXrr8 to MOVSX32rr8_NOREX so that the scheduler model regular expressions will pick it up with the regular version.
Do the same for MOVSX32_NOREXrm8, MOVZX32_NOREXrr8, and MOVZX32_NOREXrm8

llvm-svn: 327948
2018-03-20 05:00:20 +00:00
Craig Topper 4778fa7e8a [X86] Fix the SchedRW for memory forms of CMP and TEST.
They were incorrectly marked as RMW operations. Some of the CMP instrucions worked, but the ones that use a similar encoding as RMW form of ADD ended up marked as RMW.

TEST used the same tablegen class as some of the CMPs.

llvm-svn: 327947
2018-03-20 03:55:17 +00:00
Lang Hames 4cca7d229e [ORC] Rename SymbolSource to MaterializationUnit, and make the materialization
operation all-or-nothing, rather than allowing materialization on a per-symbol
basis.

This addresses a shortcoming of per-symbol materialization: If a
MaterializationUnit (/SymbolSource) wants to materialize more symbols than
requested (which is likely: most materializers will want to materialize whole
modules) then it needs a way to notify the symbol table about the extra symbols
being materialized. This process (checking what has been requested against what
is being provided and notifying the symbol table about the difference) has to
be repeated at every level of the JIT stack. Making materialization
all-or-nothing eliminates this issue, simplifying both materializer
implementations and the symbol table (VSO class) API. The cost is that
per-symbol materialization (e.g. for individual symbols in a module) now
requires multiple MaterializationUnits.

llvm-svn: 327946
2018-03-20 03:49:29 +00:00
Craig Topper 3e9462607e [X86] Add TEST16mi/TEST32mi/TEST64mi32 to the Sandybridge/Haswell/Broadwell/Skylake scheduler models.
Move it from a load+store group on SNB to a load only group, the same group as CMP.

llvm-svn: 327944
2018-03-20 03:02:03 +00:00
Craig Topper 7c90e29cf8 [X86] Add ROR/ROL/SHR/SAR by 1 instructions to the Sandy Bridge scheduler model.
I assume these match the generic immediate version like they do in the other models.

llvm-svn: 327943
2018-03-20 03:01:59 +00:00
Quentin Colombet 508f68233d [ShrinkWrap] Take into account landing pad
When scanning the function for CSRs uses and defs, also check if
the basic block are landing pads.
Consider that landing pads needs the CSRs to be properly set.
That way we force the prologue/epilogue to always be pushed out
of the problematic "throw" region. The "throw" region is
problematic because the jumps are not properly modeled.

Fixes PR36513

llvm-svn: 327942
2018-03-20 02:44:40 +00:00
David Blaikie 9ea40609ba Fix layering between llvm-c and Support by factoring out some typedefs into Support
llvm-c depends on Support, but Support (TargetRegistry) uses some of
llvm-c's typedefs. Move those into a Support header to be used from both
llvm-c and Support.

llvm-svn: 327940
2018-03-20 02:14:50 +00:00
Shiva Chen cbd498ac10 [RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects
E.g.

bar (int x)
{
  char p[x];

  push outgoing variables for foo.
  call foo
}

We need to generate stack adjustment instructions for outgoing arguments by
eliminateCallFramePseudoInstr when the function contains variable size
objects to avoid outgoing variables corrupt the variable size object.

Default hasReservedCallFrame will return !hasFP().
We don't want to generate extra sp adjustment instructions when hasFP()
return true, So We override hasReservedCallFrame as !hasVarSizedObjects().

Differential Revision: https://reviews.llvm.org/D43752

llvm-svn: 327938
2018-03-20 01:39:17 +00:00
Craig Topper 2330d6cd55 [X86] Fix the SNB scheduler for BLENDVB.
PBLENDVBrr0 was with the memory version of VBLENDVB and PBLENDVBrm0 was missing.

llvm-svn: 327937
2018-03-20 01:30:21 +00:00
Rafael Espindola d947977e87 Run dos2unix on a test. NFC.
llvm-svn: 327934
2018-03-20 01:06:29 +00:00
Aaron Smith 6fe19e819e [DebugInfoPDB] Add backward support flags to PDB_NameSearchFlags
For NS_CaseInFileNameExt support.

llvm-svn: 327933
2018-03-20 01:04:21 +00:00
Vitaly Buka 849217abdf Object: Fix handling of @@@ in .symver directive
Summary:
name@@@nodename is going to be replaced with name@@nodename if symbols is
defined in the assembled file, or name@nodename if undefined.
https://sourceware.org/binutils/docs/as/Symver.html

Fixes PR36623

Reviewers: pcc, espindola

Subscribers: mehdi_amini, hiraditya

Differential Revision: https://reviews.llvm.org/D44274

llvm-svn: 327930
2018-03-20 00:45:03 +00:00
Vitaly Buka 0d03881eb5 Object: Move attribute calculation into RecordStreamer. NFC
Summary: Preparation for D44274

Reviewers: pcc, espindola

Subscribers: hiraditya

Differential Revision: https://reviews.llvm.org/D44276

llvm-svn: 327928
2018-03-20 00:38:33 +00:00
Aaron Smith 6738960588 [SelectionDAG] Transfer DbgValues when integer operations are promoted
Summary:
DbgValue nodes were not transferred when integer DAG nodes were promoted. For example, if an i32 add node was promoted to an i64 add node by DAGTypeLegalizer::PromoteIntegerResult(), its DbgValue node was not transferred to the new node. The simple fix is to update SetPromotedInteger() to transfer DbgValues. 

Add AArch64/dbg-value-i8.ll to test this change and fix ARM/debug-info-d16-reg.ll which had the wrong DILocalVariable nodes with arg numbers even though they are not for function parameters.

Patch by Se Jong Oh!

Reviewers: vsk, JDevlieghere, aprantl

Reviewed By: JDevlieghere

Subscribers: javed.absar, kristof.beyls, llvm-commits

Tags: #debug-info

Differential Revision: https://reviews.llvm.org/D44546

llvm-svn: 327919
2018-03-19 22:58:50 +00:00
Jessica Paquette 563548d8f3 [MachineOutliner] AArch64: Emit CFI instructions when outlining calls
When outlining calls, the outliner needs to update CFI to ensure that, say,
exception handling works. This commit adds that functionality and adds a test
just for call outlining.

Call outlining stuff in machine-outliner.mir should be moved into
machine-outliner-calls.mir in a later commit.

llvm-svn: 327917
2018-03-19 22:48:40 +00:00
Craig Topper 956fec2a4a [DAGCombiner] Fix type in comment. NFC
llvm-svn: 327916
2018-03-19 22:25:26 +00:00
Craig Topper ab6076514d [X86] Simplify the AVX512 code in LowerTruncate a little.
We don't need to create an ISD::TRUNCATE node to return, we started with one and can return it. Also remove the call to getExtendInVec, the result is just going to be a getNode of that value passed in.

llvm-svn: 327914
2018-03-19 21:58:02 +00:00
Serge Guelton 1447c97909 Accept any filepath in llvm_check_source_file_list
Cmake function llvm_check_source_file_list currently only accepts paths
relative to current CMAKE_SOURCE_DIR or relative to argument SOURCE_DIR.

Extend it to accept any path, including absolute ones.

Differential revision: https://reviews.llvm.org/D44625

llvm-svn: 327912
2018-03-19 21:35:30 +00:00
Aaron Smith da61120749 [PDB] Add a method to get the full path of the source file for PDBSymbolCompiland
Summary:
Redefine PDBSymbolCompiland::getSourceFileName() to return the filename (w/o directory) of the source file that is used to compile the compiland. This is because the result returned previously is ambiguous. It could be the filename, relative path or full path of the source file. 

Move the implementation of SymbolFilePDB::GetSourceFileNameForPDBCompiland() into a new method PDBSymbolCompiland::getSourceFileFullPath(). 

Reviewers: zturner, rnk, llvm-commits

Reviewed By: zturner

Differential Revision: https://reviews.llvm.org/D44458

llvm-svn: 327910
2018-03-19 21:20:04 +00:00
Aaron Smith 06173e8b46 [PDB] Add exclusive methods to derived symbol class
Summary: This commit adds two methods to the PDBSymboFunc class used in parsing symbols. getLineNumbers() is used to determine a Function symbol's declaration and getCompilandId() is used to initialize the SymbolContext field sc.comp_unit.

Reviewers: zturner, rnk, llvm-commits

Reviewed By: zturner

Differential Revision: https://reviews.llvm.org/D44457

llvm-svn: 327909
2018-03-19 21:18:39 +00:00
Krzysztof Parzyszek c76fefc6de [Hexagon] Add REQUIRES: asserts to test/CodeGen/Hexagon/v6vec_inc1.ll
llvm-svn: 327907
2018-03-19 21:05:21 +00:00
Zachary Turner a21558897b Revert "Support embedding natvis files in PDBs."
This is causing a test failure on a certain bot, so I'm removing
this temporarily until we can figure out the source of the error.

llvm-svn: 327903
2018-03-19 20:41:59 +00:00
Zachary Turner 426885b10c Remove an unused private variable.
llvm-svn: 327900
2018-03-19 20:22:48 +00:00
Craig Topper 3b967466d5 [X86] Replace a couple calls to getExtendInVec with getNode and the appropriate target independent EXTEND_VECTOR_INREG opcode.
llvm-svn: 327899
2018-03-19 20:20:22 +00:00
Nirav Dave 3264c1bdf6 [DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
Reland ISel cycle checking improvements after simplifying node id
invariant traversal and correcting typo.

llvm-svn: 327898
2018-03-19 20:19:46 +00:00
Martin Storsjo 9a55c1b0dc [ARM, AArch64] Check the no-stack-arg-probe attribute for dynamic stack probes
This extends the use of this attribute on ARM and AArch64 from
SVN r325900 (where it was only checked for fixed stack
allocations on ARM/AArch64, but for all stack allocations on X86).

This also adds a testcase for the existing use of disabling the
fixed stack probe with the attribute on ARM and AArch64.

Differential Revision: https://reviews.llvm.org/D44291

llvm-svn: 327897
2018-03-19 20:06:50 +00:00
Alina Sbirlea eccd8ac7d8 Add cast to Type*, fix failure from r327894.
llvm-svn: 327896
2018-03-19 20:05:01 +00:00
Zachary Turner de53aaf132 Support embedding natvis files in PDBs.
Natvis is a debug language supported by Visual Studio for
specifying custom visualizers.  The /NATVIS option is an
undocumented link.exe flag which will take a .natvis file
and "inject" it into the PDB.  This way, you can ship the
debug visualizers for a program along with the PDB, which
is very useful for postmortem debugging.

This is implemented by adding a new "named stream" to the
PDB with a special name of /src/files/<natvis file name>
and simply copying the contents of the xml into this file.

Additionally, we need to emit a single stream named
/src/headerblock which contains a hash table of embedded
files to records describing them.

This patch adds this functionality, including the /NATVIS
option to lld-link.

Differential Revision: https://reviews.llvm.org/D44328

llvm-svn: 327895
2018-03-19 19:53:51 +00:00
Alina Sbirlea a2036e4945 Make ConstantDataArray::get constructor templated. Will support signed integers.
Summary: Make ConstantDataArray::get() constructors a single templated one.

Reviewers: timshen, rsmith

Subscribers: sanjoy, llvm-commits, jlebar

Differential Revision: https://reviews.llvm.org/D44337

llvm-svn: 327894
2018-03-19 19:49:28 +00:00
Sanjay Patel f2d85e78df [AMDGPU] change test to avoid NaN math
llvm-svn: 327891
2018-03-19 19:26:22 +00:00
Sanjay Patel dad3d13b99 [AMDGPU] adjust tests to be nan-free
As suggested in D44521 - bitcast to integer for the math,
so we preserve the intent of these tests when NaN math
gets folded away.

llvm-svn: 327890
2018-03-19 19:23:53 +00:00
Lei Huang ecfede94a7 [Power9]Legalize and emit code for quad-precision copySign/abs/nabs/neg/sqrt
Legalize and emit code for quad-precision floating point operations:

  * xscpsgnqp
  * xsabsqp
  * xsnabsqp
  * xsnegqp
  * xssqrtqp

Differential Revision: https://reviews.llvm.org/D44530

llvm-svn: 327889
2018-03-19 19:22:52 +00:00
Andrea Di Biagio 1038cff6e9 [llvm-mca] Remove unused method from ResourceManager. NFC
llvm-svn: 327888
2018-03-19 19:14:06 +00:00
Andrea Di Biagio 44bfcd2d63 [llvm-mca] Simplify code. NFC
llvm-svn: 327886
2018-03-19 19:09:38 +00:00
Krzysztof Parzyszek 461e6691eb [Hexagon] Add a few more lit tests
llvm-svn: 327884
2018-03-19 19:03:18 +00:00
Craig Topper 9770107b5f [X86] Add JMP16r and JMP32r to Sandybridge scheduler model.
Fixes PR36010

llvm-svn: 327883
2018-03-19 19:00:37 +00:00
Craig Topper 5e65996fac [X86] Remove OUT32rr/OUT8rr/OUT32ri/OUT8ri from Sandybridge scheduler model.
PR35590 was already filed for this information being wrong. It's probably better to default to WriteSystem behavior instead of using something completely wrong.

llvm-svn: 327882
2018-03-19 19:00:35 +00:00
Craig Topper b4c7873f8c [X86] Add JCXZ/JECXZ to Sandybridge/Haswell/Broadwell/Skylake scheduler models.
JRCXZ was already present, but not the others.

We never codegen this instruction so this doesn't affect much just trying to get them all into a single generated scheduler class in the output.

llvm-svn: 327881
2018-03-19 19:00:32 +00:00
Craig Topper afabf36505 [X86] Correct regular expression in Zen scheduler model that was excluding JECXZ instruction.
The regex was looking for JECXZ_32 or JECXZ_64, but their is just one instruction called JECXZ. They used to exist as separate instructions, but were merged over 3 years ago.

llvm-svn: 327880
2018-03-19 19:00:29 +00:00
Craig Topper 591f44df54 [X86] Correct the SchedRW on (V)MOVAPSrr_REV and similar to match their non _REV counterparts.
llvm-svn: 327879
2018-03-19 19:00:26 +00:00
Lei Huang 6d1596a98c [PowerPC][Power9]Legalize and emit code for quad-precision add/div/mul/sub
Legalize and emit code for quad-precision floating point operations:

  * xsaddqp
  * xssubqp
  * xsdivqp
  * xsmulqp

Differential Revision: https://reviews.llvm.org/D44506

llvm-svn: 327878
2018-03-19 18:52:20 +00:00
Nemanja Ivanovic d9d5bd3067 [PowerPC] Make AddrSpaceCast noop
PowerPC targets do not use address spaces. As a result, we can get selection
failures with address space casts. This patch makes those casts noops.

Patch by Valentin Churavy.

Differential revision: https://reviews.llvm.org/D43781

llvm-svn: 327877
2018-03-19 18:50:02 +00:00
Craig Topper 836cfb3a4c [X86] Add the rest of the TEST with immediate instructions to the scheduler models to match their 8-bit counterpart.
llvm-svn: 327874
2018-03-19 17:58:41 +00:00
Craig Topper 645e531a69 [X86] Add MOV16ri*/MOV32ri*/MOV64ri* to scheduler models to match MOV8ri. Correct SchedRW and itinerary for MOV32ri64.
llvm-svn: 327872
2018-03-19 17:46:59 +00:00
Craig Topper 259eaa6e7c [X86] Remove sse41 specific code from lowering v16i8 multiply
With the SRAs removed from the SSE2 code in D44267, then there doesn't appear to be any advantage to the sse41 code. The punpcklbw instruction and pmovsx seem to have the same latency and throughput on most CPUs. And the SSE41 code requires moving the upper 64-bits into the lower 64-bit before the sign extend can be done. The unpckhbw in sse2 code can do better than that.

llvm-svn: 327869
2018-03-19 17:31:41 +00:00
Craig Topper 5ccd87233f [X86] Make the multiply and divide itineraries more consistent.
Sometimes we used the same itinerary for MEM and REG forms, but that seems inconsistent with our usual usage.

We also used the MUL8 itinerary for MULX32/64 which was also weird.

The test changes are because we were using IIC_IMUL32_RR and IIC_IMUL64_RR instead of IIC_IMUL32_REG/IIC_IMUL64_REG for the 32 and 64 bit multiplies that produce double width result.

llvm-svn: 327866
2018-03-19 16:38:33 +00:00
Zaara Syeda 01f414baaa Revert [MachineLICM] This reverts commit rL327856
Failing build bots. Revert the commit now.

llvm-svn: 327864
2018-03-19 16:19:44 +00:00
Matt Davis 4b54e5fc38 [CodeGen] Avoid handling DBG_VALUE in the LivePhysRegs (addUses,removeDefs,stepForward)
Summary:
This patch prevents DBG_VALUE instructions from influencing
LivePhysRegs::stepBackwards and stepForwards.  In at least one case,
specifically branch folding, the stepBackwards logic was having an
influence on code generation.  The result was that certain code
compiled with '-g -O2' would differ from that compiled with '-O2'
alone. It seems that the original logic, accounting for DBG_VALUE,
was influencing the placement of an IMPLICIT_DEF which had a later
impact on how blocks were processed in branch folding.

Reviewers: kparzysz, MatzeB

Reviewed By: kparzysz

Subscribers: bjope, llvm-commits

Tags: #debug-info

Differential Revision: https://reviews.llvm.org/D43850

llvm-svn: 327862
2018-03-19 16:06:40 +00:00
Erik Pilkington bb7feae218 [demangler] Recopy the demangler from libcxxabi.
Some significant work has gone into libcxxabi's copy of this file:
  - Uses an AST to represent mangled names.
  - Support/bugfixes for many C++ features.
  - Uses LLVM coding style.

llvm-svn: 327859
2018-03-19 15:18:23 +00:00
Sanjay Patel 0ce3086777 [InstCombine] canonicalize fcmp+select to fabs
This is complicated by -0.0 and nan. This is based on the DAG patterns 
as shown in D44091. I'm hoping that we can just remove those DAG folds 
and always rely on IR canonicalization to handle the matching to fabs.

We would still need to delete the broken code from DAGCombiner to fix 
PR36600:
https://bugs.llvm.org/show_bug.cgi?id=36600

Differential Revision: https://reviews.llvm.org/D44550

llvm-svn: 327858
2018-03-19 15:14:30 +00:00
Zaara Syeda ff05e2b0e6 [MachineLICM] Add functions to MachineLICM to hoist invariant stores
This patch adds functions to allow MachineLICM to hoist invariant stores.
Currently, MachineLICM does not hoist any store instructions, however
when storing the same value to a constant spot on the stack, the store
instruction should be considered invariant and be hoisted. The function
isInvariantStore iterates each operand of the store instruction and checks
that each register operand satisfies isCallerPreservedPhysReg. The store
may be fed by a copy, which is hoisted by isCopyFeedingInvariantStore.
This patch also adds the PowerPC changes needed to consider the stack
register as caller preserved.

Differential Revision: https://reviews.llvm.org/D40196

llvm-svn: 327856
2018-03-19 14:52:25 +00:00
Simon Pilgrim 30c38c3849 [X86] Generalize schedule classes to support multiple stages
Currently the WriteResPair style multi-classes take a single pipeline stage and latency, this patch generalizes this to make it easier to create complex schedules with ResourceCycles and NumMicroOps be overriden from their defaults.

This has already been done for the Jaguar scheduler to remove a number of custom schedule classes and adding it to the other x86 targets will make it much tidier as we add additional classes in the future to try and replace so many custom cases.

I've converted some instructions but a lot of the models need a bit of cleanup after the patch has been committed - memory latencies not being consistent, the class not actually being used when we could remove some/all customs, etc. I'd prefer to keep this as NFC as possible so later patches can be smaller and target specific.

Differential Revision: https://reviews.llvm.org/D44612

llvm-svn: 327855
2018-03-19 14:46:07 +00:00
Sanjay Patel 05daae75ad [x86] put nops into the WriteNop class and customize for Jaguar
1. Given that we already have a classification bucket with 'nop' in the name, 
   that's where 'nop' belongs. Right now, it's only used for prefix bytes and 'pause'.
2. Make the latency of this class '1' for Jaguar to tell the scheduler (and presumably 
   llvm-mca) how to model the resource requirements better even though a nop has no 
   dependencies.

Differential Revision: https://reviews.llvm.org/D44608

llvm-svn: 327853
2018-03-19 14:26:50 +00:00
Ilya Biryukov 8418576304 Changed createTemporaryFile without FD to actually create a file.
Summary:
This commit changes semantics of createUniqueFile and
createTemporaryFile variants that do not return file descriptors.
Previously they only checked if files exist, therefore being subject
to race conditions. Now they will create an empty file to avoid them.

Functions that do not create a file are now called
getPotentiallyUniqueTempFileName and getPotentiallyUniqueFileName.

Reviewers: klimek, bkramer, krasimir, JDevlieghere, espindola

Reviewed By: klimek

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D36827

llvm-svn: 327851
2018-03-19 14:19:58 +00:00
Nicolai Haehnle 2ad19016c0 TableGen: Explicitly forbid self-references to field members
Summary:
Otherwise, patterns like in the test case produce cryptic error
messages about fields being resolved incompletely.

Change-Id: I713c0191f00fe140ad698675803ab1f8823dc5bd

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D44476

llvm-svn: 327850
2018-03-19 14:14:28 +00:00
Nicolai Haehnle 4186cc7c08 TableGen: Check the dynamic type of !cast<Rec>(string)
Summary:
The docs already claim that this happens, but so far it hasn't. As a
consequence, existing TableGen files get this wrong a lot, but luckily
the fixes are all reasonably straightforward.

To make this work with all the existing forms of self-references (since
the true type of a record is only built up over time), the lookup of
self-references in !cast is delayed until the final resolving step.

Change-Id: If5923a72a252ba2fbc81a889d59775df0ef31164

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D44475

llvm-svn: 327849
2018-03-19 14:14:20 +00:00
Nicolai Haehnle 18f1998a00 TableGen: Explicitly test some cases of self-references and !cast errors
Summary:
These are cases of self-references that exist today in practice. Let's
add tests for them to avoid regressions.

The self-references in PPCInstrInfo.td can be expressed in a simpler
way. Allowing this type of self-reference while at the same time
consistently doing late-resolve even for self-references is problematic
because there are references to fields that aren't in any class. Since
there's no need for this type of self-reference anyway, let's just
remove it.

Change-Id: I914e0b3e1ae7adae33855fac409b536879bc3f62

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: nemanjai, wdng, kbarton, llvm-commits

Differential Revision: https://reviews.llvm.org/D44474

llvm-svn: 327848
2018-03-19 14:14:10 +00:00
Nicolai Haehnle 335c70f55e TableGen: Only fold when some operand made resolve progress
Summary:
Make sure that we always fold immediately, so there's no point in
attempting to re-fold when nothing changes.

Change-Id: I069e1989455b6f2ca8606152f6adc1a5e817f1c8

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D44198

llvm-svn: 327847
2018-03-19 14:14:04 +00:00
Nicolai Haehnle a43af64fa2 TableGen: Remove OpInit::Fold
Summary:
Virtual dispatch is not actually used anywhere.

Change-Id: I9829c5c59920ea27fb9bc17f1442156a3bb09a65

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D44197

llvm-svn: 327846
2018-03-19 14:13:59 +00:00
Nicolai Haehnle 1eaebc62d7 TableGen: Move GenStrConcat to a helper function in BinOpInit
Summary:
Make it accessible for more users.

Change-Id: Ib05f09ba14e7942ced5d2f24b205efa285e40cd5

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D44196

llvm-svn: 327845
2018-03-19 14:13:54 +00:00
Nicolai Haehnle c47fe129cb TableGen: Remove the cast-from-string-to-variable-reference feature
Summary:
Cast-from-string for records isn't going away, but cast-from-string for
variables is a pretty dodgy feature to have, especially when referencing
template arguments. It's doubtful that this ever worked in a reliable
way, and nobody seems to be using it, so let's get rid of it and get
some related cleanups.

Change-Id: I395ac8a43fef4cf98e611f2f552300d21e99b66a

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D44195

llvm-svn: 327844
2018-03-19 14:13:37 +00:00
Matt Arsenault fed0a45036 AMDGPU/GlobalISel: RegBankSelect for basic int ops
llvm-svn: 327843
2018-03-19 14:07:23 +00:00
Matt Arsenault 69932e4d69 AMDGPU: Don't leave dead illegal VGPR->SGPR copies
Normally DCE kills these, but at -O0 these get left behind
leaving suspicious looking illegal copies.

Replace with IMPLICIT_DEF to avoid iterator issues.

llvm-svn: 327842
2018-03-19 14:07:15 +00:00
Karl-Johan Karlsson 1af12b587b [NFC] Fix minor typos in comments
llvm-svn: 327841
2018-03-19 13:48:40 +00:00
Clement Courbet 6d047b70a4 [MergeICmps] Re-land 324317 "Enable the MergeICmps Pass by default."
Now that PR36557 is fixed.

llvm-svn: 327840
2018-03-19 13:37:04 +00:00
Sjoerd Meijer d16037d9bb [ARM] Support for v4f16 and v8f16 vectors
This is the groundwork for adding the Armv8.2-A FP16 vector intrinsics, which
uses v4f16 and v8f16 vector operands and return values. All the moving parts
are tested with two intrinsics, a 1-operand v8f16 and a 2-operand v4f16
intrinsic. In a follow-up patch the rest of the intrinsics and tests will be
added.

Differential Revision: https://reviews.llvm.org/D44538

llvm-svn: 327839
2018-03-19 13:35:25 +00:00
Xin Tong 116c309181 Stylish change. NFC
llvm-svn: 327838
2018-03-19 13:35:23 +00:00
Andrea Di Biagio 91ab2ee954 [llvm-mca] Add pipeline stall events.
This patch introduces a new class named HWStallEvent (see HWEventListener.h),
and updates the event listener interface. A HWStallEvent represents a pipeline
stall caused by the lack of hardware resources. Similarly to HWInstructionEvent,
the event type is an unsigned, and the exact meaning depends on the subtarget.
At the moment, HWStallEvent supports a few generic dispatch events.

The main goals of this patch is to remove the logic that counts dispatch stalls
from the DispatchUnit to the BackendStatistics view.

Previously, DispatchUnit was responsible for counting and classifying dispatch
stall events. With this patch, we delegate the task of counting and classifying
stall events to the listeners (i.e. in our case, it is view
"BackendStatistics"). So, the DispatchUnit doesn't have to do extra
(unnecessary) bookkeeping.

This patch also helps futher simplifying the Backend interface. Now class
BackendStatistics no longer has to query the Backend interface to obtain the
number of dispatch stalls. As a consequence, we can get rid of all the
'getNumXXX()' methods from class Backend.
The long term goal is to remove all the remaining dependencies between the
Backend and the BackendStatistics interface.

Differential Revision: https://reviews.llvm.org/D44621

llvm-svn: 327837
2018-03-19 13:23:07 +00:00
Hans Wennborg f646bcc2de build_llvm_package.bat: Drop LLDB from the package.
I don't think anyone ever got this to work, what with getting exactly
the right Python dependency and so on. Removing it simplifies the
script, removes a number of hairy dependencies, and cuts ~30 MB off the
installer size.

llvm-svn: 327835
2018-03-19 13:05:37 +00:00
Jonas Paulsson a6216ec4cc [SystemZ] Bugfix of CC liveness in emitMemMemWrapper (CLC).
If DoneMBB becomes empty it must have CC added to its live-in list, since it
will fall-through into EndMBB. This happens when the CLC loop does the
complete range.

Review: Ulrich Weigand
llvm-svn: 327834
2018-03-19 13:05:22 +00:00
Hans Wennborg 13e8a85820 HexagonISelLowering.cpp: fix 'enum in bool context' warning
llvm-svn: 327832
2018-03-19 12:55:58 +00:00
Alex Bradbury 0171a9f4ec [RISCV] Peephole optimisation for load/store of global values or constant addresses
(load (add base, off), 0) -> (load base, off)
(store val, (add base, off)) -> (store val, base, off)

This is similar to an equivalent peephole optimisation in PPCISelDAGToDAG.

llvm-svn: 327831
2018-03-19 11:54:28 +00:00
Alexander Potapenko fa0217276a [MSan] fix the types of RegSaveAreaPtrPtr and OverflowArgAreaPtrPtr
Despite their names, RegSaveAreaPtrPtr and OverflowArgAreaPtrPtr
used to be i8* instead of i8**.

This is important, because these pointers are dereferenced twice
(first in CreateLoad(), then in getShadowOriginPtr()), but for some
reason MSan allowed this - most certainly because it was possible
to optimize getShadowOriginPtr() away at compile time.

Differential revision: https://reviews.llvm.org/D44520

llvm-svn: 327830
2018-03-19 10:08:04 +00:00
Alexander Potapenko 014ff63f24 [MSan] Don't create zero offsets in getShadowPtrForArgument(). NFC
For MSan instrumentation with MS.ParamTLS and MS.ParamOriginTLS being
TLS variables, the CreateAdd() with ArgOffset==0 is a no-op, because
the compiler is able to fold the addition of 0.

But for KMSAN, which receives ParamTLS and ParamOriginTLS from a call
to the runtime library, this introduces a stray instruction which
complicates reading/testing the IR.

Differential revision: https://reviews.llvm.org/D44514

llvm-svn: 327829
2018-03-19 10:03:47 +00:00
Alexander Potapenko e0bafb4359 [MSan] Introduce insertWarningFn(). NFC
This is a step towards the upcoming KMSAN implementation patch.
KMSAN is going to use a different warning function,
__msan_warning_32(uptr origin), so we'd better create the warning
calls in one place.

Differential Revision: https://reviews.llvm.org/D44513

llvm-svn: 327828
2018-03-19 09:59:44 +00:00
Mikhail Maltsev f07278ec31 [ARM] Fix warnings about missing parentheses in ARMAsmParser
llvm-svn: 327827
2018-03-19 09:48:58 +00:00
Serguei Katkov 7d0664b41f [SCEV] Factor out isKnownViaInduction. NFC.
This just extracts the isKnownViaInduction from isKnownPredicate.

Reviewers: sanjoy, mkazantsev, reames
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44554

llvm-svn: 327824
2018-03-19 08:32:09 +00:00
Serguei Katkov 529f42331e [SCEV] Re-land: Fix isKnownPredicate
This is re-land of https://reviews.llvm.org/rL327362 with a fix
and regression test.

The crash was due to it is possible that for found MDL loop,
LHS or RHS may contain an invariant unknown SCEV which
does not dominate the MDL. Please see regression
test for an example.

Reviewers: sanjoy, mkazantsev, reames
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44553

llvm-svn: 327822
2018-03-19 06:35:30 +00:00
Craig Topper e18fbab988 [X86] Merge XADD8rr regular expression with XADD16rr/XADD32rr/XADD64rr in a couple scheduler models.
llvm-svn: 327821
2018-03-19 04:21:42 +00:00
Craig Topper d10ceffa5f [X86] Add ADD16i16/ADD32i32/ADD64i32 and similar to the scheduler models to match ADD8i8.
Also move ADC8i8 and SBB8i8 in the Sandy Bridge model to the same class as ADC8ri and SBB8ri. That seems more accurate since its the 8i8 is just the register forced to AL instead of coming from modrm.

llvm-svn: 327820
2018-03-19 04:21:40 +00:00
Craig Topper e9c99d32b3 [X6] Remove two unused InstrItinClass
llvm-svn: 327819
2018-03-19 02:07:32 +00:00
Craig Topper 793733a6c8 [X86] Use IIC_CMOV64_RR/RM on 64-bit cmov instructions.
llvm-svn: 327817
2018-03-19 00:56:12 +00:00
Craig Topper 9b60dcb29b [X86] Merge 32 and 64-bit RORX/SHLX/SARX/SHRX into single regular expressions in scheduler models.
llvm-svn: 327816
2018-03-19 00:56:11 +00:00
Craig Topper 13a1650d8a [X86] Merge 8-bit instructions into instregex with 16/32/64 instructions in the scheduler models as much as possible. NFCI
This reduces the total number of generated scheduler classes from 5404 to 5316.

llvm-svn: 327815
2018-03-19 00:56:09 +00:00