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314 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes e3acfd4d58 Add more 256-bit forms for a bunch of regular AVX instructions 
Add 64-bit (GR64) versions of some instructions (which are not
described in their SSE forms, but are described in AVX)

llvm-svn: 109063
 2010-07-21 23:53:50 +00:00
Bruno Cardoso Lopes 6238c1d102 Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it 
llvm-svn: 109039
 2010-07-21 21:37:59 +00:00
Bruno Cardoso Lopes cdbec62510 Add AVX only vzeroall and vzeroupper instructions 
llvm-svn: 109002
 2010-07-21 08:56:24 +00:00
Bruno Cardoso Lopes 3499934da6 Add new AVX vpermilps, vpermilpd and vperm2f128 instructions 
llvm-svn: 108984
 2010-07-21 03:07:42 +00:00
Bruno Cardoso Lopes 3ceaf7a0a2 Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it 
llvm-svn: 108983
 2010-07-21 02:46:58 +00:00
Bruno Cardoso Lopes e706501975 Add new AVX vextractf128 instructions 
llvm-svn: 108964
 2010-07-20 23:19:02 +00:00
Matt Fleming c3eb5e3d4b Include some tests for the recently committed ELF section directive 
handlers.

llvm-svn: 108938
 2010-07-20 21:37:30 +00:00
Bruno Cardoso Lopes 3b505848fd Add new AVX instruction vinsertf128 
llvm-svn: 108892
 2010-07-20 19:44:51 +00:00
Bruno Cardoso Lopes 6c8041ea34 x86_32 tests for vbroadcast 
llvm-svn: 108789
 2010-07-20 00:11:50 +00:00
Bruno Cardoso Lopes 14c5fd437c Add AVX vbroadcast new instruction 
llvm-svn: 108788
 2010-07-20 00:11:13 +00:00
Bruno Cardoso Lopes 9de0ca73d4 Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions! 
llvm-svn: 108769
 2010-07-19 23:32:44 +00:00
Daniel Dunbar 9db7d0addd X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same 
instruction, we only want to allow the one for the current subtarget.
 - This also fixes suffix matching for jmp instructions, because it eliminates
   the ambiguity between 'jmpl' and 'jmpq'.

llvm-svn: 108746
 2010-07-19 20:44:16 +00:00
Daniel Dunbar 9aefb8ee4c X86-64: Mark WINCALL and more tail call instructions as code gen only. 
llvm-svn: 108685
 2010-07-19 07:21:07 +00:00
Daniel Dunbar b82cd9319b MC/X86: We now match instructions like "incl %eax" correctly for the arch we are 
assembling; remove crufty custom cleanup code.

llvm-svn: 108681
 2010-07-19 06:14:54 +00:00
Daniel Dunbar af75e1923c tests: Force another triple. 
llvm-svn: 108666
 2010-07-19 00:43:58 +00:00
Daniel Dunbar 3b4621103a tests: Force triples. 
llvm-svn: 108658
 2010-07-18 21:16:10 +00:00
Daniel Dunbar 40a564f09f MC/AsmParser: Fix .abort and .secure_log_unique to accept arbitrary token 
sequences, not just strings.

llvm-svn: 108655
 2010-07-18 20:15:59 +00:00
Daniel Dunbar 6fb1c3ad8a MC/AsmParser: Add macro argument substitution support. 
llvm-svn: 108654
 2010-07-18 19:00:10 +00:00
Daniel Dunbar 4323571efb MC/AsmParser: Add basic support for macro instantiation. 
llvm-svn: 108653
 2010-07-18 18:54:11 +00:00
Daniel Dunbar c1f58ec83c MC/AsmParser: Add basic parsing support for .macro definitions. 
llvm-svn: 108652
 2010-07-18 18:47:21 +00:00
Daniel Dunbar 828984ff4e MC/AsmParser: Add .macros_{off,on} support, not that makes sense since we don't 
support macros.

llvm-svn: 108649
 2010-07-18 18:38:02 +00:00
Eli Friedman ceb16a5ce9 Test for ELF .size directive. 
llvm-svn: 108607
 2010-07-17 03:15:24 +00:00
Bruno Cardoso Lopes 6c6c14a55c Add AVX 256-bit compare instructions and a bunch of testcases 
llvm-svn: 108286
 2010-07-13 22:06:38 +00:00
Bruno Cardoso Lopes fd8bfcd6e1 AVX 256-bit conversion instructions 
Add the x86 VEX_L form to handle special cases where VEX_L must be set.

llvm-svn: 108274
 2010-07-13 21:07:28 +00:00
Bruno Cardoso Lopes dff283e146 Add AVX 256-bit packed logical forms 
llvm-svn: 108224
 2010-07-13 02:38:35 +00:00
Bruno Cardoso Lopes 36b32aeaa5 Add AVX 256-bit unop arithmetic instructions 
llvm-svn: 108223
 2010-07-13 01:53:31 +00:00
Bruno Cardoso Lopes 8e67a0482e Add AVX 256 binary arithmetic instructions 
llvm-svn: 108207
 2010-07-12 23:04:15 +00:00
Bruno Cardoso Lopes f9bcaad76d Add AVX 256-bit MOVMSK forms 
llvm-svn: 108184
 2010-07-12 20:06:32 +00:00
Daniel Dunbar d388c93f87 MC/AsmParser: Move .tbss and .zerofill parsing to Darwin specific parser. 
llvm-svn: 108180
 2010-07-12 19:37:35 +00:00
Daniel Dunbar 63a379dd5c MC/AsmParser: Move .desc parsing to Darwin specific parser. 
llvm-svn: 108179
 2010-07-12 19:22:53 +00:00
Daniel Dunbar ae9da1481a MC/AsmParser: Move some misc. Darwin directive handling to DarwinAsmParser. 
llvm-svn: 108174
 2010-07-12 18:49:22 +00:00
Bruno Cardoso Lopes 2419606bfb Add AVX 256-bit packed MOVNT variants 
llvm-svn: 108021
 2010-07-09 21:42:42 +00:00
Bruno Cardoso Lopes 6bc772eec7 Add AVX 256-bit unpack and interleave 
llvm-svn: 108017
 2010-07-09 21:20:35 +00:00
Bruno Cardoso Lopes 792e906bef Start the support for AVX instructions with 256-bit %ymm registers. A couple of 
notes:
- The instructions are being added with dummy placeholder patterns using some 256
  specifiers, this is not meant to work now, but since there are some multiclasses
  generic enough to accept them,  when we go for codegen, the stuff will be already
  there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
  file.

llvm-svn: 107996
 2010-07-09 18:27:43 +00:00
Chris Lattner 9f034c1e5d Rework segment prefix emission code to handle segments 
in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax

This fixes rdar://8127102.  I have several cleanup patches coming
next.

llvm-svn: 107917
 2010-07-08 22:28:12 +00:00
Chris Lattner ac5881295c Implement the major chunk of PR7195: support for 'callw' 
in the integrated assembler.  Still some discussion to be
done.

llvm-svn: 107825
 2010-07-07 22:27:31 +00:00
Bruno Cardoso Lopes 6c61451011 Add more assembly opcodes for SSE compare instructions 
llvm-svn: 107823
 2010-07-07 22:24:03 +00:00
Bruno Cardoso Lopes fd8060335b Add AVX AES instructions 
llvm-svn: 107798
 2010-07-07 18:24:20 +00:00
Bruno Cardoso Lopes 6d122aef97 Add AVX SSE4.2 instructions 
llvm-svn: 107752
 2010-07-07 03:39:29 +00:00
Bruno Cardoso Lopes 8f5472a8e8 Add AVX SSE4.1 insertps, ptest and movntdqa instructions 
llvm-svn: 107747
 2010-07-07 01:14:56 +00:00
Bruno Cardoso Lopes 6430c7350d Add AVX SSE4.1 extractps and pinsr instructions 
llvm-svn: 107746
 2010-07-07 01:01:13 +00:00
Bruno Cardoso Lopes f3116ebe96 Add AVX SSE4.1 Extract Integer instructions 
llvm-svn: 107740
 2010-07-07 00:07:24 +00:00
Bruno Cardoso Lopes 1f9ad516c6 Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions 
llvm-svn: 107723
 2010-07-06 23:15:17 +00:00
Bruno Cardoso Lopes 35702d27c4 Add part of AVX SSE4.1 packed move with sign/zero extend instructions 
llvm-svn: 107720
 2010-07-06 23:01:41 +00:00
Bruno Cardoso Lopes e2bd058d32 Add AVX vblendvpd, vblendvps and vpblendvb instructions 
Update VEX encoding to support those new instructions

llvm-svn: 107715
 2010-07-06 22:36:24 +00:00
Bruno Cardoso Lopes ca99012ac0 Add AVX SSE4.1 blend, mpsadbw and vdp 
llvm-svn: 107560
 2010-07-03 01:37:03 +00:00
Bruno Cardoso Lopes bc75502f09 Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions 
llvm-svn: 107558
 2010-07-03 01:15:47 +00:00
Bruno Cardoso Lopes fc9cdc4d61 Add AVX SSE4.1 Horizontal Minimum and Position instruction 
llvm-svn: 107552
 2010-07-03 00:49:21 +00:00
Bruno Cardoso Lopes 621c85b038 Add AVX SSE4.1 round instructions 
llvm-svn: 107549
 2010-07-03 00:37:44 +00:00
Bruno Cardoso Lopes c7111fd355 - Add support for the rest of AVX SSE3 instructions 
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode

llvm-svn: 107523
 2010-07-02 22:06:54 +00:00
Bruno Cardoso Lopes 5e88700f28 Move SSE3 Move patterns to a more appropriate section 
Add AVX SSE3 packed horizontal and & sub instructions

llvm-svn: 107405
 2010-07-01 17:35:02 +00:00
Bruno Cardoso Lopes 886ee33a38 Add AVX SSE3 packed addsub instructions 
llvm-svn: 107404
 2010-07-01 17:08:18 +00:00
Bruno Cardoso Lopes a7a0c83563 Add AVX SSE3 replicate and convert instructions 
llvm-svn: 107375
 2010-07-01 02:33:39 +00:00
Bruno Cardoso Lopes 05166740eb - Add AVX SSE2 Move doubleword and quadword instructions. 
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.

llvm-svn: 107365
 2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes cbcebe2950 Add AVX SSE2 mask creation and conditional store instructions 
llvm-svn: 107306
 2010-06-30 18:38:10 +00:00
Bruno Cardoso Lopes d079c91683 Add AVX SSE2 packed integer extract/insert instructions 
llvm-svn: 107293
 2010-06-30 17:03:03 +00:00
Bruno Cardoso Lopes e82689fea2 Add AVX SSE2 integer unpack instructions 
llvm-svn: 107246
 2010-06-30 04:06:39 +00:00
Bruno Cardoso Lopes ec0115c9b7 Add AVX SSE2 packed integer shuffle instructions 
llvm-svn: 107245
 2010-06-30 03:47:56 +00:00
Bruno Cardoso Lopes be792feb8b Add AVX SSE2 pack with saturation integer instructions 
llvm-svn: 107241
 2010-06-30 02:30:25 +00:00
Bruno Cardoso Lopes 2686ea4555 Add AVX SSE2 integer packed compare instructions 
llvm-svn: 107240
 2010-06-30 02:21:09 +00:00
Bruno Cardoso Lopes 2e2caefff9 - Add AVX form of all SSE2 logical instructions 
- Add VEX encoding bits to x86 MRM0r-MRM7r

llvm-svn: 107238
 2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes 3f71ddfaad Add *several* AVX integer packed binop instructions 
llvm-svn: 107225
 2010-06-29 23:47:49 +00:00
Bruno Cardoso Lopes 30689a3a7f Add AVX ld/st XCSR register. 
Add VEX encoding bits for MRMXm x86 form

llvm-svn: 107204
 2010-06-29 20:35:48 +00:00
Bruno Cardoso Lopes a4575f5b31 Add AVX non-temporal stores 
llvm-svn: 107178
 2010-06-29 18:22:01 +00:00
Bruno Cardoso Lopes 21a9433e9e Add sqrt, rsqrt and rcp AVX instructions 
llvm-svn: 107166
 2010-06-29 17:26:30 +00:00
Bruno Cardoso Lopes d6a091a4d4 Described the missing AVX forms of SSE2 convert instructions 
llvm-svn: 107108
 2010-06-29 00:36:02 +00:00
Bruno Cardoso Lopes 74d716b9cd Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions 
llvm-svn: 106917
 2010-06-25 23:47:23 +00:00
Bruno Cardoso Lopes 83651094ad Reapply r106896: 
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg

llvm-svn: 106912
 2010-06-25 23:33:42 +00:00
Bruno Cardoso Lopes 4530fed87e revert this now, it's using avx instead of sse :) 
llvm-svn: 106906
 2010-06-25 23:04:29 +00:00
Bruno Cardoso Lopes a34d9b6d84 Add several AVX MOV flavors 
Support VEX encoding for MRMDestReg

llvm-svn: 106896
 2010-06-25 22:27:51 +00:00
Bruno Cardoso Lopes cbdcce6478 Add some AVX convert instructions 
llvm-svn: 106815
 2010-06-25 00:39:30 +00:00
Bruno Cardoso Lopes 4398fd7b83 - Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}. 
- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.

llvm-svn: 106787
 2010-06-24 20:48:23 +00:00
Chris Lattner 8048662539 Teach the x86 mc assembler that %dr6 = %db6, this implements 
rdar://8013734

llvm-svn: 106725
 2010-06-24 07:29:18 +00:00
Bruno Cardoso Lopes 191a1cd2bb Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases 
llvm-svn: 106705
 2010-06-24 00:32:06 +00:00
Bruno Cardoso Lopes 05220c9a0d Add AVX MOVMSK{PS,PD}rr instructions 
llvm-svn: 106683
 2010-06-23 21:30:27 +00:00
Bruno Cardoso Lopes 3183dd5692 Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction 
llvm-svn: 106678
 2010-06-23 21:10:57 +00:00
Bruno Cardoso Lopes 360d6fe299 Add AVX SHUF{PS,PD}{rr,rm} instructions 
llvm-svn: 106672
 2010-06-23 20:07:15 +00:00
Nico Weber 337e8db712 Add support for the x86 instructions "pusha" and "popa". 
llvm-svn: 106671
 2010-06-23 20:00:58 +00:00
Bruno Cardoso Lopes 1e13c17a55 Add AVX compare packed instructions 
llvm-svn: 106600
 2010-06-22 23:37:59 +00:00
Bruno Cardoso Lopes 535aa8ea91 Reapply support for AVX unpack and interleave instructions, with 
testcases this time.

llvm-svn: 106593
 2010-06-22 23:02:38 +00:00
Bruno Cardoso Lopes 1a890f9dc0 Add AVX MOV{SS,SD}{rr,rm} instructions 
llvm-svn: 106588
 2010-06-22 22:38:56 +00:00
Eric Christopher 6250bd9e3c Move a 64-bit test to the 64-bit file. Fixes an llvm-mc assertion 
during test runs.

llvm-svn: 106577
 2010-06-22 21:11:51 +00:00
Bruno Cardoso Lopes 8737b7d73d Refactor aliased packed logical instructions, also add 
AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.

llvm-svn: 106374
 2010-06-19 02:44:01 +00:00
Bruno Cardoso Lopes 1e205f6b1c Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions 
llvm-svn: 106366
 2010-06-19 00:37:31 +00:00
Chris Lattner e808a78ac1 fix rdar://7873482 by teaching the instruction encoder to emit 
segment prefixes.  Daniel wrote most of this patch.

llvm-svn: 106364
 2010-06-19 00:34:00 +00:00
Bruno Cardoso Lopes 2323168705 Add {mix,max}{ss,sd}{rr,rm} AVX forms. 
llvm-svn: 106264
 2010-06-18 01:12:56 +00:00
Bruno Cardoso Lopes a714ea0f7d More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rm 
llvm-svn: 105870
 2010-06-12 01:53:48 +00:00
Bruno Cardoso Lopes b06f54b852 More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rr 
Handle OpSize TSFlag for AVX

llvm-svn: 105869
 2010-06-12 01:23:26 +00:00
Bruno Cardoso Lopes fd5458d4bd More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm) 
Introduce the VEX_X field

llvm-svn: 105859
 2010-06-11 23:50:47 +00:00
Bruno Cardoso Lopes c2f87b7bb2 Reapply r105521, this time appending "LLU" to 64 bit 
immediates to avoid breaking the build.

llvm-svn: 105652
 2010-06-08 22:51:23 +00:00
Chris Lattner fdd2614330 revert r105521, which is breaking the buildbots with stuff like this: 
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type

llvm-svn: 105524
 2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes 594fa26317 Initial AVX support for some instructions. No patterns matched 
yet, only assembly encoding support.

llvm-svn: 105521
 2010-06-05 03:53:24 +00:00
Kevin Enderby 4c71e08ed8 MC/X86: Add alias for movzx. 
llvm-svn: 105005
 2010-05-28 21:20:21 +00:00
Kevin Enderby b29228905f MC/X86: Add alias for fwait. 
llvm-svn: 105001
 2010-05-28 20:59:10 +00:00
Kevin Enderby 76413597a9 Fix the use of x86 control and debug registers so that the assertion failure in 
getX86RegNum() does not happen.  Patch by Shantonu Sen!

llvm-svn: 104994
 2010-05-28 19:01:27 +00:00
Kevin Enderby 70e34983e8 Fix the x86 move to/from segment register instructions. 
llvm-svn: 104731
 2010-05-26 20:10:45 +00:00
Kevin Enderby 492d4f409a Changed the encoding of X86 floating point stack operations where both operands 
are st(0).  These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0.  To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used.  To do this the same logical trick is use from the darwin assembler
in converting things like this:

fmul %st(0), %st

into this:

fmul %st(0)

by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand.  This also has the add
benefit to allow things like:

fmul %st(1), %st

that llvm-mc did not assemble.

llvm-svn: 104634
 2010-05-25 20:52:34 +00:00
Daniel Dunbar 0e767d7364 MC/X86: Add a hack to allow recognizing 'cmpltps' and friends. 
llvm-svn: 104626
 2010-05-25 19:49:32 +00:00
Daniel Dunbar 4a5b2c597b MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}. 
llvm-svn: 104622
 2010-05-25 18:40:53 +00:00
Kevin Enderby c798965e63 The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required 
for the 64-bit version of the Bit Test instruction.

llvm-svn: 104621
 2010-05-25 18:16:58 +00:00