Commit Graph

319356 Commits

Author SHA1 Message Date
Stanislav Mekhanoshin ab4f2ea793 [AMDGPU] gfx1010 disassembler changes for wave32
Differential Revision: https://reviews.llvm.org/D63506

llvm-svn: 363721
2019-06-18 19:10:59 +00:00
Alexey Bataev 7ae267dc0f [OPENMP][NVPTX]Correct codegen for 128 bit long double.
If the host uses 128 bit long doubles, the compiler should generate correct code for NVPTX devices. If the return type has 128 bit long doubles, in LLVM IR this type must be coerced to int array instead.

llvm-svn: 363720
2019-06-18 19:04:27 +00:00
Craig Topper 10e6128c62 [X86] Remove unnecessary line that makes v4f32 FP_ROUND Legal. NFC
FP_ROUND defaults to Legal for all MVT types and nothing changes
the v4f32 entry way from this default. If we needed this line
we'd also need one for v8f32 with AVX512 which we don't have.

llvm-svn: 363719
2019-06-18 19:04:03 +00:00
Jordan Rupprecht 33e85ad956 Revert [SROA] Enhance SROA to handle `addrspacecast`ed allocas
This reverts r363711 (git commit 76a149ef81)

This causes stage2 build failures, e.g.:
http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/132/steps/stage%202%20build/logs/stdio
http://lab.llvm.org:8011/builders/ppc64le-lld-multistage-test/builds/87/steps/build-stage2-unified-tree/logs/stdio

llvm-svn: 363718
2019-06-18 18:40:04 +00:00
Alexey Bataev 8557d1ac98 [OPENMP]Use host's long double when compiling the code for device.
The device code must use the same long double type as the host.
Otherwise the code cannot be linked and executed properly. Patch adds
only basic support and checks for supporting of the host long double
double on the device.

llvm-svn: 363717
2019-06-18 18:39:26 +00:00
Simon Pilgrim 5bef886cd8 [TargetLowering] SimplifyDemandedBits - Cleanup ANY_EXTEND handling
Match SIGN_EXTEND + ZERO_EXTEND handling - will be adding ANY_EXTEND_VECTOR_INREG support in a future patch.

llvm-svn: 363716
2019-06-18 18:22:30 +00:00
Marshall Clow 8dc6840f1c Fix the floating point version of midpoint. It wasn't constexpr, among other things. Add more tests. As a drive-by, the LCD implementation had a class named '__abs' which did a 'absolute value to a common-type' conversion. Rename that to be '__ct_abs'.
llvm-svn: 363714
2019-06-18 18:13:54 +00:00
Simon Pilgrim 032b54f8e8 [TargetLowering] SimplifyDemandedBits - Merge ZERO_EXTEND+ZERO_EXTEND_VECTOR_INREG handling
Other than adding consistent demanded elts handling which was a trivial addition, the other differences in functionality will be added in later patches.

llvm-svn: 363713
2019-06-18 18:08:30 +00:00
Julie Hockett d9b3d08a9a [clang-tidy] Split fuchsia-default-arguments
Splits fuchsia-default-arguments check into two checks. fuchsia-default-arguments-calls warns if a function or method is called with default arguments. fuchsia-default-arguments-declarations warns if a function or method is declared with default parameters.

Committed on behalf of @diegoast (Diego Astiazarán).

Resolves b38051.

Differential Revision: https://reviews.llvm.org/D62437

llvm-svn: 363712
2019-06-18 18:07:33 +00:00
Michael Liao 76a149ef81 [SROA] Enhance SROA to handle `addrspacecast`ed allocas
Summary:
- After `addrspacecast` is allowed to be eliminated in SROA, the
  adjusting of storage pointer (from `alloca) needs to handle the
  potential different address spaces between the storage pointer (from
  alloca) and the pointer being used.

Reviewers: arsenm

Subscribers: wdng, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63501

llvm-svn: 363711
2019-06-18 17:58:49 +00:00
Simon Pilgrim b6e7108dcd [TargetLowering] SimplifyDemandedBits - Merge SIGN_EXTEND+SIGN_EXTEND_VECTOR_INREG handling
Other than adding consistent demanded elts handling which was a trivial addition, the other differences in functionality will be added in later patches.

llvm-svn: 363710
2019-06-18 17:57:53 +00:00
Aaron Ballman d4a1c3bb5a Add test cases for dumping AST function decl nodes to JSON; NFC.
llvm-svn: 363709
2019-06-18 17:56:50 +00:00
Antonio Afonso fda83c9b0b Implement xfer:libraries-svr4:read packet
Summary:
This is the fourth patch to improve module loading in a series that started here (where I explain the motivation and solution): D62499

Implement the `xfer:libraries-svr4` packet by adding a new function that generates the list and then in Handle_xfer I generate the XML for it. The XML is really simple so I'm just using string concatenation because I believe it's more readable than having to deal with a DOM api.

Reviewers: clayborg, xiaobai, labath

Reviewed By: labath

Subscribers: emaste, mgorny, srhines, krytarowski, lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D62502

llvm-svn: 363707
2019-06-18 17:51:56 +00:00
Kostya Kortchinsky 5cf216c9a7 [scudo][standalone] Fuchsia related changes
Summary:
Fuchsia wants to use mutexes with PI in the Scudo code, as opposed to
our own implementation. This required making `lock` & `unlock` platform
specific (as opposed to `wait` & `wake`) [code courtesy of John
Grossman].
There is an additional flag required now for mappings as well:
`ZX_VM_ALLOW_FAULTS`.

Reviewers: morehouse, mcgrathr, eugenis, vitalybuka, hctim

Reviewed By: morehouse

Subscribers: delcypher, jfb, #sanitizers, llvm-commits

Tags: #llvm, #sanitizers

Differential Revision: https://reviews.llvm.org/D63435

llvm-svn: 363705
2019-06-18 17:41:17 +00:00
Sanjay Patel 223176f5d7 [x86] add test for load splitting with extracted store (PR42305); NFC
llvm-svn: 363704
2019-06-18 17:16:17 +00:00
Simon Atanasyan 796e7f8724 [mips] Add more strict predicates to the RSQRT_S_MM and TAILCALL_MM
This patch is one of a series of patches. The goal is to make P5600
scheduler model complete and turn on the `CompleteModel` flag.

llvm-svn: 363703
2019-06-18 17:00:08 +00:00
Simon Atanasyan 60a9d0c248 [mips] Add PTR_64 and GPR_64 predicates to some MIPS 64-bit instructions
Add `IsGP64bit` and `IsPTR64bit` to the list of `UnsupportedFeatures`
of the P5600 scheduling definitions. Also mark some MIPS 64-bit
instructions by PTR_64 and GPR_64 predicates. This reduces number
of "No schedule information for" and "lacks information for" errors
in case of marking this scheduler model as complete.

This patch is one of a series of patches. The goal is to make P5600
scheduler model complete and turn on the `CompleteModel` flag.

Differential Revision: https://reviews.llvm.org/D63237

llvm-svn: 363702
2019-06-18 16:59:57 +00:00
Simon Atanasyan 9086ba8763 [mips] Set the hasNoSchedulingInfo flag for the `MipsAsmPseudoInst`
Set the hasNoSchedulingInfo flag for the`MipsAsmPseudoInst`. These
pseudo-instructions are never used by codegen. This flag allows to
reduce number of "No schedule information for" and "lacks information
for" errors in case of marking a scheduler model as complete.

This patch is one of a series of patches. The goal is to make P5600
scheduler model complete and turn on the `CompleteModel` flag.

Differential Revision: https://reviews.llvm.org/D63236

llvm-svn: 363701
2019-06-18 16:59:47 +00:00
Adrian McCarthy 46e6e13298 Fix some lit test ResourceWarnings on Windows
When running LLDB lit tests on Windows, the system selects a debug version
of Python, which was issuing lots of ResourceWarnings about files that
weren't closed.  There are two kinds of them, and each test triggered one
of each.

This patch fixes one kind by ensuring TestRunner explicitly close the
temporary files created for routing stderr.  This is important on Windows
but has no net effect on Posix systems.

The remaining ResourceWarnings are more elusive; the bug may lie in
the Python library subprocess.py, and it may be Windows-specific.

Differential Revision: https://reviews.llvm.org/D63102

llvm-svn: 363700
2019-06-18 16:36:57 +00:00
Aaron Ballman 3559d2224e Add test cases for dumping AST decl nodes to JSON; NFC.
llvm-svn: 363699
2019-06-18 16:36:49 +00:00
Ilya Biryukov 5aed309a4f [Syntax] Add a helper to find expansion by its first spelled token
Summary: Used in clangd for a code tweak that expands a macro.

Reviewers: sammccall

Reviewed By: sammccall

Subscribers: kadircet, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D62954

llvm-svn: 363698
2019-06-18 16:27:27 +00:00
Jonas Devlieghere c470ac50a8 [Reproducers] Make reproducer relocatable
Before this patch, reproducers weren't relocatable. The reproducer
contained hard coded paths in the VFS mapping, as well in the yaml file
listing the different input files for the command interpreter. This
patch changes that:

 - Use relative paths for the DataCollector.
 - Use an overlay prefix for the FileCollector.

Differential revision: https://reviews.llvm.org/D63467

llvm-svn: 363697
2019-06-18 16:20:17 +00:00
Simon Tatham cfc70782d7 [ARM] Add MVE vector shift instructions.
This includes saturating and non-saturating shifts, both with
immediate shift count and with the shift counts given by another
vector register; VSHLC (in which the bits shifted out of each active
vector lane are shifted in to the next active lane); and also VMOVL,
which is enough like an immediate shift that it didn't fit too badly
in this category.

Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62672

llvm-svn: 363696
2019-06-18 16:19:59 +00:00
Simon Tatham faaf1a5366 [ARM] Add MVE integer vector min/max instructions.
Summary:
These form a small family of their own, to go with the floating-point
VMINNM/VMAXNM instructions added in a previous commit.

They introduce the first of many special cases in the mnemonic
recognition code, because VMIN with the E suffix used by the VPT
predication system needs to avoid being interpreted as the nonexistent
instruction 'VMI' with an ordinary 'NE' condition suffix.

Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62671

llvm-svn: 363695
2019-06-18 15:51:46 +00:00
Simon Pilgrim 9aa25be149 [TargetLowering] SimplifyDemandedVectorElts - support MUL and ANY_EXTEND_VECTOR_INREG
Also fold ANY_EXTEND_VECTOR_INREG -> BITCAST if we only need the bottom element.

Fixes temporary regression introduced in rL363693.

llvm-svn: 363694
2019-06-18 15:49:35 +00:00
Simon Pilgrim 9c8593934a [X86][AVX] extract_subvector(any_extend(x)) -> any_extend_vector_inreg(x)
Part of fixing the X86 regression noted in D63281 - I've split this into X86 and generic parts - the generic commit will be coming shortly and will fix the vector-reduce-mul-widen.ll regression introduced here.

llvm-svn: 363693
2019-06-18 15:30:50 +00:00
Zhihao Yuan c74fc6d5f9 [libc++] Implement P0608R3 - A sane variant converting constructor
Summary:
Prefer user-defined conversions over narrowing conversions and conversions to bool.

References:
 http://wg21.link/p0608

Reviewers: EricWF, mpark, mclow.lists

Reviewed By: mclow.lists

Subscribers: zoecarver, ldionne, libcxx-commits, cfe-commits, christof

Differential Revision: https://reviews.llvm.org/D44865

llvm-svn: 363692
2019-06-18 15:26:50 +00:00
Ilya Biryukov df9ee08b64 [clangd] Return vector<TextEdit> from applyTweak. NFC
For the same reasons as r363150, which got overwritten by changes in
r363680.

Sending without review to unbreak our integrate.

llvm-svn: 363691
2019-06-18 15:15:41 +00:00
Simon Tatham ed4a602515 [ARM] Rename MVE instructions in Tablegen for consistency.
Summary:
Their names began with a mishmash of `MVE_`, `t2` and no prefix at
all. Now they all start with `MVE_`, which seems like a reasonable
choice on the grounds that (a) NEON is the thing they're most at risk
of being confused with, and (b) MVE implies Thumb-2, so a prefix
indicating MVE is strictly more specific than one indicating Thumb-2.

Reviewers: ostannard, SjoerdMeijer, dmgreen

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63492

llvm-svn: 363690
2019-06-18 15:05:42 +00:00
Louis Dionne 91185b69d1 [libc++] Re-apply XFAIL to is_base_of test that was inadvertently reverted
llvm-svn: 363689
2019-06-18 15:01:59 +00:00
Louis Dionne 1fab01f92b [libc++] Revert the addition of map/multimap CTAD
This was found to be broken on Clang trunk. This is a revert of the
following commits (the subsequent commits added XFAILs to the tests
that were missing from the original submission):

    r362986: Implement deduction guides for map/multimap.
    r363014: Add some XFAILs
    r363097: Add more XFAILs
    r363197: Add even more XFAILs

llvm-svn: 363688
2019-06-18 14:40:15 +00:00
Mikhail Maltsev a45292cbfd [CodeGen][ARM] Fix FP16 vector coercion
Summary:
When a function argument or return type is a homogeneous aggregate
which contains an FP16 vector but the target does not support FP16
operations natively, the type must be converted into an array of
integer vectors by then front end (otherwise LLVM will handle FP16
vectors incorrectly by scalarizing them and promoting FP16 to float,
see https://reviews.llvm.org/D50507).

Currently the logic for checking whether or not a given homogeneous
aggregate contains FP16 vectors is incorrect: it only looks at the
type of the first vector.

This patch fixes the issue by adding a new method
ARMABIInfo::containsAnyFP16Vectors and using it. The traversal logic
of this method is largely the same as in
ABIInfo::isHomogeneousAggregate.

Reviewers: eli.friedman, olista01, ostannard

Reviewed By: ostannard

Subscribers: ostannard, john.brawn, javed.absar, kristof.beyls, pbarrio, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D63437

llvm-svn: 363687
2019-06-18 14:34:27 +00:00
Lewis Revill 74c8364954 [RISCV] Lower calls through PLT
This patch adds support for generating calls through the procedure
linkage table where required for a given ExternalSymbol or GlobalAddress
callee.

Differential Revision: https://reviews.llvm.org/D55304

llvm-svn: 363686
2019-06-18 14:29:45 +00:00
Simon Pilgrim 2fef12ccb1 Fix -Wunused-but-set-variable warning. NFCI.
llvm-svn: 363685
2019-06-18 14:24:28 +00:00
Matt Arsenault 2acc717627 AMDGPU: Add GWS instruction builtins
llvm-svn: 363684
2019-06-18 14:10:01 +00:00
Fangrui Song 677423997d [llvm-readobj] Allow --hex-dump/--string-dump to dump multiple sections
1) `-x foo` currently dumps one `foo`. This change makes it dump all `foo`.
2) `-x foo -x foo` currently dumps `foo` twice. This change makes it dump `foo` once.
   In addition, if foo has section index 9, `-x foo -x 9` dumps `foo` once.
3) Give a warning instead of an error if `foo` does not exist.

The new behaviors match GNU readelf.

Also, print a new line as a separator between two section dumps.
GNU readelf uses two lines, but one seems good enough.

Reviewed By: grimar, jhenderson

Differential Revision: https://reviews.llvm.org/D63475

llvm-svn: 363683
2019-06-18 14:01:03 +00:00
Matt Arsenault d204987ada AMDGPU: Disable errno by default
llvm-svn: 363682
2019-06-18 13:59:32 +00:00
Haojian Wu 9483bcf781 [clangd] Remove the extra ";", NFC
llvm-svn: 363681
2019-06-18 13:52:00 +00:00
Sam McCall 395fde753c [clangd] Add hidden tweaks to dump AST/selection.
Summary:
This introduces a few new concepts:
 - tweaks have an Intent (they don't all advertise as refactorings)
 - tweaks may produce messages (for ShowMessage notification). Generalized
   Replacements -> Effect.
 - tweaks (and other features) may be hidden (clangd -hidden-features flag).
   We may choose to promote these one day. I'm not sure they're worth their own
   feature flags though.

Verified it in vim-clangd (not yet open source), curious if the UI is ok in VSCode.

Reviewers: ilya-biryukov

Subscribers: mgorny, MaskRay, jkorous, arphaman, kadircet, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D62538

llvm-svn: 363680
2019-06-18 13:37:54 +00:00
Ulrich Weigand 45b10d2da5 [compiler-rt][SystemZ] Work around ASAN failures via -fno-partial-inlining
Since updating the SystemZ LLVM build bot system to Ubuntu 18.04, all bots
are red due to two ASAN failures.  It turns out these are triggered due to
building the ASAN support libraries, in particular the interceptor routines
using GCC 7.  Specifically, at least on our platform, this compiler decides
to "partially inline" some of those interceptors, creating intermediate
stub routines like "__interceptor_recvfrom.part.321".  These will show up
in the backtraces at interception points, causing testsuite failures.

As a workaround to get the build bots green again, this patch adds the
-fno-partial-inlining command line option when building the common
sanitizer support libraries on s390x, if that option is supported by
the compiler.

llvm-svn: 363679
2019-06-18 13:26:27 +00:00
Matt Arsenault 8d35dcd703 AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics
There may or may not be additional work to handle this correctly on
SI/CI.

llvm-svn: 363678
2019-06-18 13:19:57 +00:00
Andrea Di Biagio 3b2f5df12c [MCA] Slightly refactor the bottleneck analysis view. NFCI
This patch slightly refactors data structures internally used by the bottleneck
analysis to track data and resource dependencies.
This patch also updates methods used to print out information about dependency
edges when in debug mode.
This is the last of a sequence of commits done in preparation for an upcoming
patch that fixes PR37494. No functional change intended.

llvm-svn: 363677
2019-06-18 12:59:46 +00:00
Aaron Ballman 7a89909c84 Require commas to separate multiple GNU-style attributes in the same attribute list.
Fixes PR38352.

llvm-svn: 363676
2019-06-18 12:57:05 +00:00
Matt Arsenault f39f3bd056 AMDGPU: Change API for checking for exec modification
Invert the name and return value to better reflect the imprecise
nature.

Force passing in the DefMI, since it's known in the 2 users and could
possibly fail for an arbitrary vreg.

Allow specifying a specific user instruction. Scan through use
instructions, instead of use operands. Add scan thresholds instead of
searching infinitely.

Stop using a set to track seen uses. I didn't understand this usage,
or why it would not check the last use. I don't think the use list has
any particular order.

llvm-svn: 363675
2019-06-18 12:48:36 +00:00
Fangrui Song c99d9aee00 MCContext: Delete unused functions
llvm-svn: 363674
2019-06-18 12:30:06 +00:00
Nico Weber 3c8e2cdda5 gn build: Merge r363658
llvm-svn: 363673
2019-06-18 12:29:04 +00:00
Nico Weber 7001fe8d14 gn build: Merge r363649
This reverts commit "gn build: Merge r363626" because r363626
was reverted in r363649.

llvm-svn: 363672
2019-06-18 12:26:31 +00:00
Simon Pilgrim 83bacd8d72 [SelectionDAG] Legalize vaargs that require vector splitting
This adds vector splitting for vaarg instructions during type legalization

Committed on behalf of @luke (Luke Lau)

Differential Revision: https://reviews.llvm.org/D60762

llvm-svn: 363671
2019-06-18 12:24:02 +00:00
Matt Arsenault bcb5ea0042 AMDGPU: Fold readlane from copy of SGPR or imm
These may be inserted to assert uniformity somewhere.

llvm-svn: 363670
2019-06-18 12:23:46 +00:00
Matt Arsenault e75e197ad8 AMDGPU: Remove unnecessary check for virtual register
The copy was found by searching the uses of a virtual register, so
it's already known to be virtual.

llvm-svn: 363669
2019-06-18 12:23:45 +00:00