dd7f566597
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
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llvm-svn: 104111
2010-05-19 06:07:03 +00:00
e89f5ae9d4
Target instruction selection should copy memoperands.
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llvm-svn: 104110
2010-05-19 06:06:09 +00:00
45ace40959
MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, to
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avoid same prefix byte problem as in r104062.
llvm-svn: 104108
2010-05-19 04:31:36 +00:00
e9ceb31405
Profile type-dependent uses of overloaded operators in C++ the same
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way regardless of whether some overloaded operator functions were
found by name lookup within the template. Fixes PR6851.
llvm-svn: 104107
2010-05-19 04:13:23 +00:00
21553f5970
Teach clang to instantiate attributes on more declarations. Fixes PR7102.
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llvm-svn: 104106
2010-05-19 03:39:53 +00:00
cbfbca14d0
Implement C++ builtin operator candidates for vector types.
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llvm-svn: 104105
2010-05-19 03:21:00 +00:00
425cec3e33
Fix a GCC warning about inline functions not being defined. Until r104081, only
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the same .cpp file as provided the definitions referenced these functions,
hiding the issue. However, they are clearly no longer inline. Let me know if
there is a reason to move their definitions to the header and make them truly
inline.
llvm-svn: 104104
2010-05-19 02:12:56 +00:00
fb0e5ec825
[rand.dist.samp.discrete]
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llvm-svn: 104103
2010-05-19 01:53:57 +00:00
2c452fcd14
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
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llvm-svn: 104102
2010-05-19 01:52:25 +00:00
eba788efa6
Fix an obvious goof that rjmccall found by inspection. No testcase, suggestions
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welcome for one.
llvm-svn: 104101
2010-05-19 01:37:01 +00:00
744c96dd48
Add a comment explaining why this code uses Append mode.
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llvm-svn: 104095
2010-05-19 01:21:34 +00:00
abd0ad54a4
Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
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The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.
Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.
llvm-svn: 104094
2010-05-19 01:08:17 +00:00
58c6f21453
Factor out the code for picking integer arithmetic with immediate
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opcodes into a helper function. This fixes a few places in the code
which were not properly selecting the 8-bit-immediate opcodes.
llvm-svn: 104091
2010-05-19 00:53:19 +00:00
c09d5a29d8
Add a test to make sure that we're lowering the shift amount correctly.
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llvm-svn: 104090
2010-05-19 00:22:04 +00:00
beebef4137
Add a comment.
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llvm-svn: 104089
2010-05-18 23:55:57 +00:00
50f8f2c23d
Fix the predicate which checks for non-sensical formulae which have
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constants in registers which partially cancel out their immediate fields.
llvm-svn: 104088
2010-05-18 23:48:08 +00:00
4cf99b5303
Factor out the code for recomputing an LSRUse's Regs set after some
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of its formulae have been removed into a helper function, and also
teach it how to update the RegUseTracker.
llvm-svn: 104087
2010-05-18 23:42:37 +00:00
055c01d9dc
Fix a crash when debugging the coalescer. DebugValue instructions are not
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in the coalescer's instruction map.
llvm-svn: 104086
2010-05-18 23:19:42 +00:00
bd130a2962
Basic test for user-defined conversions involving vector types
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llvm-svn: 104085
2010-05-18 23:05:44 +00:00
9f963c2488
Misc. fixes to bring Objetive-C++'s handling of
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gc attributes to be inline with Objective-C
(for radar 7925141).
llvm-svn: 104084
2010-05-18 23:04:17 +00:00
bdb604a806
Protect isIntegerConstantExpr from seeing type- or value-dependent
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expressions in attributes, pragmas.
llvm-svn: 104083
2010-05-18 23:01:22 +00:00
a4eca05174
Factor out code for estimating search space complexity into a helper
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function.
llvm-svn: 104082
2010-05-18 22:51:59 +00:00
4618868a7d
Implement C++ support for vector and extended vector types. This
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involves extending implicit conversion sequences to model vector
conversions and vector splats, along with teaching the C++ conditional
operator-checking code about vector types.
Fixes <rdar://problem/7983501>.
llvm-svn: 104081
2010-05-18 22:42:18 +00:00
63e9015248
Add some more debug output.
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llvm-svn: 104080
2010-05-18 22:41:32 +00:00
f1c7b1b42f
Factor out the code for deleting a formula from an LSRUse into
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a helper function.
llvm-svn: 104079
2010-05-18 22:39:15 +00:00
8aca7ef903
Make some debug output more informative.
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llvm-svn: 104078
2010-05-18 22:37:37 +00:00
06ab08f795
Print an error message in Formula::print if the HasBaseReg flag
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is inconsistent with the BaseRegs field. It's not print's job to
assert on an invalid condition, but it can make one more obvious.
llvm-svn: 104077
2010-05-18 22:35:55 +00:00
248c41d108
Rename RegUseTracker's RegUses member to RegUsesMap to avoid
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confusion with LSRInstance's RegUses member.
llvm-svn: 104076
2010-05-18 22:33:00 +00:00
a10f12829f
Add function 'clang_isTagDeclDefinition()' to allow clients of libclang to distinguish between
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forward declarations and definitions of structs/classes/enums.
llvm-svn: 104075
2010-05-18 22:32:15 +00:00
430b6e40ab
Remember to update VirtRegLastUse when spilling without killing before a call.
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llvm-svn: 104074
2010-05-18 22:20:09 +00:00
62713dac19
Add set_new_handler and nothrow implementations
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llvm-svn: 104073
2010-05-18 22:17:13 +00:00
f8bf663873
Teach mode load folding and unfolding code about CMP32ri8 and friends.
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llvm-svn: 104068
2010-05-18 21:54:15 +00:00
4ed63f8687
Don't eliminate frame pointers from leaf functions if "--disable-fp-elim" is
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specified.
llvm-svn: 104066
2010-05-18 21:47:08 +00:00
887dd1cd31
When converting a test to a cmp to fold a load, use the cmp that has an
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8-bit immediate field rather than one with a wider immediate field.
llvm-svn: 104064
2010-05-18 21:42:03 +00:00
7f173d1d27
Quick test to make sure we're emitting the tbss section correctly.
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llvm-svn: 104063
2010-05-18 21:40:20 +00:00
9f46539e07
make mcinstlower remove all but the first operand to CALL64pcrel32.
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The register use operands (e.g. the first argument is passed in a
register) is currently being modeled as a normal register use,
instead of correctly being an implicit use. This causes the operand
to get propagated onto the mcinst, which was causing the encoder to
emit a rex prefix byte, which generates an invalid call.
This fixes rdar://7998435
llvm-svn: 104062
2010-05-18 21:40:18 +00:00
f19384d54a
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
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llvm-svn: 104060
2010-05-18 21:31:17 +00:00
feedc90c57
Implement EmitTBSSSymbol for MachOStreamer.
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Fixes build failure as well.
llvm-svn: 104059
2010-05-18 21:26:41 +00:00
b125532b64
Fix enum to address array bounds regression.
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llvm-svn: 104058
2010-05-18 21:22:12 +00:00
5c87be766d
Make EmitTBSSSymbol take a section argument so that we can find it later.
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Fix up callers and users.
llvm-svn: 104057
2010-05-18 21:16:04 +00:00
663543b4d7
Properly handle multiple definitions of a virtual register in the same
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instruction.
This can happen on ARM:
>> %reg1035:5<def>, %reg1035:6<def> = VLD1q16 %reg1028, 0, pred:14, pred:%reg0
Regs: Q0=%reg1032* R0=%reg1028* R1=%reg1029* R2 R3=%reg1031*
Killing last use: %reg1028
Allocating %reg1035 from QPR
Assigning %reg1035 to Q1
<< %D2<def>, %D3<def> = VLD1q16 %R0<kill>, 0, pred:14, pred:%reg0, %Q1<imp-def>
llvm-svn: 104056
2010-05-18 21:10:50 +00:00
49be9e0819
Teach CursorVisitor about duplicate ObjCPropertyDecls that can arise because of a current
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design limitation in how we handle Objective-C class extensions. This was causing the CursorVisitor
to essentially visit an @property twice (once in the @interface, the other in the class extension).
Fixes <rdar://problem/7410145>.
llvm-svn: 104055
2010-05-18 21:09:07 +00:00
6338d15939
Test passed on ppc, to my surprise; if it worked
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there it may work everywhere...
llvm-svn: 104053
2010-05-18 20:47:04 +00:00
ecbb921cbf
[rand.dist.norm.t]
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llvm-svn: 104052
2010-05-18 20:08:04 +00:00
45b3f702ab
Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices.
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llvm-svn: 104051
2010-05-18 20:07:47 +00:00
e7fc64a5c9
Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.
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llvm-svn: 104050
2010-05-18 20:03:28 +00:00
fb7df5317a
Testcase for llvm-gcc checkin 104042.
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llvm-svn: 104043
2010-05-18 19:03:51 +00:00
87b915a9bc
These test now run in objective-c++ mode we well.
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llvm-svn: 104041
2010-05-18 18:24:06 +00:00
7bcc9e9450
Incorporate Daniel's suggestion and use !isdigit(CurPtr[0]) and not
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CurPtr[0] == '\n' when testing the character after a "0b" when looking
to see if it part of a something like "jmp 0b".
llvm-svn: 104039
2010-05-18 18:09:20 +00:00
53e0631516
Fixed the problem with a branch to "0b" that was not parsed by llvm-mc
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correctly. The Lexer was incorrectly eating the newline casusing it to branch
to address 0. Updated the test case to use a "0:" label and a branch to "0b".
llvm-svn: 104038
2010-05-18 17:51:35 +00:00
Evan Cheng