3b34190100
AVX/AVX2: Move the SEXT lowering code from a target specific DAGco to a lowering function.
...
llvm-svn: 171170
2012-12-27 22:47:16 +00:00
e2eec3c52b
Merge basic_sse12_fp_binop_p and basic_sse12_fp_binop_p_y multiclasses.
...
llvm-svn: 171166
2012-12-27 18:51:50 +00:00
e40e60eed5
Make this parameter be named consistently with most other
...
getAnalysisUsage implementations.
llvm-svn: 171157
2012-12-27 11:17:15 +00:00
29dd7f2090
[ASan] Fix lifetime intrinsics handling. Now for each intrinsic we check if it describes one of 'interesting' allocas. Assume that allocas can go through casts and phi-nodes before apperaring as llvm.lifetime arguments
...
llvm-svn: 171153
2012-12-27 08:50:58 +00:00
2a054b4475
On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
...
register. In most cases we actually compare or select YMM-sized registers
and mixing the two types creates horrible code. This commit optimizes
some of the transition sequences.
PR14657.
llvm-svn: 171148
2012-12-27 08:15:45 +00:00
8e5d80eba3
AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom lowering hook.
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The vector truncs were scalarized during LegalizeVectorOps, later vectorized again by some DAGCombine optimization
and finally, lowered by a dagcombing optimization. Now, they are properly lowered during LegalizeVectorOps.
No new testcase because the original testcases still work.
llvm-svn: 171146
2012-12-27 07:45:10 +00:00
757f3fc394
Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT.
...
llvm-svn: 171143
2012-12-27 07:16:08 +00:00
b1dd52450e
Refactor DAGCombinerInfo. Change the different booleans that indicate if we are before or after different runs of DAGCo, with the CombineLevel enum.
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Also, added a new API for checking if we are running before or after the LegalizeVectorOps phase.
llvm-svn: 171142
2012-12-27 06:47:41 +00:00
09ce4b9efe
Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again.
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llvm-svn: 171141
2012-12-27 06:34:54 +00:00
8f0b73942e
Update tablegen parser to allow defm names to start with #NAME.
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llvm-svn: 171140
2012-12-27 06:32:52 +00:00
396cb795bc
Add hasSideEffects=0 to some shift and rotate instructions. None of which are currently used by code generation.
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llvm-svn: 171137
2012-12-27 03:35:44 +00:00
c7910828e4
Mark the divide instructions as hasSideEffects=0.
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llvm-svn: 171136
2012-12-27 03:01:18 +00:00
3bf29fda91
For the dwarf5 split debug info code split out the string section
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per compile unit/skeleton compile unit. Update tests accordingly.
llvm-svn: 171133
2012-12-27 02:14:01 +00:00
5b807aaa38
Add hasSideEffects=0 to CMP*rr_REV.
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llvm-svn: 171130
2012-12-27 02:08:46 +00:00
89e8607755
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them.
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llvm-svn: 171128
2012-12-27 02:01:33 +00:00
5a6acfa4c8
Right now all of the relocations are 32-bit dwarf, and the relocation
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information doesn't return an addend for Rel relocations. Go ahead
and use this information to fix relocation handling inside dwarfdump
for 32-bit ELF REL.
llvm-svn: 171126
2012-12-27 01:07:07 +00:00
5350cd314b
If all of the write objects are identified then we can vectorize the loop even if the read objects are unidentified.
...
PR14719.
llvm-svn: 171124
2012-12-26 23:30:53 +00:00
c557343956
Fix operands and encoding form for ARPL instruction. Register form had and reversed. Memory form writes memory, but was marked as MRMSrcMem.
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llvm-svn: 171123
2012-12-26 23:27:57 +00:00
d47a70de9f
Add hasSideEffects=0 to some atomic instructions.
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llvm-svn: 171122
2012-12-26 23:08:12 +00:00
af2372087b
Mark the AL/AX/EAX forms of the basic arithmetic operations has never having side effects.
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llvm-svn: 171121
2012-12-26 22:19:23 +00:00
fca2acb618
80 columns. No functionality change.
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llvm-svn: 171120
2012-12-26 22:00:49 +00:00
90053a1214
Remove mid-optimizer warning. This situation should be handled differently,
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such as by a compiler warning, a check in clang -fsanitizer=undefined, being
optimized to unreachable, or a combination of the above. PR14722.
llvm-svn: 171119
2012-12-26 22:00:35 +00:00
1b8c0750ee
Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier.
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llvm-svn: 171118
2012-12-26 21:30:22 +00:00
18f2675e9b
Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns.
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llvm-svn: 171117
2012-12-26 21:04:30 +00:00
3f7c4f36ba
LoopVectorizer: Optimize the vectorization of consecutive memory access when the iteration step is -1
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llvm-svn: 171114
2012-12-26 19:08:17 +00:00
5eb5bf8b46
[msan] Raise alignment of origin stores/loads when possible.
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Origin alignment is as high as the alignment of the corresponding application
location, but never less than 4.
llvm-svn: 171110
2012-12-26 11:55:09 +00:00
d8be0c510c
[msan] Expand the file comment with track-origins info.
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llvm-svn: 171109
2012-12-26 10:59:00 +00:00
24f316e4db
Merge still more SSE/AVX instruction definitions.
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llvm-svn: 171103
2012-12-26 07:54:43 +00:00
af629e2700
Merge more SSE/AVX instruction definitions.
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llvm-svn: 171102
2012-12-26 07:20:35 +00:00
65fe30450d
Fix 80 column violation.
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llvm-svn: 171097
2012-12-26 06:15:53 +00:00
f4d0fe8fcd
Fix class name in comment.
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llvm-svn: 171096
2012-12-26 06:15:09 +00:00
59747c4dbd
Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions.
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llvm-svn: 171095
2012-12-26 06:14:15 +00:00
8a48677586
Remove 'v' from mnemonic to fix asm matching failures.
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llvm-svn: 171093
2012-12-26 06:02:15 +00:00
b4ef0fa3a1
Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions.
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llvm-svn: 171092
2012-12-26 05:49:15 +00:00
5267bb71b8
Reformat the docs.
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llvm-svn: 171091
2012-12-26 04:59:20 +00:00
a2594dd5f0
Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN
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llvm-svn: 171087
2012-12-26 04:36:03 +00:00
97730a0d6a
Merge an AVX/SSE 256-bit and 128-bit multiclass.
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llvm-svn: 171086
2012-12-26 03:56:47 +00:00
8b59746390
Mark VANDNPD/VANDNPDS as not commutable.
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llvm-svn: 171085
2012-12-26 03:48:10 +00:00
81d1e596bb
Remove alignment from a bunch more VEX encoded operations in the folding tables.
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llvm-svn: 171082
2012-12-26 02:44:47 +00:00
b2922164f0
Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment...
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llvm-svn: 171081
2012-12-26 02:14:19 +00:00
d09a9af9b6
Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX.
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llvm-svn: 171080
2012-12-26 01:47:12 +00:00
30e95a8ebb
BBVectorize: Use VTTI to compute costs for intrinsics vectorization
...
For the time being this includes only some dummy test cases. Once the
generic implementation of the intrinsics cost function does something other
than assuming scalarization in all cases, or some target specializes the
interface, some real test cases can be added.
Also, for consistency, I changed the type of IID from unsigned to Intrinsic::ID
in a few other places.
llvm-svn: 171079
2012-12-26 01:36:57 +00:00
caef1c5d86
Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment.
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llvm-svn: 171078
2012-12-26 00:35:47 +00:00
b44f890133
LoopVectorize: Enable vectorization of the fmuladd intrinsic
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llvm-svn: 171076
2012-12-25 23:21:29 +00:00
2a456112ec
BBVectorize: Enable vectorization of the fmuladd intrinsic
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llvm-svn: 171075
2012-12-25 22:36:08 +00:00
1b5ff08d43
Expand PPC64 atomic load and store
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Use of store or load with the atomic specifier on 64-bit types would
cause instruction-selection failures. As with the 32-bit case, these
can use the default expansion in terms of cmp-and-swap.
llvm-svn: 171072
2012-12-25 17:22:53 +00:00
f19c086d1e
[msan] Fix handling of vectors of pointers.
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VectorType::getInteger() can not be used with them, because pointer size
depends on the target.
llvm-svn: 171070
2012-12-25 16:04:38 +00:00
ec8371283b
[msan] Fix handling of select with vector condition.
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llvm-svn: 171069
2012-12-25 14:56:21 +00:00
81b5a8fd2e
X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use of and commutativity.
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llvm-svn: 171064
2012-12-25 13:09:08 +00:00
df4af41b9b
X86: Custom lower <2 x i64> eq and ne when SSE41 is not available.
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pcmpeqd, pshufd, pshufd, pand is cheaper than unpack + cmpq, sbbq, cmpq, sbbq + pack.
Small speedup on loop-vectorized viterbi (-march=core2).
llvm-svn: 171063
2012-12-25 12:54:19 +00:00
788381b8ac
ASan: initialize callbacks from ASan module pass in a separate function for consistency
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llvm-svn: 171061
2012-12-25 12:28:20 +00:00
1e3f7ba8f7
ASan: move stack poisoning logic into FunctionStackPoisoner struct
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llvm-svn: 171060
2012-12-25 12:04:36 +00:00
d192517cf3
Fix whitespace. No functionality change.
...
llvm-svn: 171051
2012-12-25 06:13:25 +00:00
00410ae625
VCVTSS2SD requires a strict alignment. Thanks Elena.
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llvm-svn: 171049
2012-12-25 03:29:18 +00:00
fe73ac34c5
Rename LLVMContext diagnostic handler types and functions.
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These are now generally used for all diagnostics from the backend, not just
for inline assembly, so this drops the "InlineAsm" from the names. No
functional change. (I've left aliases for the old names but only for long
enough to let me switch over clang to use the new ones.)
llvm-svn: 171047
2012-12-25 00:07:12 +00:00
521e0d59f3
Quiet gcc's -Wparenthesis warning. No functionality change.
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llvm-svn: 171044
2012-12-24 19:58:45 +00:00
9d46110ff1
Use a std::string rather than a dynamically allocated char* buffer.
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This affords us to use std::string's allocation routines and use the destructor
for the memory management. Switching to that also means that we can use
operator==(const std::string&, const char *) to perform the string comparison
rather than resorting to libc functionality (i.e. strcmp).
Patch by Saleem Abdulrasool!
Differential Revision: http://llvm-reviews.chandlerc.com/D230
llvm-svn: 171042
2012-12-24 19:23:30 +00:00
4ed23578da
Add LLVMContext::emitWarning methods and use them. <rdar://problem/12867368>
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When the backend is used from clang, it should produce proper diagnostics
instead of just printing messages to errs(). Other clients may also want to
register their own error handlers with the LLVMContext, and the same handler
should work for warnings in the same way as the existing emitError methods.
llvm-svn: 171041
2012-12-24 18:15:21 +00:00
3ee6b10dd4
CostModel: We have API for checking the costs of known shuffles. This patch adds
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support for the insert-subvector and extract-subvector kinds.
llvm-svn: 171027
2012-12-24 10:04:03 +00:00
517afbff01
Added 6 more value types: v32i1, v64i1, v32i16, v32i8, v64i8, v8f64
...
llvm-svn: 171026
2012-12-24 10:03:57 +00:00
2fdeb6da8d
Removed "static" from "__jit_debug_descriptor" because "static" adds C++ mangling prefix to this symbol.
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llvm-svn: 171025
2012-12-24 09:42:27 +00:00
dc0ad92b64
Some x86 instructions can load/store one of the operands to memory. On SSE, this memory needs to be aligned.
...
When these instructions are encoded in VEX (on AVX) there is no such requirement. This changes the folding
tables and removes the alignment restrictions from VEX-encoded instructions.
llvm-svn: 171024
2012-12-24 09:40:33 +00:00
5f7c12cfbd
LoopVectorizer: When checking for vectorizable types, also check
...
the StoreInst operands.
PR14705.
llvm-svn: 171023
2012-12-24 09:14:18 +00:00
7e1599e100
Change the codegen Cost Model API for shuffeles. This patch removes the API for broadcast and adds a more general API that accepts an enum of known shuffles.
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llvm-svn: 171022
2012-12-24 08:57:47 +00:00
098842b401
Fix typo in comments
...
llvm-svn: 171021
2012-12-24 08:52:53 +00:00
99868e4f9d
Update the docs of the cost model.
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llvm-svn: 171016
2012-12-24 05:51:12 +00:00
bd5d1d832a
LoopVectorizer: Fix an endless loop in the code that looks for reductions.
...
The bug was in the code that detects PHIs in if-then-else block sequence.
PR14701.
llvm-svn: 171008
2012-12-24 01:22:06 +00:00
cf9999d9d5
CostModel: Change the default target-independent implementation for finding
...
the cost of arithmetic functions. We now assume that the cost of arithmetic
operations that are marked as Legal or Promote is low, but ops that are
marked as custom are higher.
llvm-svn: 171002
2012-12-23 17:31:23 +00:00
28691400dd
LoopVectorize: Fix accidentaly inverted condition.
...
llvm-svn: 171001
2012-12-23 13:21:41 +00:00
855ba03408
LoopVectorize: For scalars and void types there is no need to compute vector insert/extract costs.
...
Fixes an assert during the build of oggenc in the test suite.
llvm-svn: 171000
2012-12-23 13:19:18 +00:00
b15c69a725
whitespace
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llvm-svn: 170997
2012-12-23 07:33:44 +00:00
1bef5a0509
Rename a function.
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llvm-svn: 170996
2012-12-23 07:30:09 +00:00
2cade68025
Loop Vectorizer: Update the cost model of scatter/gather operations and make
...
them more expensive.
llvm-svn: 170995
2012-12-23 07:23:55 +00:00
1bef2c859f
Remove trailing whitespace.
...
llvm-svn: 170991
2012-12-22 19:15:35 +00:00
4c94775198
Remove trailing whitespace
...
llvm-svn: 170990
2012-12-22 18:09:02 +00:00
7bca670a8b
Remove a special case that doesn't seem necessary any longer.
...
Back when this exception was added, it was skipping a lot more code, but
now it just looks like a premature optimization.
llvm-svn: 170989
2012-12-22 17:33:22 +00:00
b089483993
Use getNumOperands() instead of Operands.size().
...
The representation of the Operands array is going to change soon so it
can be allocated from a BumpPtrAllocator.
llvm-svn: 170988
2012-12-22 17:13:06 +00:00
76268ac682
X86: Turn mul of <4 x i32> into pmuludq when no SSE4.1 is available.
...
pmuludq is slow, but it turns out that all the unpacking and packing of the
scalarized mul is even slower. 10% speedup on loop-vectorized paq8p.
llvm-svn: 170985
2012-12-22 16:07:56 +00:00
b2f0a2bd4b
X86: Emit vector sext as shuffle + sra if vpmovsx is not available.
...
Also loosen the SSSE3 dependency a bit, expanded pshufb + psra is still better
than scalarized loads. Fixes PR14590.
llvm-svn: 170984
2012-12-22 11:34:28 +00:00
c79e42c5ce
Change 'AttrVal' to 'AttrKind' to better reflect that it's a kind of attribute instead of the value of the attribute.
...
llvm-svn: 170972
2012-12-22 00:37:52 +00:00
045e4f1365
Don't call back() on an empty SmallVector. Found by -fsanitize=enum!
...
llvm-svn: 170968
2012-12-22 00:15:13 +00:00
d5aae980cb
In some cases, due to scheduling constraints we copy the EFLAGS.
...
The only way to read the eflags is using push and pop. If we don't
adjust the stack then we run over the first frame index. This is
not something that we want to do, so we have to make sure that
our machine function does not copy the flags. If it does then
we have to emit the prolog that adjusts the stack.
rdar://12896831
llvm-svn: 170961
2012-12-21 23:48:49 +00:00
6ac2fc4976
[mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware
...
instructions.
llvm-svn: 170956
2012-12-21 23:21:32 +00:00
beea8a34c3
[mips] Refactor SYNC and multiply/divide instructions.
...
llvm-svn: 170955
2012-12-21 23:17:36 +00:00
31ddec5887
[mips] Refactor BAL instructions.
...
llvm-svn: 170954
2012-12-21 23:15:59 +00:00
d6b694f036
[mips] Fix encoding of BAL instruction. Also, fix assembler test case which
...
was not catching the error.
llvm-svn: 170953
2012-12-21 23:13:59 +00:00
a158042a56
[mips] Refactor jump, jump register, jump-and-link and nop instructions.
...
llvm-svn: 170952
2012-12-21 23:03:50 +00:00
e1826d7464
[mips] Refactor load/store left/right and load-link and store-conditional
...
instructions.
llvm-svn: 170950
2012-12-21 23:01:24 +00:00
d9bf8424e5
[mips] Refactor load/store instructions.
...
llvm-svn: 170948
2012-12-21 22:58:55 +00:00
b59b047fbe
[mips] Remove unnecessary isPseudo parameter.
...
llvm-svn: 170947
2012-12-21 22:57:26 +00:00
e738efc95b
[mips] Refactor LUI instruction.
...
llvm-svn: 170944
2012-12-21 22:46:07 +00:00
895e1cb2aa
[mips] Refactor count leading zero or one instructions.
...
llvm-svn: 170942
2012-12-21 22:43:58 +00:00
4f4c4aa05e
[mips] Refactor sign-extension-in-register instructions.
...
llvm-svn: 170940
2012-12-21 22:41:52 +00:00
b14c6e4e5f
[mips] Refactor instructions which copy from and to HI/LO registers.
...
llvm-svn: 170939
2012-12-21 22:39:17 +00:00
9e89195dce
[mips] Refactor logical NOR instructions.
...
llvm-svn: 170937
2012-12-21 22:35:47 +00:00
ac10697207
[mips] Move instruction definitions in MipsInstrInfo.td.
...
llvm-svn: 170936
2012-12-21 22:33:43 +00:00
09ef8425e9
R600: Coding style - remove empty spaces from the beginning of functions
...
No functionality change.
llvm-svn: 170923
2012-12-21 20:12:02 +00:00
41398026e7
R600: Fix MAX_UINT definition
...
Patch by: Vadim Girlin
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 170922
2012-12-21 20:12:01 +00:00
4fa7ac29f1
R600: Add SHADOWCUBE to TEX_SHADOW pattern
...
Patch by: Vadim Girlin
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 170921
2012-12-21 20:11:59 +00:00
5521b94b07
Cleanup compiler warnings on discarding type qualifiers in casts. Switch to C++ style casts.
...
Patch by Saleem Abdulrasool!
Differential Revision: http://llvm-reviews.chandlerc.com/D204
llvm-svn: 170917
2012-12-21 19:09:53 +00:00
Nadav Rotem