a7b2bd5997
Add and sort "sections" in debug lines. This always stepping through
...
code in sections other than ".text", including weak sections like ctors and
dtors.
llvm-svn: 28909
2006-06-23 12:51:53 +00:00
0a9e837b6f
Add support for function types.
...
llvm-svn: 28874
2006-06-20 19:41:06 +00:00
2837e3204f
References need to be section relative.
...
llvm-svn: 28861
2006-06-19 19:49:42 +00:00
f32058a2b7
References need to be section relative.
...
llvm-svn: 28858
2006-06-19 15:48:00 +00:00
90cd68acc6
Handle versioning of compile unit.
...
llvm-svn: 28855
2006-06-19 12:54:15 +00:00
b2ff2d481e
1. Revise vector debug support.
...
2. Update docs for vector debug support and new version control.
3. Simplify serialization of DebugDescInfo subclasses.
llvm-svn: 28816
2006-06-16 13:14:03 +00:00
4ff6c1646f
Teach the local allocator to know that live-in values (e.g. arguments) are
...
live at function entry. This prevents it from using arg registers for other
purposes before the arguments are used.
llvm-svn: 28809
2006-06-15 22:21:53 +00:00
19f964e048
1. Support standard dwarf format (was bootstrapping in Apple format.)
...
2. Add vector support.
llvm-svn: 28807
2006-06-15 20:51:43 +00:00
3519b87758
Was pointed out that structure alignment and type alignment are not the same
...
thing. Doubles still need to be special cased.
llvm-svn: 28806
2006-06-15 19:37:14 +00:00
dce07568f2
Alignment of globals has not been quite right. Needed to drop the pointer type
...
to get the alignment of the element type.
llvm-svn: 28799
2006-06-15 13:10:58 +00:00
ef9e07d3f0
Consistency. EXTRACT_ELEMENT index operand should have ptr type.
...
llvm-svn: 28795
2006-06-15 08:11:54 +00:00
df63179d95
Assert. Rather than silently stop printing.
...
llvm-svn: 28794
2006-06-15 08:10:56 +00:00
55772ccfd6
Instructions with variable operands (variable_ops) can have a number required
...
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.
Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.
llvm-svn: 28791
2006-06-15 07:22:16 +00:00
f0a7a1a117
Change versioning to per debug info descriptor (merged with tag.)
...
llvm-svn: 28782
2006-06-14 14:45:39 +00:00
f67bec0579
Place dwarf headers at earliest possible point. Well behaved when skipping
...
functions.
llvm-svn: 28781
2006-06-14 11:35:03 +00:00
32d92e004d
Make sure to update the CFG correctly if a switch only has a default dest.
...
This fixes CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll
llvm-svn: 28755
2006-06-12 18:25:29 +00:00
0e57b2cb92
Start on my todo list
...
llvm-svn: 28752
2006-06-12 16:07:18 +00:00
c03a9259c0
Fix X86/inline-asm.ll:test2, a case where an input value was implicitly
...
truncated.
llvm-svn: 28733
2006-06-08 18:27:11 +00:00
705948d742
Fix Regression/CodeGen/X86/inline-asm.ll, a case where inline asm causes
...
implement extension of a register.
llvm-svn: 28731
2006-06-08 18:22:48 +00:00
8f8b5e4631
Fix an assert-on-inline-inline-asm bug.
...
llvm-svn: 28727
2006-06-08 18:00:47 +00:00
614cb2ff82
For PR798:
...
Provide GraphViz support for MingW32. Patch provided by Anton Korobeynikov
llvm-svn: 28688
2006-06-05 16:26:06 +00:00
7c77323e1d
For PR798:
...
Add support for Graphviz. Patch contributed by Anton Korobeynikov.
llvm-svn: 28684
2006-06-05 15:44:46 +00:00
cd8f67a106
Prevent the -pedantic option from causing Mac OS/X build problems:
...
LiveIntervalAnalysis.cpp:218: error: floating constant exceeds range of 'double'
llvm-svn: 28620
2006-06-01 06:12:21 +00:00
a647c7ff42
Use archive libraries instead of object files for VMCore, BCReader,
...
BCWriter, and bzip2 libraries. Adjust the various makefiles to accommodate
these changes. This was done to speed up link times.
llvm-svn: 28610
2006-06-01 01:30:27 +00:00
0c0996a97b
commuteInstruction() does not always create a new MI!
...
llvm-svn: 28592
2006-05-31 18:03:39 +00:00
9d91caa053
Eliminate a memory leak.
...
llvm-svn: 28585
2006-05-31 07:13:03 +00:00
64d2846017
visitVBinOp: Can't fold divide by zero!
...
llvm-svn: 28584
2006-05-31 06:08:35 +00:00
d12c97d23a
Make sure the register pressure reduction schedulers work for non-uniform
...
latency targets, e.g. PPC32.
llvm-svn: 28561
2006-05-30 18:05:39 +00:00
61e9f0d680
When a priority_queue is empty, the behavior of top() operator is
...
non-deterministic. Returns NULL when it's empty!
llvm-svn: 28560
2006-05-30 18:04:34 +00:00
8f872d2091
Fix a nasty dag combiner bug that caused nondeterminstic crashes (MY FAVORITE!):
...
SimplifySelectOps would eliminate a Select, delete it, then return true.
The clients would see that it did something and return null.
The top level would see a null return, and decide that nothing happened,
proceeding to process the node in other ways: boom.
The fix is simple: clients of SimplifySelectOps should return the select
node itself.
In order to catch really obnoxious boogs like this in the future, add an
assert that nodes are not deleted. We do this by checking for a sentry node
type that the SDNode dtor sets when a node is destroyed.
llvm-svn: 28514
2006-05-27 00:43:02 +00:00
21dee4e0b2
Make CALL node consistent with RET node. Signness of value has type MVT::i32
...
instead of MVT::i1. Either is fine except MVT::i32 is probably a legal type
for most (if not all) platforms while MVT::i1 is not.
llvm-svn: 28511
2006-05-26 23:13:20 +00:00
a2e9953c54
Change RET node to include signness information of the return values. e.g.
...
RET chain, value1, sign1, value2, sign2
llvm-svn: 28509
2006-05-26 23:09:09 +00:00
0f5c7936e7
Remove a bogus cast.
...
llvm-svn: 28492
2006-05-26 08:00:14 +00:00
009f5f55f7
Turn on -sched-commute-nodes by default.
...
llvm-svn: 28465
2006-05-25 08:37:31 +00:00
4582771f3f
CALL node change: now including signness of every argument.
...
llvm-svn: 28461
2006-05-25 00:55:32 +00:00
aa2372562e
Patches to make the LLVM sources more -pedantic clean. Patch provided
...
by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
ac4f66ff24
-enable-unsafe-fp-math implies -enable-finite-only-fp-math
...
llvm-svn: 28437
2006-05-23 18:18:46 +00:00
df1d439849
Fix missing include
...
llvm-svn: 28435
2006-05-23 13:43:15 +00:00
1c5b7d12df
Incorrect SETCC CondCode used for FP comparisons.
...
llvm-svn: 28433
2006-05-23 06:40:47 +00:00
d8e2f6ebc1
lib/Target/Target.td
...
llvm-svn: 28386
2006-05-18 20:42:07 +00:00
7949c2e8b2
Fix the result of the call to use a correct vbitconvert. There is no need to
...
use getPackedTypeBreakdown at all here.
llvm-svn: 28365
2006-05-17 20:49:36 +00:00
938155ca57
Correct a previous patch which broke CodeGen/PowerPC/vec_call.ll
...
llvm-svn: 28364
2006-05-17 20:43:21 +00:00
751cd7653d
Fixed a LowerCallTo and LowerArguments bug. They were introducing illegal
...
VBIT_VECTOR nodes. There were some confusion about the semantics of
getPackedTypeBreakdown(). e.g. for <4 x f32> it returns 1 and v4f32, not 4,
and f32.
llvm-svn: 28352
2006-05-17 18:16:39 +00:00
62f1b83c0e
When we legalize target nodes, do not use getNode to create a new node,
...
use UpdateNodeOperands to just update the operands! This is important because
getNode will allocate a new node if the node returns a flag and this breaks
assumptions in the legalizer that you can legalize some things multiple times
and get exactly the same results.
This latent bug was exposed by my ppc patch last night, and this fixes
gsm/toast.
llvm-svn: 28348
2006-05-17 18:00:08 +00:00
a1cec0106a
Add an assertion, avoid some unneeded work for each call. No functionality
...
change.
llvm-svn: 28347
2006-05-17 17:55:45 +00:00
b77ba73a29
Add support for calls that pass and return legal vectors.
...
llvm-svn: 28340
2006-05-16 23:39:44 +00:00
aaa23d953f
Add a new ISD::CALL node, make the default impl of TargetLowering::LowerCallTo
...
produce it.
llvm-svn: 28338
2006-05-16 22:53:20 +00:00
1dc9ec5874
Move this code to a common place
...
llvm-svn: 28329
2006-05-16 17:42:15 +00:00
3d82699605
Add a chain to FORMAL_ARGUMENTS. This is a minimal port of the X86 backend,
...
it doesn't currently use/maintain the chain properly. Also, make the
X86ISelLowering.cpp file 80-col clean.
llvm-svn: 28320
2006-05-16 06:45:34 +00:00
957cb6733a
Move function-live-in-handling code from the sdisel code to the scheduler.
...
This code should be emitted after legalize, so it can't be in sdisel.
Note that the EmitFunctionEntryCode hook should be updated to operate on the
DAG. The X86 backend is the only one currently using this hook.
llvm-svn: 28315
2006-05-16 06:10:58 +00:00
52d0c78de8
Print the vreg that livein physregs are live in
...
llvm-svn: 28314
2006-05-16 05:55:30 +00:00
5f0edfb849
Legalize FORMAL_ARGUMENTS nodes correctly, we don't want to legalize them once
...
for each argument.
llvm-svn: 28313
2006-05-16 05:49:56 +00:00
99f2f79e2f
Fixing 2006-05-01-SchedCausingSpills.ll; some clean up
...
llvm-svn: 28279
2006-05-13 08:22:24 +00:00
d1915cfa6f
Revert an un-intended change
...
llvm-svn: 28278
2006-05-13 05:53:47 +00:00
69a0ce6261
Merge identical code.
...
llvm-svn: 28274
2006-05-13 02:11:14 +00:00
a726fc6dbf
If the register allocator cannot find a register to spill, try the aliases. If
...
that still fails (because all the register spill weights are inf), just grab
one.
llvm-svn: 28262
2006-05-12 19:07:46 +00:00
53cdb2f2b0
Remove dead vars
...
llvm-svn: 28255
2006-05-12 18:06:45 +00:00
da076e41ab
remove dead vars
...
llvm-svn: 28254
2006-05-12 18:04:28 +00:00
fe211deedf
Remove dead variable
...
llvm-svn: 28253
2006-05-12 18:02:04 +00:00
afe72481f6
Comment out dead variables
...
llvm-svn: 28252
2006-05-12 17:57:54 +00:00
936cd3390d
Remove dead var
...
llvm-svn: 28250
2006-05-12 17:50:35 +00:00
8c02c3f41a
Compile:
...
%tmp152 = setgt uint %tmp144, %tmp149 ; <bool> [#uses=1]
%tmp159 = setlt uint %tmp144, %tmp149 ; <bool> [#uses=1]
%bothcond2 = or bool %tmp152, %tmp159 ; <bool> [#uses=1]
To setne, not setune, which causes an assertion fault.
llvm-svn: 28244
2006-05-12 17:03:46 +00:00
8c2c1e90c4
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
...
TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
llvm-svn: 28238
2006-05-12 06:33:49 +00:00
6a6886185b
Backing out fix for PR770. Need to re-apply it after live range splitting is possible
...
llvm-svn: 28236
2006-05-12 06:06:34 +00:00
095c9d9b7f
Duh. That could take a long time.
...
llvm-svn: 28235
2006-05-12 06:05:18 +00:00
66adee93aa
Two simplifications for token factor nodes: simplify tf(x,x) -> x.
...
simplify tf(x,y,y,z) -> tf(x,y,z).
llvm-svn: 28233
2006-05-12 05:01:37 +00:00
afed73eebe
Add capability to scheduler to commute nodes for profit.
...
If a two-address code whose first operand has uses below, it should be commuted
when possible.
llvm-svn: 28230
2006-05-12 01:58:24 +00:00
d38c22bdd3
Refactor scheduler code. Move register-reduction list scheduler to a
...
separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.
llvm-svn: 28226
2006-05-11 23:55:42 +00:00
47926aff96
Set weight of zero length intervals to infinite to prevent them from being
...
spilled.
llvm-svn: 28220
2006-05-11 07:29:24 +00:00
db6aa4896b
Backing out previous check-in.
...
llvm-svn: 28219
2006-05-11 07:28:16 +00:00
6ad040a6bc
If the live interval legnth is essentially zero, i.e. in every live range
...
the use follows def immediately, it doesn't make sense to spill it and
hope it will be easier to allocate for this LI.
llvm-svn: 28217
2006-05-10 22:30:41 +00:00
9665ba053f
Templatify RegReductionPriorityQueue
...
llvm-svn: 28212
2006-05-10 06:16:44 +00:00
1a225d23ae
Fix PR773
...
llvm-svn: 28207
2006-05-09 18:20:51 +00:00
f801792e08
Fix a regression in my patch from last night that broke the llvmgcc4 build on
...
ppc
llvm-svn: 28205
2006-05-09 16:41:59 +00:00
7d693898ee
Add pseudo dependency to force a def&use operand to be scheduled last (unless
...
the distance between the def and another use is much longer). This is under
option control for now "-sched-lower-defnuse".
llvm-svn: 28201
2006-05-09 07:13:34 +00:00
2c74848af1
Debugging info
...
llvm-svn: 28200
2006-05-09 06:55:15 +00:00
ae45020720
PR 770 - permit coallescing of registers in subset register classes.
...
llvm-svn: 28197
2006-05-09 06:37:48 +00:00
4ebc6a2311
Implement MASM sections correctly, without a "has masm sections flag" and a bunch of special case code.
...
llvm-svn: 28194
2006-05-09 05:33:48 +00:00
8c2bfc0659
Oh yeah, there are two of these now, unify both.
...
llvm-svn: 28192
2006-05-09 05:24:50 +00:00
6341df8069
Setting SwitchToSectionDirective properly in the MASM backend permits a bunch
...
of code to be unified.
llvm-svn: 28191
2006-05-09 05:23:12 +00:00
d36cc2b610
Don't prefix section directives with a tab. Doing so causes blank lines to
...
be emitted to the .s file.
llvm-svn: 28189
2006-05-09 05:19:59 +00:00
e64f764d25
Make the masm codepath work like the normal code path.
...
llvm-svn: 28188
2006-05-09 05:15:58 +00:00
c0f0dfa56f
The MASM asmprinter has been fixed, these hacks are no longer needed.
...
llvm-svn: 28186
2006-05-09 05:13:34 +00:00
8488ba2e41
Split SwitchSection into SwitchTo{Text|Data}Section methods.
...
llvm-svn: 28184
2006-05-09 04:59:56 +00:00
446e1ef26a
Make the case I just checked in stronger. Now we compile this:
...
short test2(short X, short x) {
int Y = (short)(X+x);
return Y >> 1;
}
to:
_test2:
add r2, r3, r4
extsh r2, r2
srawi r3, r2, 1
blr
instead of:
_test2:
add r2, r3, r4
extsh r2, r2
srwi r2, r2, 1
extsh r3, r2
blr
llvm-svn: 28175
2006-05-08 21:18:59 +00:00
29062da0ac
Implement and_sext.ll:test3, generating:
...
_test4:
srawi r3, r3, 16
blr
instead of:
_test4:
srwi r2, r3, 16
extsh r3, r2
blr
for:
short test4(unsigned X) {
return (X >> 16);
}
llvm-svn: 28174
2006-05-08 20:59:41 +00:00
2935d8190c
Compile this:
...
short test4(unsigned X) {
return (X >> 16);
}
to:
_test4:
movl 4(%esp), %eax
sarl $16, %eax
ret
instead of:
_test4:
movl $-65536, %eax
andl 4(%esp), %eax
sarl $16, %eax
ret
llvm-svn: 28171
2006-05-08 20:51:54 +00:00
78da6792e7
Fold shifts with undef operands.
...
llvm-svn: 28167
2006-05-08 17:29:49 +00:00
d7a19102d1
Make emission of jump tables a bit less conservative; they are now required
...
to be only 31.25% dense, rather than 75% dense.
llvm-svn: 28165
2006-05-08 16:51:36 +00:00
e5ce5bb6da
Fix PR772
...
llvm-svn: 28161
2006-05-08 01:35:01 +00:00
7e7bcf3a54
Simplify some code, add a couple minor missed folds
...
llvm-svn: 28152
2006-05-06 23:06:26 +00:00
751817c54f
constant fold sign_extend_inreg
...
llvm-svn: 28151
2006-05-06 23:05:41 +00:00
2a4d7b845b
remove cases handled elsewhere
...
llvm-svn: 28150
2006-05-06 22:43:44 +00:00
ce9b9fe6eb
Fix some loose ends in MASM support.
...
llvm-svn: 28148
2006-05-06 21:27:14 +00:00
1ecb2a2dac
Use the new TargetLowering::ComputeNumSignBits method to eliminate
...
sign_extend_inreg operations. Though ComputeNumSignBits is still rudimentary,
this is enough to compile this:
short test(short X, short x) {
int Y = X+x;
return (Y >> 1);
}
short test2(short X, short x) {
int Y = (short)(X+x);
return Y >> 1;
}
into:
_test:
add r2, r3, r4
srawi r3, r2, 1
blr
_test2:
add r2, r3, r4
extsh r2, r2
srawi r3, r2, 1
blr
instead of:
_test:
add r2, r3, r4
srawi r2, r2, 1
extsh r3, r2
blr
_test2:
add r2, r3, r4
extsh r2, r2
srawi r2, r2, 1
extsh r3, r2
blr
llvm-svn: 28146
2006-05-06 09:30:03 +00:00
21cd99024a
When inserting casts, be careful of where we put them. We cannot insert
...
a cast immediately before a PHI node.
This fixes Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll
llvm-svn: 28143
2006-05-06 09:10:37 +00:00
907e392dba
Fold trunc(any_ext). This gives stuff like:
...
27,28c27
< movzwl %di, %edi
< movl %edi, %ebx
---
> movw %di, %bx
llvm-svn: 28137
2006-05-05 22:56:26 +00:00
57f8c5a387
Shrink shifts when possible.
...
llvm-svn: 28136
2006-05-05 22:53:17 +00:00
a633c31319
Indent multiline asm strings more nicely
...
llvm-svn: 28132
2006-05-05 21:47:05 +00:00
3d26577396
Fold (fpext (load x)) -> (extload x)
...
llvm-svn: 28130
2006-05-05 21:34:35 +00:00
3e3f2c63c3
More aggressively sink GEP offsets into loops. For example, before we
...
generated:
movl 8(%esp), %eax
movl %eax, %edx
addl $4316, %edx
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, (%edx)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %edx
movl %edx, 4460(%eax)
ret
...
Now we generate:
movl 8(%esp), %eax
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, 4316(%eax)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %ecx
movl %ecx, 4460(%eax)
ret
... which uses one fewer register.
llvm-svn: 28129
2006-05-05 21:17:49 +00:00
25a5283a86
Fold some common code.
...
llvm-svn: 28124
2006-05-05 06:32:04 +00:00
002ee91457
Implement:
...
// fold (and (sext x), (sext y)) -> (sext (and x, y))
// fold (or (sext x), (sext y)) -> (sext (or x, y))
// fold (xor (sext x), (sext y)) -> (sext (xor x, y))
// fold (and (aext x), (aext y)) -> (aext (and x, y))
// fold (or (aext x), (aext y)) -> (aext (or x, y))
// fold (xor (aext x), (aext y)) -> (aext (xor x, y))
llvm-svn: 28123
2006-05-05 06:31:05 +00:00
5ac4293606
Pull and through and/or/xor. This compiles some bitfield code to:
...
mov EAX, DWORD PTR [ESP + 4]
mov ECX, DWORD PTR [EAX]
mov EDX, ECX
add EDX, EDX
or EDX, ECX
and EDX, -2147483648
and ECX, 2147483647
or EDX, ECX
mov DWORD PTR [EAX], EDX
ret
instead of:
sub ESP, 4
mov DWORD PTR [ESP], ESI
mov EAX, DWORD PTR [ESP + 8]
mov ECX, DWORD PTR [EAX]
mov EDX, ECX
add EDX, EDX
mov ESI, ECX
and ESI, -2147483648
and EDX, -2147483648
or EDX, ESI
and ECX, 2147483647
or EDX, ECX
mov DWORD PTR [EAX], EDX
mov ESI, DWORD PTR [ESP]
add ESP, 4
ret
llvm-svn: 28122
2006-05-05 06:10:43 +00:00
812646aa0c
Implement a variety of simplifications for ANY_EXTEND.
...
llvm-svn: 28121
2006-05-05 05:58:59 +00:00
8d6fc20181
Factor some code, add these transformations:
...
// fold (and (trunc x), (trunc y)) -> (trunc (and x, y))
// fold (or (trunc x), (trunc y)) -> (trunc (or x, y))
// fold (xor (trunc x), (trunc y)) -> (trunc (xor x, y))
llvm-svn: 28120
2006-05-05 05:51:50 +00:00
78a7f0e05e
Fix VC++ compilation error.
...
llvm-svn: 28117
2006-05-05 01:47:05 +00:00
7a3ecf7993
Sink noop copies into the basic block that uses them. This reduces the number
...
of cross-block live ranges, and allows the bb-at-a-time selector to always
coallesce these away, at isel time.
This reduces the load on the coallescer and register allocator. For example
on a codec on X86, we went from:
1643 asm-printer - Number of machine instrs printed
419 liveintervals - Number of loads/stores folded into instructions
1144 liveintervals - Number of identity moves eliminated after coalescing
1022 liveintervals - Number of interval joins performed
282 liveintervals - Number of intervals after coalescing
1304 liveintervals - Number of original intervals
86 regalloc - Number of times we had to backtrack
1.90232 regalloc - Ratio of intervals processed over total intervals
40 spiller - Number of values reused
182 spiller - Number of loads added
121 spiller - Number of stores added
132 spiller - Number of register spills
6 twoaddressinstruction - Number of instructions commuted to coalesce
360 twoaddressinstruction - Number of two-address instructions
to:
1636 asm-printer - Number of machine instrs printed
403 liveintervals - Number of loads/stores folded into instructions
1155 liveintervals - Number of identity moves eliminated after coalescing
1033 liveintervals - Number of interval joins performed
279 liveintervals - Number of intervals after coalescing
1312 liveintervals - Number of original intervals
76 regalloc - Number of times we had to backtrack
1.88998 regalloc - Ratio of intervals processed over total intervals
1 spiller - Number of copies elided
41 spiller - Number of values reused
191 spiller - Number of loads added
114 spiller - Number of stores added
128 spiller - Number of register spills
4 twoaddressinstruction - Number of instructions commuted to coalesce
356 twoaddressinstruction - Number of two-address instructions
On this testcase, this change provides a modest reduction in spill code,
regalloc iterations, and total instructions emitted. It increases the number
of register coallesces.
llvm-svn: 28115
2006-05-05 01:04:50 +00:00
abdf4d569c
Final pass of minor cleanups for MachineInstr
...
llvm-svn: 28110
2006-05-04 19:36:09 +00:00
9add880566
Initial support for register pressure aware scheduling. The register reduction
...
scheduler can go into a "vertical mode" (i.e. traversing up the two-address
chain, etc.) when the register pressure is low.
This does seem to reduce the number of spills in the cases I've looked at. But
with x86, it's no guarantee the performance of the code improves.
It can be turned on with -sched-vertically option.
llvm-svn: 28108
2006-05-04 19:16:39 +00:00
53af9da363
Remove redundancy and a level of indirection when creating machine operands
...
llvm-svn: 28107
2006-05-04 19:14:44 +00:00
469647bf38
Remove and simplify some more machineinstr/machineoperand stuff.
...
llvm-svn: 28105
2006-05-04 18:16:01 +00:00
10b71c0d08
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
...
llvm-svn: 28104
2006-05-04 18:05:43 +00:00
10d6341618
Move some methods out of MachineInstr into MachineOperand
...
llvm-svn: 28102
2006-05-04 17:52:23 +00:00
fef7a2d0f5
There shalt be only one "immediate" operand type!
...
llvm-svn: 28099
2006-05-04 17:21:20 +00:00
15c52bda1d
Change "value" in MachineOperand to be a GlobalValue, as that is the only
...
thing that can be in it. Remove a dead method.
llvm-svn: 28098
2006-05-04 17:02:51 +00:00
ee64b6b40f
Remove a bunch more dead V9 specific stuff
...
llvm-svn: 28094
2006-05-04 01:26:39 +00:00
940cc978ef
Remove a bunch more SparcV9 specific stuff
...
llvm-svn: 28093
2006-05-04 01:15:02 +00:00
6e663f1c1e
Remove some more V9-specific stuff.
...
llvm-svn: 28092
2006-05-04 00:49:59 +00:00
9f6639b64d
Remove some more unused stuff from MachineInstr that was leftover from V9.
...
llvm-svn: 28091
2006-05-04 00:44:25 +00:00
1d8ee1fc80
Suck block address tracking out of targets into the JIT Emitter. This
...
simplifies the MachineCodeEmitter interface just a little bit and makes
BasicBlocks work like constant pools and jump tables.
llvm-svn: 28082
2006-05-03 17:10:41 +00:00
df4883971e
Finish up the initial jump table implementation by allowing jump tables to
...
not be 100% dense. Increase the minimum threshold for the number of cases
in a switch statement from 4 to 6 in order to create a jump table.
llvm-svn: 28079
2006-05-03 03:48:02 +00:00
ffef8b9412
Bottom up register pressure reduction work: clean up some hacks and enhanced
...
the heuristic to further reduce spills for several test cases. (Note, it may
not necessarily translate to runtime win!)
llvm-svn: 28076
2006-05-03 02:10:45 +00:00
20a631fde7
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
...
This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
d8b192ba3b
Change the BasicBlockAddrs map to be a vector, indexed by MBB number.
...
llvm-svn: 28069
2006-05-03 00:32:55 +00:00
b8065a9a3a
Several related changes:
...
1. Change several methods in the MachineCodeEmitter class to be pure virtual.
2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them
from the MachineCodeEmitter interface, and reducing the amount of target-
specific code.
3. Change the JITEmitter so that it allocates constantpools and jump tables
*right* next to the functions that they belong to, instead of in a separate
pool of memory. This makes all memory for a function be contiguous, and
means the JITEmitter only tracks one block of memory now.
llvm-svn: 28065
2006-05-02 23:22:24 +00:00
23621fe8f4
Do not make the JIT memory manager manage the memory for globals. Instead
...
just have the JIT malloc them.
llvm-svn: 28062
2006-05-02 21:57:51 +00:00
c9aa3715e8
Refactor the machine code emitter interface to pull the pointers for the current
...
code emission location into the base class, instead of being in the derived classes.
This change means that low-level methods like emitByte/emitWord now are no longer
virtual (yaay for speed), and we now have a framework to support growable code
segments. This implements feature request #1 of PR469.
llvm-svn: 28059
2006-05-02 18:27:26 +00:00
4971ba5f41
Print function number instead of name
...
llvm-svn: 28057
2006-05-02 17:36:46 +00:00
67a3aa2aaa
Remove dead method
...
llvm-svn: 28055
2006-05-02 17:20:28 +00:00
bb1c345ec6
Remove the debug machine code emitter. The "FilePrinterEmitter" is more
...
useful for debugging.
llvm-svn: 28051
2006-05-02 16:59:24 +00:00
b9d4f8324d
Extend printBasicBlockLabel a bit so that it can be used to print all
...
basic block labels, consolidating the code to do so in one place for each
target.
llvm-svn: 28050
2006-05-02 05:37:32 +00:00
470f431f44
De-virtualize SwitchSection.
...
llvm-svn: 28047
2006-05-02 03:58:45 +00:00
f34ddb1e0d
De-virtualize EmitZeroes.
...
llvm-svn: 28046
2006-05-02 03:46:13 +00:00
24a62a9bc1
Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work).
...
llvm-svn: 28044
2006-05-02 01:16:28 +00:00
fd0a5478a1
Fix a latent bug that my spiller patch last week exposed: we were leaving
...
instructions in the virtregfolded map that were deleted. Because they
were deleted, newly allocated instructions could end up at the same address,
magically finding themselves in the map. The solution is to remove entries
from the map when we delete the instructions.
llvm-svn: 28041
2006-05-01 22:03:24 +00:00
ab7dbe0cc9
When promoting a load to a reg-reg copy, where the load was a previous
...
instruction folded with spill code, make sure the remove the load from
the virt reg folded map.
llvm-svn: 28040
2006-05-01 21:17:10 +00:00
4dee67c2cd
Remove previous patch, which wasn't quite right.
...
llvm-svn: 28039
2006-05-01 21:16:03 +00:00
0d084fb9ca
Dis-favor stores more
...
llvm-svn: 28035
2006-05-01 09:20:44 +00:00
24e795496d
Bottom up register-pressure reduction scheduler now pushes store operations
...
up the schedule. This helps code that looks like this:
loads ...
computations (first set) ...
stores (first set) ...
loads
computations (seccond set) ...
stores (seccond set) ...
Without this change, the stores and computations are more likely to
interleave:
loads ...
loads ...
computations (first set) ...
computations (second set) ...
computations (first set) ...
stores (first set) ...
computations (second set) ...
stores (stores set) ...
This can increase the number of spills if we are unlucky.
llvm-svn: 28033
2006-05-01 09:14:40 +00:00
10ff7b27ce
Didn't mean ScheduleDAGList.cpp to make the last checkin.
...
llvm-svn: 28030
2006-05-01 08:56:34 +00:00
a656242690
Remove temp. option -spiller-check-liveout, it didn't cause any failure nor performance regressions.
...
llvm-svn: 28029
2006-05-01 08:54:57 +00:00
25f55ae74a
Format #APP lines a bit nicer
...
llvm-svn: 28026
2006-05-01 04:11:03 +00:00
f71f0f2e0b
Local spiller kills a store if the folded restore is turned into a copy.
...
But this is incorrect if the spilled value live range extends beyond the
current BB.
It is currently controlled by a temporary option -spiller-check-liveout.
llvm-svn: 28024
2006-04-30 08:41:47 +00:00
2b48a94413
Remove a bogus transformation. This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c
...
with some changes I have to the new CFE.
llvm-svn: 28022
2006-04-28 23:33:20 +00:00
c5e8ce8b8c
Remove the temporary option: -no-isel-fold-inflight
...
llvm-svn: 28012
2006-04-28 18:54:11 +00:00
d43c5c6046
TargetLowering::LowerArguments should return a VBIT_CONVERT of
...
FORMAL_ARGUMENTS SDOperand in the return result vector.
llvm-svn: 28009
2006-04-28 05:25:15 +00:00
79c50d96c9
Mapping of physregs can make it so that the designated and input physregs are
...
the same. In this case, don't emit a noop copy.
llvm-svn: 28008
2006-04-28 04:43:18 +00:00
51ab4498e7
Added a temporary option -no-isel-fold-inflight to control whether a "inflight"
...
node can be folded.
llvm-svn: 28003
2006-04-28 02:09:19 +00:00
84e95d00b5
When we have a two-address instruction where the input cannot be clobbered
...
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy. This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write. As one example, this change does:
pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
xorps %XMM2, %XMM5
cmpltps %XMM1, %XMM0
- movaps XMMWORD PTR [%ESP + 52], %XMM0
- movapd %XMM6, XMMWORD PTR [%ESP + 52]
+ movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
movapd XMMWORD PTR [%ESP + 52], %XMM6
movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
cmpltps %XMM3, %XMM0
- movaps XMMWORD PTR [%ESP + 20], %XMM0
- movapd %XMM7, XMMWORD PTR [%ESP + 20]
+ movaps %XMM7, %XMM0
cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
movapd XMMWORD PTR [%ESP + 20], %XMM7
cmpltps %XMM4, %XMM0
... which is far better than a store followed by a load!
llvm-svn: 28001
2006-04-28 01:46:50 +00:00
Jim Laskey