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Author SHA1 Message Date
Alex Bradbury fa7e4ec837 [RISCV] Implement floating point assembler pseudo instructions 
Adds the assembler aliases for the floating point instructions
which can be mapped to a single canonical instruction. The missing
pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.

This patch builds upon D40902.

Differential Revision: https://reviews.llvm.org/D41071

Patch by Mario Werner.

llvm-svn: 320569
 2017-12-13 11:37:19 +00:00
Alex Bradbury ee8950efd5 [RISCV] MC layer support for the standard RV64D instruction set extension 
llvm-svn: 320029
 2017-12-07 11:04:18 +00:00
Alex Bradbury 7bc2a95bb9 [RISCV] MC layer support for the standard RV32D instruction set extension 
As the FPR32 and FPR64 registers have the same names, use 
validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an 
FPR64 when necessary. The rest of this patch is very similar to the RV32F 
patch.

Differential Revision: https://reviews.llvm.org/D39895

llvm-svn: 320023
 2017-12-07 10:46:23 +00:00