dc4ca0dbbc
[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder
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Differential Revision: https://reviews.llvm.org/D104528
2021-07-27 11:27:58 +01:00
3fdf3b1539
AMDGPU: Update AMDHSA code object version handling
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Differential Revision: https://reviews.llvm.org/D89076
2020-10-14 13:04:27 -04:00
b3afad0463
[GlobalISel] Add a `X, Y = G_UNMERGE(G_ZEXT Z)` -> X = G_ZEXT Z; Y = 0 combine
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Add a combiner helper to transform unmerge of zext into one zext and
a constant 0
Differential Revision: https://reviews.llvm.org/D87427
2020-09-14 17:27:23 -07:00
4033aa1467
AMDGPU/GlobalISel: Sign extend integer constants
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This matches the DAG behavior and fixes immediate folding
2020-07-26 09:30:14 -04:00
a8816ebee0
[AMDGPU] Fix and simplify AMDGPULegalizerInfo::legalizeUDIV_UREM32Impl
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Use the algorithm from AMDGPUCodeGenPrepare::expandDivRem32.
Differential Revision: https://reviews.llvm.org/D83383
2020-07-08 19:14:49 +01:00
f4bd01c191
[AMDGPU] Fix and simplify AMDGPUCodeGenPrepare::expandDivRem32
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Fix the division/remainder algorithm by adding a second quotient
refinement step, which is required in some cases like
0xFFFFFFFFu / 0x11111111u (https://bugs.llvm.org/show_bug.cgi?id=46212 ).
Also document, rewrite and simplify it by ensuring that we always have a
lower bound on inv(y), which simplifies the UNR step and the quotient
refinement steps.
Differential Revision: https://reviews.llvm.org/D83381
2020-07-08 19:14:48 +01:00
3b34f3fcca
AMDGPU/GlobalISel: Fix obvious bug in ported 32-bit udiv/urem
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This was hidden by the IR expansion in AMDGPUCodeGenPrepare, which I
forgot to turn off.
2020-06-16 22:46:35 -04:00
f742a28ae3
AMDGPU/GlobalISel: Custom lower 32-bit G_SDIV/G_SREM
2020-02-17 15:09:51 -05:00
Jay Foad