68ec63b3d7
tLEApcrel is a AddrModeTs, i.e. pc relative.
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llvm-svn: 36502
2007-04-27 07:37:22 +00:00
6be85337b0
- Divides the comparisons in two types: comparisons that only use N and Z
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flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).
llvm-svn: 35573
2007-04-02 01:30:03 +00:00
cc44b1e743
Can't re-materialize mov r, imm in thumb since mov would clobber the condition code.
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llvm-svn: 35479
2007-03-29 21:38:31 +00:00
143b0dff31
bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK.
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llvm-svn: 35381
2007-03-27 16:19:21 +00:00
a88c4a74f3
bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted:
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mov lr, pc
bx lr
So, the function was not called.
llvm-svn: 35218
2007-03-20 17:57:23 +00:00
9bb01c9f4f
Fix naming inconsistencies.
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llvm-svn: 35163
2007-03-19 07:48:02 +00:00
ee2763f76f
Special LDR instructions to load from non-pc-relative constantpools. These are
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rematerializable. Only used for constant generation for now.
llvm-svn: 35162
2007-03-19 07:20:03 +00:00
5be3e09a30
Constant generation instructions are re-materializable.
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llvm-svn: 35161
2007-03-19 07:09:02 +00:00
ec13f826a2
Spill / restore should avoid modifying the condition register.
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llvm-svn: 33971
2007-02-07 00:06:56 +00:00
06736d0f88
.set pc relative displacement bug: label should be moved down one instruction
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to just before the add r1, pc:
Before:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
mov r1, #PCRELV0
add r1, pc
Now:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
mov r1, #PCRELV0
LPCRELL0:
add r1, pc
llvm-svn: 33744
2007-02-01 03:04:49 +00:00
e7e966de5e
Special epilogue for vararg functions. We cannot do a pop to pc because
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there follows a sp increment for the va register save region. Instead issue
a separate pop to another register, increment sp, and then return:
pop {r4, r5, r6, r7}
pop {r3}
add sp, #3 * 4
bx r3
llvm-svn: 33739
2007-02-01 01:49:46 +00:00
0584836340
Thumb asm syntax does not want 's' suffix for flag setting opcodes.
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llvm-svn: 33717
2007-01-31 20:12:31 +00:00
83f35170fa
- Fix codegen for pc relative constant (e.g. JT) in thumb mode:
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.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
mov r1, #PCRELV0
add r1, pc
- In thumb mode, it's not possible to use .set generate a pc relative stub
address. The stub is ARM code which is in a different section from the thumb
code. Load the value from a constpool instead.
- Some asm printing clean up.
llvm-svn: 33664
2007-01-30 20:37:08 +00:00
1cd3c0efb8
Change the operand orders to t_addrmode_s* to make it easier to morph
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instructions that use these address modes to instructions that use
t_addrmode_sp.
llvm-svn: 33651
2007-01-30 02:35:32 +00:00
863736b0ad
Use BL to implement Thumb far jumps.
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llvm-svn: 33649
2007-01-30 01:13:37 +00:00
0701c5a074
Thumb jumptable support.
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llvm-svn: 33568
2007-01-27 02:29:45 +00:00
f40b9006a8
Thumb add / sub with carry.
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llvm-svn: 33562
2007-01-27 00:07:15 +00:00
add7f164a1
Represent tADDspi and tSUBspi as two-address instructions.
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llvm-svn: 33551
2007-01-26 21:33:19 +00:00
d02d75c295
extload -> zextload
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llvm-svn: 33542
2007-01-26 19:13:16 +00:00
1526ba50d9
Use PC relative ldr to load from a constantpool in Thumb mode.
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llvm-svn: 33484
2007-01-24 08:53:17 +00:00
c0b7366cf9
- Reorg Thumb load / store instructions. Combine each rr and ri pair of
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instructions into one (e.g. tLDRrr, tLDRri -> tLDR).
- Thumb ldrsb and ldrsh only have the [reg, reg] address format. If the
address is not an add, materialize a 0 immediate into a register and use
it as the offset field.
llvm-svn: 33470
2007-01-23 22:59:13 +00:00
10043e215b
ARM backend contribution from Apple.
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llvm-svn: 33353
2007-01-19 07:51:42 +00:00
Evan Cheng