a9abf57409
Fix encoding problem for VMLS instruction.
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Thanks to Johnny Chen for pointing this out!
llvm-svn: 83256
2009-10-03 04:41:21 +00:00
1b2b64f618
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
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ld / st pairs, etc.
llvm-svn: 83197
2009-10-01 08:22:27 +00:00
bea6848f9d
Finish scheduling itineraries for NEON.
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llvm-svn: 82788
2009-09-25 18:38:29 +00:00
afcaf79603
Checkpoint NEON scheduling itineraries.
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llvm-svn: 82657
2009-09-23 21:38:08 +00:00
8d0fbebb9f
Add QPR_VFP2 regclass and add copy_to_regclass nodes, where needed to
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constraint the register usage.
llvm-svn: 81635
2009-09-12 22:21:08 +00:00
7697d37777
Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's.
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llvm-svn: 81262
2009-09-08 22:51:43 +00:00
59e2b8e894
Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and
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makes the code faster.
llvm-svn: 81220
2009-09-08 15:22:32 +00:00
f0da41c3e4
More missed vdup patterns
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llvm-svn: 80838
2009-09-02 21:21:28 +00:00
d7797754d4
Add support for generating code for vst{234}lane intrinsics.
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llvm-svn: 80707
2009-09-01 18:51:56 +00:00
da9817cddd
Generate code for vld{234}_lane intrinsics.
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llvm-svn: 80656
2009-09-01 04:26:28 +00:00
3681144bd8
Add missed pattern
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llvm-svn: 80502
2009-08-30 19:06:39 +00:00
cd41d07f29
Add missed extract_element pattern
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llvm-svn: 80408
2009-08-28 23:41:26 +00:00
076f105d86
Forgot about actual change :)
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llvm-svn: 80250
2009-08-27 16:10:17 +00:00
58ebae4acd
Transform float scalar_to_vector into subreg accesses.
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No idea whether this is profitable or not.
llvm-svn: 80245
2009-08-27 14:38:44 +00:00
f1beef9f48
Remove some unused SDNode definitions.
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llvm-svn: 80015
2009-08-25 17:52:39 +00:00
9129376719
Expose the instruction contraint string as an argument to the NLdSt class.
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llvm-svn: 80011
2009-08-25 17:46:06 +00:00
ceffeb6abd
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
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several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
llvm-svn: 79676
2009-08-21 21:58:55 +00:00
232b19c3d5
Fix some typos and use type-based isel for VZIP/VUZP/VTRN
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llvm-svn: 79625
2009-08-21 12:41:42 +00:00
ce3ff1be8a
Add nodes & dummy matchers for some v{zip,uzp,trn} instructions
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llvm-svn: 79622
2009-08-21 12:40:50 +00:00
38f284f2ae
Provide vext.{16,32}
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llvm-svn: 79620
2009-08-21 12:40:21 +00:00
32cd8550ce
Add support for Neon VEXT (vector extract) shuffles.
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This is derived from a patch by Anton Korzh. I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.
llvm-svn: 79428
2009-08-19 17:03:43 +00:00
eb54d51759
Create a new ARM-specific DAG node, VDUP, to represent a splat from a
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scalar_to_vector. Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.
llvm-svn: 78994
2009-08-14 05:13:08 +00:00
cce31f6831
During legalization, change Neon vdup_lane operations from shuffles to
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target-specific VDUPLANE nodes. This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.
llvm-svn: 78993
2009-08-14 05:08:32 +00:00
ef6e602bf4
Revert r78852 for now. I want to do this differently, but I don't have time
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to fix it tonight.
llvm-svn: 78896
2009-08-13 05:58:56 +00:00
ff2db10211
Recognize Neon VDUP shuffles during legalization instead of selection.
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llvm-svn: 78852
2009-08-12 22:54:19 +00:00
ea3a402ae7
Recognize Neon VREV shuffles during legalization instead of selection.
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llvm-svn: 78850
2009-08-12 22:31:50 +00:00
4b35448360
Generate Neon VTBL and VTBX instructions from the corresponding intrinsics.
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llvm-svn: 78835
2009-08-12 20:51:55 +00:00
25cae66713
Fix TableGen warnings. This partly reverts my previous change to this file,
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leaving the mayLoad and mayStore settings around only the load/store
instructions where those can't be inferred from the patterns.
llvm-svn: 78815
2009-08-12 17:04:56 +00:00
f042eadd1e
Add missing chain operands for VLD* and VST* instructions.
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Set "mayLoad" and "mayStore" on the load/store instructions.
llvm-svn: 78761
2009-08-12 00:49:01 +00:00
9f94459d24
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
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the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
12842f9865
Use vAny type to get rid of Neon intrinsics that differed only in whether
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the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.
If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.
llvm-svn: 78646
2009-08-11 05:39:44 +00:00
741a9c7bf6
Use new EVT::vAny type to combine Neon intrinsics for VPADD.
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llvm-svn: 78632
2009-08-11 01:15:26 +00:00
b80734bb15
Fix bug in NEON convert for single-precision FP. This also fixes the tblgen warnings.
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llvm-svn: 78629
2009-08-11 01:07:38 +00:00
53aa7a960c
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
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llvm-svn: 78610
2009-08-10 22:56:29 +00:00
85b5b027f7
Use NEON for single-precision int<->FP conversions.
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llvm-svn: 78604
2009-08-10 22:17:39 +00:00
cfed3005e5
Use subclassing to print lane-like immediates (w/o hash) eliminating
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'no_hash' modifier. Hopefully this will make Daniel happy :)
llvm-svn: 78514
2009-08-08 23:10:41 +00:00
7167f33872
Add insert_elt / extract_elt patterns for v4f32 stuff.
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Did anyone tests v4f32 ever?
llvm-svn: 78470
2009-08-08 14:06:07 +00:00
4218516f5d
Lane number should be printed w/o hash
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llvm-svn: 78469
2009-08-08 14:05:53 +00:00
887d05ce9b
Use VLDM / VSTM to spill/reload 128-bit Neon registers
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llvm-svn: 78468
2009-08-08 13:35:48 +00:00
e2231070ff
Implement Neon VZIP and VUZP instructions. These are very similar to VTRN,
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so I generalized the class for VTRN in the .td file to handle all 3 of them.
llvm-svn: 78460
2009-08-08 06:13:25 +00:00
db46af0461
Implement Neon VTRN instructions. For now, anyway, these are selected
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directly from the intrinsics produced by the frontend. If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.
llvm-svn: 78459
2009-08-08 05:53:00 +00:00
d28a26dfab
Unbreak the stuff
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llvm-svn: 78425
2009-08-07 22:51:13 +00:00
23b28cb824
2 more vdup.32 cases
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llvm-svn: 78419
2009-08-07 22:36:50 +00:00
4c3b1ca5a0
Fix support to use NEON for single precision fp math.
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llvm-svn: 78397
2009-08-07 19:30:41 +00:00
0127031c20
Implement Neon VST[234] operations.
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llvm-svn: 78330
2009-08-06 18:47:44 +00:00
b062c236c5
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
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llvm-svn: 78321
2009-08-06 16:52:47 +00:00
488db94e7b
Neon does not actually have VLD{234}.64 instructions.
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These operations will have to be synthesized from other instructions.
llvm-svn: 78263
2009-08-06 00:24:27 +00:00
e5b5d8fbb3
When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.
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llvm-svn: 78244
2009-08-05 21:02:22 +00:00
e219be7346
80 col violations.
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llvm-svn: 78175
2009-08-05 06:41:25 +00:00
20f79e321e
Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.
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Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions. The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.
llvm-svn: 78136
2009-08-05 00:49:09 +00:00
Bob Wilson