Commit Graph

44 Commits

Author SHA1 Message Date
Manman Ren 5097e4f38a Revert r157831
llvm-svn: 157896
2012-06-03 03:14:24 +00:00
Manman Ren 879ca9d47d X86: peephole optimization to remove cmp instruction
This patch will optimize the following:
  sub r1, r3
  cmp r3, r1 or cmp r1, r3
  bge L1
TO
  sub r1, r3
  bge L1 or ble L1

If the branch instruction can use flag from "sub", then we can eliminate
the "cmp" instruction.

llvm-svn: 157831
2012-06-01 19:49:33 +00:00
Preston Gurd 2eec367227 This patch adds X86 instruction itineraries, which were missed by the
original patch to add itineraries, to X86InstrArithmetc.td.  

llvm-svn: 154320
2012-04-09 15:32:22 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
llvm-svn: 150878
2012-02-18 12:03:15 +00:00
Andrew Trick 8523b16ff5 Instruction scheduling itinerary for Intel Atom.
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

llvm-svn: 149558
2012-02-01 23:20:51 +00:00
Craig Topper e94d277db8 Add X86 MULX instruction for disassembler.
llvm-svn: 142738
2011-10-23 00:33:32 +00:00
Craig Topper 7412aa9886 Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 multiply instructions.
llvm-svn: 142737
2011-10-22 23:13:53 +00:00
Craig Topper 965de2c197 Add X86 ANDN instruction. Including instruction selection.
llvm-svn: 141947
2011-10-14 07:06:56 +00:00
Jakob Stoklund Olesen 729abd360e Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies.
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.

TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.

This fixes PR11088.

llvm-svn: 141499
2011-10-08 18:28:28 +00:00
Craig Topper 7aea69d949 Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
llvm-svn: 140974
2011-10-02 21:08:12 +00:00
Craig Topper a88e356017 Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
llvm-svn: 139485
2011-09-11 21:41:45 +00:00
Chris Lattner 0ab5e2cded Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!

llvm-svn: 129558
2011-04-15 05:18:47 +00:00
Chris Lattner 846c20d4e6 Change the X86 backend to stop using the evil ADDC/ADDE/SUBC/SUBE nodes (which
their carry depenedencies with MVT::Flag operands) and use clean and beautiful
EFLAGS dependences instead.

We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs
(which is what requires the previous scheduler change) and change X86 ISelLowering
to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes.

With the previous series of changes, this causes no changes in the testsuite, woo.

llvm-svn: 122213
2010-12-20 00:59:46 +00:00
Chris Lattner 364bb0a081 it turns out that when ".with.overflow" intrinsics were added to the X86
backend that they were all implemented except umul.  This one fell back
to the default implementation that did a hi/lo multiply and compared the
top.  Fix this to check the overflow flag that the 'mul' instruction
sets, so we can avoid an explicit test.  Now we compile:

void *func(long count) {
      return new int[count];
}

into:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	seto	%cl                     ## encoding: [0x0f,0x90,0xc1]
	testb	%cl, %cl                ## encoding: [0x84,0xc9]
	movq	$-1, %rdi               ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
	cmoveq	%rax, %rdi              ## encoding: [0x48,0x0f,0x44,0xf8]
	jmp	__Znam                  ## TAILCALL

instead of:

__Z4funcl:                              ## @_Z4funcl
	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
	testq	%rdx, %rdx              ## encoding: [0x48,0x85,0xd2]
	movq	$-1, %rdi               ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
	cmoveq	%rax, %rdi              ## encoding: [0x48,0x0f,0x44,0xf8]
	jmp	__Znam                  ## TAILCALL

Other than the silly seto+test, this is using the o bit directly, so it's going in the right
direction.

llvm-svn: 120935
2010-12-05 07:30:36 +00:00
Chris Lattner 35e6ce479c fix a subtle bug I introduced in my refactoring, where we stopped preferring
the i8 versions of instructions in some cases.  In test6, we started 
generating:

	cmpq	$0, -8(%rsp)            ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00]
                                        ## <MCInst #478 CMP64mi32
                                        ##  <MCOperand Reg:114>
                                        ##  <MCOperand Imm:1>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:-8>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:0>>

instead of:

	cmpq	$0, -8(%rsp)            ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
                                        ## <MCInst #479 CMP64mi8
                                        ##  <MCOperand Reg:114>
                                        ##  <MCOperand Imm:1>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:-8>
                                        ##  <MCOperand Reg:0>
                                        ##  <MCOperand Imm:0>>

Fix this and add some comments.

llvm-svn: 116053
2010-10-08 05:12:14 +00:00
Chris Lattner f5c60d8156 convert test to use the existing classes that the multipatterns
use.  Since TEST is completely different than all other binops,
don't define a multipattern for it.

This completes factorization of binops.

llvm-svn: 115982
2010-10-07 21:31:03 +00:00
Chris Lattner ae8d67d3bb convert cmp to use a multipattern
llvm-svn: 115978
2010-10-07 20:56:25 +00:00
Chris Lattner a8c0bbb869 reduce redundancy between pattern copies.
llvm-svn: 115968
2010-10-07 20:14:23 +00:00
Chris Lattner 9fece2bea2 the opcode for BinOpMI/BinOpMI8 is always the same, remove the argument.
llvm-svn: 115967
2010-10-07 20:06:24 +00:00
Chris Lattner 752b60bc01 convert adc/sbb to a multipattern. Because the adde/sube nodes
are not defined as returning EFLAGS (like add_flag and friends),
the entire multipattern and several of the subclasses need to be
cloned.

This could be handled through better instantiation support in tblgen,
but it isn't meta enough.

llvm-svn: 115964
2010-10-07 20:01:55 +00:00
Chris Lattner 67677515ac add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS,
allowing us to convert ADD over.  deletes 160 lines of .td file.

llvm-svn: 115897
2010-10-07 01:37:01 +00:00
Chris Lattner 4fc52f6fa0 Fix a few issues in ArithBinOpEFLAGS that made it specific to and.
Start using ArithBinOpEFLAGS for OR, XOR, and SUB.

This removes 500 lines from the .td file.  Now AND/OR/XOR/SUB are all
defined exactly the same way instead of being close relatives.

llvm-svn: 115896
2010-10-07 01:26:27 +00:00
Chris Lattner 26d6a0449a Convert 'and' to single instance of a multipattern
which instantiates the 34 versions of and all in one
swoop.  The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.

No change in the generated .inc files.

llvm-svn: 115893
2010-10-07 01:10:20 +00:00
Chris Lattner b71a77d7b8 add a new BinOpAI class to represent the immediate form that directly acts on EAX.
This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.

llvm-svn: 115885
2010-10-07 00:43:39 +00:00
Chris Lattner 894d2e6146 add a bunch of classes for other common patterns.
As usual, no change in generated .inc files.

llvm-svn: 115882
2010-10-07 00:35:28 +00:00
Chris Lattner e17d7212f1 Define a new BinOpRI8 class and use it to define the imm8 versions of and.
llvm-svn: 115880
2010-10-07 00:12:45 +00:00
Chris Lattner 356f16c142 add the pattern operator to match to X86TypeInfo, use this to
convert AND64ri32 to use BinOpRI.

llvm-svn: 115878
2010-10-07 00:01:39 +00:00
Chris Lattner 6e85be2ecf enhance X86TypeInfo to include information about the encoding and
operand kind for immediates.  Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it.  AND64ri32 needs some
more refactoring before it can make the switcheroo.

llvm-svn: 115752
2010-10-06 05:55:42 +00:00
Chris Lattner 94eff91dc0 add a class for _REV nodes.
llvm-svn: 115748
2010-10-06 05:35:22 +00:00
Chris Lattner a46073b56b sink more intelligence into the ITy base class. Now it knows
that i8 operations are even and i16,i32,i64 operations have a
low opcode bit set (they are odd).

llvm-svn: 115747
2010-10-06 05:28:38 +00:00
Chris Lattner b6da2be7e8 refactor things a bit, now the REX_W and OpSize prefix bytes are inferred from the type info.
llvm-svn: 115745
2010-10-06 05:20:57 +00:00
Chris Lattner 7bbd809b6c with tblgen suitably extended, we can now get the load node from typeinfo.
llvm-svn: 115744
2010-10-06 04:58:43 +00:00
Chris Lattner 1fc81e90f7 lets go all meta and define new X86 type wrappers that declare the associated
gunk that goes along with an MVT (e.g. reg class, preferred load operation,
memory operand)

llvm-svn: 115727
2010-10-06 00:45:24 +00:00
Chris Lattner eadaeaab93 introduce a new BinOpRM class and use it to factor AND*rm. This points out
that I need a heavier handed approach to get ultimate factorization.

llvm-svn: 115726
2010-10-06 00:30:49 +00:00
Chris Lattner 61ea00b494 allow !strconcat to take more than two operands to eliminate
!strconcat(!strconcat(!strconcat(!strconcat

Simplify some x86 td files to use it.

llvm-svn: 115719
2010-10-05 23:58:18 +00:00
Chris Lattner 97b1368ae3 associate the instruction suffix letter with the integer gpr
register class, and use this to simplify use of BinOpRR.

llvm-svn: 115716
2010-10-05 23:43:04 +00:00
Chris Lattner 7359194b63 introduce a new BinOpRR class, and convert 4 and instructions to use it.
llvm-svn: 115715
2010-10-05 23:32:05 +00:00
Chris Lattner 13111b08fb Replace a gross hack (the MOV64ri_alt instruction) with a slightly less
gross hack (having the asmmatcher handle the alias).

llvm-svn: 115685
2010-10-05 21:09:45 +00:00
Chris Lattner ab85ef9e55 distribute the rest of the contents of X86Instr64bit.td out to
the right places.  X86Instr64bit.td now dies, long live x86-64!

llvm-svn: 115669
2010-10-05 20:49:15 +00:00
Chris Lattner 27c763d342 move the rest of the simple 64-bit arithmetic into InstrArithmetic.td
llvm-svn: 115663
2010-10-05 20:35:37 +00:00
Chris Lattner c2f5e5764f continue moving 64-bit stuff into X86InstrArithmetic.td
llvm-svn: 115660
2010-10-05 20:23:31 +00:00
Chris Lattner 7552d15d19 move 64-bit add and adc to InstrArithmetic.
llvm-svn: 115632
2010-10-05 16:59:08 +00:00
Chris Lattner 182e87caaf rewrote two addr constraints so that they are only set, not set and then nestedly cleared.
llvm-svn: 115631
2010-10-05 16:52:25 +00:00
Chris Lattner 39c70f4833 split the 32-bit integer arithmetic instructions out to their own file.
llvm-svn: 115627
2010-10-05 16:39:12 +00:00