Commit Graph

65 Commits

Author SHA1 Message Date
Andrew Trick 05ff4667eb Move RegisterClassInfo.h.
Allow targets to access this API. It's required for RegisterPressure.

llvm-svn: 158102
2012-06-06 20:29:31 +00:00
Andrew Trick 88517f608c Move RegisterPressure.h.
Make it a general utility for use by Targets.

llvm-svn: 158097
2012-06-06 19:47:35 +00:00
Andrew Trick 4544606c71 misched: API for minimum vs. expected latency.
Minimum latency determines per-cycle scheduling groups.
Expected latency determines critical path and cost.

llvm-svn: 158021
2012-06-05 21:11:27 +00:00
Andrew Trick d36adece50 misched: comments from code review.
llvm-svn: 157975
2012-06-05 03:44:26 +00:00
Andrew Trick 4e7f6a7702 misched: trace formatting
llvm-svn: 157455
2012-05-25 02:02:39 +00:00
Kaelyn Uhrain 85d8f0cba8 Silence unused variable warnings from when assertions are disabled.
llvm-svn: 157438
2012-05-24 23:37:49 +00:00
Andrew Trick a306a8a844 misched: Use the same scheduling heuristics with -misched-topdown/bottomup.
(except the part about choosing direction)

llvm-svn: 157437
2012-05-24 23:11:17 +00:00
Andrew Trick 79d3eecbb4 misched: Trace regpressure.
llvm-svn: 157429
2012-05-24 22:11:14 +00:00
Andrew Trick a8ad5f7c7b misched: Give each ReadyQ a unique ID
llvm-svn: 157428
2012-05-24 22:11:12 +00:00
Andrew Trick 61f1a278b8 misched: Added ScoreboardHazardRecognizer.
The Hazard checker implements in-order contraints, or interlocked
resources. Ready instructions with hazards do not enter the available
queue and are not visible to other heuristics.

The major code change is the addition of SchedBoundary to encapsulate
the state at the top or bottom of the schedule, including both a
pending and available queue.

The scheduler now counts cycles in sync with the hazard checker. These
are minimum cycle counts based on known hazards.

Targets with no itinerary (x86_64) currently remain at cycle 0. To fix
this, we need to provide some maximum issue width for all targets. We
also need to add the concept of expected latency vs. minimum latency.

llvm-svn: 157427
2012-05-24 22:11:09 +00:00
Andrew Trick ca47335461 misched: Release bottom roots in reverse order.
llvm-svn: 157426
2012-05-24 22:11:05 +00:00
Andrew Trick dd375dd34a misched: rename ReadyQ class
llvm-svn: 157425
2012-05-24 22:11:03 +00:00
Andrew Trick f378617773 misched: copy comments so compareRPDelta is readable by itself.
llvm-svn: 157424
2012-05-24 22:11:01 +00:00
Andrew Trick 6a50baa26e comments
llvm-svn: 157020
2012-05-17 22:37:09 +00:00
Andrew Trick 276a3e8c46 misched: trace ReadyQ.
llvm-svn: 157007
2012-05-17 18:35:13 +00:00
Andrew Trick 2202577d80 misched: Added 3-level regpressure back-off.
Introduce the basic strategy for register pressure scheduling.

1) Respect target limits at all times.

2) Indentify critical register classes (pressure sets).
   Track pressure within the scheduled region.
   Avoid increasing scheduled pressure for critical registers.

3) Avoid exceeding the max pressure of the region prior to scheduling.

Added logic for picking between the top and bottom ready Q's based on
regpressure heuristics.

Status: functional but needs to be asjusted to achieve good results.
llvm-svn: 157006
2012-05-17 18:35:10 +00:00
Andrew Trick 47a1feaea0 comment
llvm-svn: 157005
2012-05-17 18:35:07 +00:00
Andrew Trick 463b2f1f04 misched: fix liveness iterators
llvm-svn: 157003
2012-05-17 18:35:03 +00:00
Andrew Trick c5d7008f27 misched: Print machineinstrs with -debug-only=misched
llvm-svn: 156576
2012-05-10 21:06:21 +00:00
Andrew Trick 419eae2db7 misched: tracing register pressure heuristics.
llvm-svn: 156575
2012-05-10 21:06:19 +00:00
Andrew Trick 7ee9de51f2 misched: Add register pressure backoff to ConvergingScheduler.
Prioritize the instruction that comes closest to keeping pressure
under the target's limit. Then prioritize instructions that avoid
increasing the max pressure in the scheduled region. The max pressure
heuristic is a tad aggressive. Later I'll fix it to consider the
unscheduled pressure as well.

WIP: This is mostly functional but untested and not likely to do much good yet.
llvm-svn: 156574
2012-05-10 21:06:16 +00:00
Andrew Trick 795c1120a6 misched: Release only unscheduled nodes into ReadyQ.
llvm-svn: 156573
2012-05-10 21:06:14 +00:00
Andrew Trick 95dafd8b31 misched: Added ReadyQ container wrapper for Top and Bottom Queues.
llvm-svn: 156572
2012-05-10 21:06:12 +00:00
Andrew Trick 4add42f439 misched: Introducing Top and Bottom register pressure trackers during scheduling.
llvm-svn: 156571
2012-05-10 21:06:10 +00:00
Andrew Trick 4d4b5469ab Fix a naughty header include that breaks "installed" builds.
llvm-svn: 155486
2012-04-24 20:36:19 +00:00
Andrew Trick c3ea00565f misched: try (not too hard) to place debug values where they belong
llvm-svn: 155458
2012-04-24 18:04:37 +00:00
Andrew Trick cc45a28320 misched: ignore debug values during scheduling
llvm-svn: 155457
2012-04-24 18:04:34 +00:00
Andrew Trick 88639928bd misched: DAG builder support for tracking register pressure within the current scheduling region.
The DAG builder is a convenient place to do it. Hopefully this is more
efficient than a separate traversal over the same region.

llvm-svn: 155456
2012-04-24 17:56:43 +00:00
Andrew Trick 779b32a44e misched: Add finalizeScheduler to complete the target interface.
llvm-svn: 153827
2012-04-01 07:24:23 +00:00
Andrew Trick adb03b91ee misched: trace LiveIntervals after scheduling.
llvm-svn: 153161
2012-03-21 04:12:12 +00:00
Andrew Trick 54f7def703 misched: obvious iterator update fixes for bottom-up.
llvm-svn: 153160
2012-03-21 04:12:10 +00:00
Andrew Trick de670c0304 misched: cleanup main loop
llvm-svn: 153159
2012-03-21 04:12:07 +00:00
Lang Hames dd98c497b9 Add an option to the MI scheduler to cut off scheduling after a fixed number of
instructions have been scheduled. Handy for tracking down scheduler bugs, or
bugs exposed by scheduling.

llvm-svn: 153045
2012-03-19 18:38:38 +00:00
Benjamin Kramer 05e7a843aa Silence operator precedence warnings.
llvm-svn: 152711
2012-03-14 11:26:37 +00:00
Andrew Trick 8823decdd4 misched: implemented a framework for top-down or bottom-up scheduling.
New flags: -misched-topdown, -misched-bottomup. They can be used with
the default scheduler or with -misched=shuffle. Without either
topdown/bottomup flag -misched=shuffle now alternates scheduling
direction.

LiveIntervals update is unimplemented with bottom-up scheduling, so
only -misched-topdown currently works.

Capped the ScheduleDAG hierarchy with a concrete ScheduleDAGMI class.
ScheduleDAGMI is aware of the top and bottom of the unscheduled zone
within the current region. Scheduling policy can be plugged into
the ScheduleDAGMI driver by implementing MachineSchedStrategy.
ConvergingScheduler is now the default scheduling algorithm.
It exercises the new driver but still does no reordering.

llvm-svn: 152700
2012-03-14 04:00:41 +00:00
Andrew Trick 72515bef32 misched comments
llvm-svn: 152699
2012-03-14 04:00:38 +00:00
Andrew Trick af1bee7235 misched: handle scheduler that insert instructions at empty region boundaries.
And add comments, since this is obviously confusing.

llvm-svn: 152445
2012-03-09 22:34:56 +00:00
Andrew Trick edfe2ec429 misched: handle scheduling region boundaries nicely.
llvm-svn: 152393
2012-03-09 08:02:51 +00:00
Andrew Trick 8c207e47c1 misched interface: rename Begin/End to RegionBegin/RegionEnd since they are not private.
llvm-svn: 152382
2012-03-09 04:29:02 +00:00
Andrew Trick 1c0ec45b67 misched comments
llvm-svn: 152374
2012-03-09 03:46:42 +00:00
Andrew Trick a21daf7f5b revert 152356: verify misched changes using -misched=shuffle.
llvm-svn: 152373
2012-03-09 03:46:39 +00:00
Andrew Trick 453006875c misched: allow the default scheduler to be one chosen by the target.
llvm-svn: 152360
2012-03-09 00:52:20 +00:00
Evan Cheng bc3b4e3f12 Cache MBB->begin. It's possible the scheduler / bundler may change MBB->begin().
llvm-svn: 152356
2012-03-09 00:24:29 +00:00
Andrew Trick 02a80da331 misched interface: Expose the MachineScheduler pass.
Allow targets to provide their own schedulers (subclass of
ScheduleDAGInstrs) to the misched pass. Select schedulers using
-misched=...

llvm-svn: 152278
2012-03-08 01:41:12 +00:00
Andrew Trick 9a0c583954 misched prep: Expose the ScheduleDAGInstrs interface so targets may
implement their own MachineScheduler.

llvm-svn: 152261
2012-03-07 23:01:06 +00:00
Andrew Trick a316faabec misched prep: rename InsertPos to End.
ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted.

llvm-svn: 152256
2012-03-07 23:00:52 +00:00
Andrew Trick 52226d409b misched preparation: rename core scheduler methods for consistency.
We had half the API with one convention, half with another. Now was a
good time to clean it up.

llvm-svn: 152255
2012-03-07 23:00:49 +00:00
Andrew Trick 60cf03e772 misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.
ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation.

ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class.

ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target.

Specific changes:
- Removed driver code from ScheduleDAG. clearDAG is the only interface needed.

- Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls.

- Added ScheduleDAGInstrs::begin()/end() public API.

- Moved Sequence into the driver layer, which is specific to the scheduling algorithm.

llvm-svn: 152208
2012-03-07 05:21:52 +00:00
Andrew Trick a5f19560fb Added -view-misched=dags options.
llvm-svn: 152178
2012-03-07 00:18:25 +00:00
Andrew Trick 3b6eb1e5ea misched: Use the StartBlock/FinishBlock hooks
llvm-svn: 152172
2012-03-07 00:18:05 +00:00