Commit Graph

36 Commits

Author SHA1 Message Date
Javed Absar b672722810 [ARM] Classification Improvements to ARM Sched-Models. NFCI.
This patch adds missing sched classes for Thumb2 instructions.
This has been missing so far, and as a consequence, machine
scheduler models for individual sub-targets have tended to
be larger than they needed to be. These patches should help
write schedulers better and faster in the future
for ARM sub-targets.

Reviewer: Diana Picus
Differential Revision: https://reviews.llvm.org/D29953

llvm-svn: 295811
2017-02-22 07:22:57 +00:00
Javed Absar bb8dcc6aec [ARM] Classification Improvements to ARM Sched-Model. NFCI.
This is the second in the series of patches to enable adding
of machine sched-models for ARM processors easier and compact.
This patch focuses on integer instructions and adds missing
sched definitions.

Reviewers: rovka, rengolin
Differential Revision: https://reviews.llvm.org/D29127

llvm-svn: 293935
2017-02-02 21:08:12 +00:00
Javed Absar 00cce41752 [ARM] Classification Improvements to ARM Sched-Models. NFCI.
This is a series of patches to enable adding of machine sched
models for ARM processors easier and compact. They define new
sched-readwrites for groups of ARM instructions. This has been
missing so far, and as a consequence, machine scheduler models
for individual sub-targets have tended to be larger than they
needed to be. 

The current patch focuses on floating-point instructions.

Reviewers: Diana Picus (rovka), Renato Golin (rengolin)

Differential Revision: https://reviews.llvm.org/D28194

llvm-svn: 292825
2017-01-23 20:20:39 +00:00
Duncan P. N. Exon Smith 9cfc75c214 CodeGen: Use MachineInstr& in TargetInstrInfo, NFC
This is mostly a mechanical change to make TargetInstrInfo API take
MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator)
when the argument is expected to be a valid MachineInstr.  This is a
general API improvement.

Although it would be possible to do this one function at a time, that
would demand a quadratic amount of churn since many of these functions
call each other.  Instead I've done everything as a block and just
updated what was necessary.

This is mostly mechanical fixes: adding and removing `*` and `&`
operators.  The only non-mechanical change is to split
ARMBaseInstrInfo::getOperandLatencyImpl out from
ARMBaseInstrInfo::getOperandLatency.  Previously, the latter took a
`MachineInstr*` which it updated to the instruction bundle leader; now,
the latter calls the former either with the same `MachineInstr&` or the
bundle leader.

As a side effect, this removes a bunch of MachineInstr* to
MachineBasicBlock::iterator implicit conversions, a necessary step
toward fixing PR26753.

Note: I updated WebAssembly, Lanai, and AVR (despite being
off-by-default) since it turned out to be easy.  I couldn't run tests
for AVR since llc doesn't link with it turned on.

llvm-svn: 274189
2016-06-30 00:01:54 +00:00
James Molloy fa4e994a7a [ARM] Mark Swift MISched model as incomplete
The Swift Machine Scheduler Model is incomplete. There are instructions
missing which can trigger the "incomplete machine model" abort. This was
observed when a downstream SchedMachineModel was added to the ARM
target.

Patch by Christof Douma!

llvm-svn: 250033
2015-10-12 12:49:59 +00:00
Matthias Braun 9e85980658 ARM: Enable MachineScheduler and disable PostRAScheduler for swift.
Reapply r242500 now that the swift schedmodel includes LDRLIT.

This is mostly done to disable the PostRAScheduler which optimizes for
instruction latencies which isn't a good fit for out-of-order
architectures. This also allows to leave out the itinerary table in
swift in favor of the SchedModel ones.

This change leads to performance improvements/regressions by as much as
10% in some benchmarks, in fact we loose 0.4% performance over the
llvm-testsuite for reasons that appear to be unknown or out of the
compilers control. rdar://20803802 documents the investigation of
these effects.

While it is probably a good idea to perform the same switch for the
other ARM out-of-order CPUs, I limited this change to swift as I cannot
perform the benchmark verification on the other CPUs.

Differential Revision: http://reviews.llvm.org/D10513

llvm-svn: 242588
2015-07-17 23:18:30 +00:00
Matthias Braun 141d1c9d8f ARM: Add scheduling information for LDRLIT instructions to swift scheduling model
These pseudo instructions are only lowered after register allocation and
are therefore still present when the machine scheduler runs.
Add a run: line to a testcase that uses the uncommon flags necessary to
actually produce a LDRLIT instruction on swift.

llvm-svn: 242587
2015-07-17 23:18:26 +00:00
Adam Nemet 5a6d5bc17b Revert "ARM: Enable MachineScheduler and disable PostRAScheduler for swift."
This reverts commit r242500.

It broke some internal tests and Matthias asked me to revert it while he
is investigating.

llvm-svn: 242553
2015-07-17 18:14:19 +00:00
Matthias Braun 2d8315f806 ARM: Enable MachineScheduler and disable PostRAScheduler for swift.
This is mostly done to disable the PostRAScheduler which optimizes for
instruction latencies which isn't a good fit for out-of-order
architectures. This also allows to leave out the itinerary table in
swift in favor of the SchedModel ones.

This change leads to performance improvements/regressions by as much as
10% in some benchmarks, in fact we loose 0.4% performance over the
llvm-testsuite for reasons that appear to be unknown or out of the
compilers control. rdar://20803802 documents the investigation of
these effects.

While it is probably a good idea to perform the same switch for the
other ARM out-of-order CPUs, I limited this change to swift as I cannot
perform the benchmark verification on the other CPUs.

Differential Revision: http://reviews.llvm.org/D10513

llvm-svn: 242500
2015-07-17 01:44:31 +00:00
Matthias Braun b5424d043b Revert "ARM: Remove Itineraries for swift CPU"
Reverting until I figure out the new lit failures.

This reverts commit r237179.

llvm-svn: 237189
2015-05-12 21:28:39 +00:00
Matthias Braun befa1380d2 ARM: Remove Itineraries for swift CPU
They do more harm than good when used in the MachineScheduler as they
tend to take preference to register pressure minimsation which is more
important for swift.

Differential Revision: http://reviews.llvm.org/D9718

llvm-svn: 237179
2015-05-12 21:07:54 +00:00
Alp Toker cb40291100 Fix known typos
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.

llvm-svn: 200018
2014-01-24 17:20:08 +00:00
Arnold Schwaighofer 66eb921a82 Swift model: Fix uop description on some writes
Those writes really need two/three uops.

llvm-svn: 191677
2013-09-30 15:56:34 +00:00
Andrew Trick 18dc3da855 Update machine models. Specify buffer sizes for OOO processors.
llvm-svn: 184033
2013-06-15 04:50:02 +00:00
Arnold Schwaighofer c5893da32d ARM sched model: Use the right resources for DIV
llvm-svn: 183477
2013-06-07 01:16:15 +00:00
Arnold Schwaighofer 5f0a2ce542 ARM sched model: Add VFP div instruction on Swift
Reapply 183271.

llvm-svn: 183472
2013-06-07 01:10:36 +00:00
Arnold Schwaighofer a30936a33b ARM sched model: Add SIMD/VFP load/store instructions on Swift
Reapply 183270 again (because three is a magic number).

This should now no longer seg fault after r183459.

llvm-svn: 183464
2013-06-07 00:04:28 +00:00
Arnold Schwaighofer e5f6a8f649 Revert "ARM sched model: Add SIMD/VFP load/store instructions on Swift"
Breaks linux build bots (I thought the problem was something else).

llvm-svn: 183447
2013-06-06 21:08:18 +00:00
Arnold Schwaighofer cfe830dc52 ARM sched model: Add SIMD/VFP load/store instructions on Swift
Reapply 183270.

llvm-svn: 183445
2013-06-06 21:02:18 +00:00
Arnold Schwaighofer eac54473dd ARM sched model: Add integer VFP/SIMD instructions on Swift
Reapply 183269.

llvm-svn: 183441
2013-06-06 20:26:18 +00:00
Arnold Schwaighofer dff8e4c488 ARM sched model: Add integer load/store instructions on Swift
Reapply 183268.

llvm-svn: 183438
2013-06-06 20:11:56 +00:00
Arnold Schwaighofer 41a7b06888 ARM sched model: Add integer arithmetic instructions on Swift
Reapply 183267.

llvm-svn: 183436
2013-06-06 19:49:46 +00:00
Arnold Schwaighofer 2773f1deb4 ARM sched model: Add divsion, loads, branches, vfp cvt
Add some generic SchedWrites and assign resources for Swift and Cortex A9.

Reapply of r183257. (Removed empty InstRW for division on swift)

llvm-svn: 183319
2013-06-05 16:06:11 +00:00
Arnold Schwaighofer 2a70c69d31 Revert series of sched model patches until I figure out what is going on.
llvm-svn: 183273
2013-06-04 22:35:17 +00:00
Arnold Schwaighofer 0024b8bd73 ARM sched model: Add VFP div instruction on Swift
llvm-svn: 183271
2013-06-04 22:16:08 +00:00
Arnold Schwaighofer 89901730b1 ARM sched model: Add SIMD/VFP load/store instructions on Swift
llvm-svn: 183270
2013-06-04 22:16:07 +00:00
Arnold Schwaighofer bc61f0912c ARM sched model: Add integer VFP/SIMD instructions on Swift
llvm-svn: 183269
2013-06-04 22:16:05 +00:00
Arnold Schwaighofer 83a4197085 ARM sched model: Add integer load/store instructions on Swift
llvm-svn: 183268
2013-06-04 22:16:04 +00:00
Arnold Schwaighofer f77ea45488 ARM sched model: Add integer arithmetic instructions on Swift
llvm-svn: 183267
2013-06-04 22:16:02 +00:00
Arnold Schwaighofer d5b9794a53 ARM sched model: Add divsion, loads, branches, vfp cvt
Add some generic SchedWrites and assign resources for Swift and Cortex A9.

llvm-svn: 183257
2013-06-04 22:15:46 +00:00
Arnold Schwaighofer fb6b9f48d0 ARM scheduler model: Add scheduler info to more instructions and resource
descriptions for compares

llvm-svn: 178844
2013-04-05 05:01:06 +00:00
Arnold Schwaighofer 5dde1f39c1 ARM scheduler model: Swift has varying latencies, uops for simple ALU ops
llvm-svn: 178842
2013-04-05 04:42:00 +00:00
Arnold Schwaighofer 6793aebb84 ARM Scheduler Model: Add resources instructions, map resources in subtargets
Reapply r177968:
After commit 178074 we can now have undefined scheduler variants.

Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.

Incooperate Andrew's feedback.

llvm-svn: 178460
2013-04-01 13:07:05 +00:00
Arnold Schwaighofer 414ef565bb Revert ARM Scheduler Model: Add resources instructions, map resources
This reverts commit r177968. It is causing failures in a local build bot.

"fatal error: error in backend: Expected a variant SchedClass"

Original commit message:
Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.

llvm-svn: 178028
2013-03-26 15:14:04 +00:00
Arnold Schwaighofer ce6392611b ARM Scheduler Model: Add resources instructions, map resources in subtargets
Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.

llvm-svn: 177968
2013-03-26 02:01:42 +00:00
Bob Wilson e8a549cd92 Add LLVM support for Swift.
llvm-svn: 164899
2012-09-29 21:43:49 +00:00