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6 Commits

Author SHA1 Message Date
ShihPo Hung 5cdb2e9860 [RISCV][MC] Fix nf encoding for vector ld/st whole register 
The three bit nf is one less than the number of NFIELDS,
so we manually decrement 1 for VS1/2/4/8R & VL1/2/4/8R.

Reviewed By: craig.topper

Differential revision: https://reviews.llvm.org/D98185
 2021-03-08 19:30:24 -08:00
Hsiangkai Wang 53c4c2b9f7 [RISCV] vle1.v/vse1.v should be unmasked instructions. 
vle1.v/vse1.v should be unmasked instructions. The vm encoding is 1 for
unmasked instructions.

Differential Revision: https://reviews.llvm.org/D97237
 2021-02-23 19:59:22 +08:00
Hsiangkai Wang c7189ba785 [RISCV] Add new vector instructions in v0.10. 
* Add new vector instructions in v0.10.
 - load/store for mask value vle1.v vse1.v
 - vsetivli for 0-31 immediate vector length.
* Rename vector instructions in v0.10.
 - vfrsqrte7 -> vfrsqrt7
 - vfrece7 -> vfrec7
* Reserve memory width encodings for EEW>128b.

Differential Revision: https://reviews.llvm.org/D95781
 2021-02-03 13:28:58 +08:00
Hsiangkai Wang b7ab6726b6 [RISCV] New vector load/store in V extension v1.0 
Upgrade RISC-V V extension to v1.0-08a0b46.
Indexed load/store have ordered and unordered form.
New whole vector load/store.

Differential Revision: https://reviews.llvm.org/D93614
 2021-01-22 07:30:09 +08:00
Hsiangkai Wang 47a4a27f47 Upgrade MC to v0.9. 
Differential revision: https://reviews.llvm.org/D80802
 2020-08-01 07:42:06 +08:00
Hsiangkai Wang 66da87dcba [RISCV] Assemble/Disassemble v-ext instructions. 
Assemble/disassemble RISC-V V extension instructions according to
latest version spec in https://github.com/riscv/riscv-v-spec/.

I have tested this patch using GNU toolchain. The encoding is aligned
to GNU assembler output. In this patch, there is a test case for each
instruction at least.

The V register definition is just for assemble/disassemble. Its type
is not important in this stage. I think it will be reviewed and modified
as we want to do codegen for scalable vector types.

This patch does not include Zvamo, Zvlsseg, and Zvediv.

Differential revision: https://reviews.llvm.org/D69987
 2020-06-28 00:54:07 +08:00