Ehsan Amiri
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ed7bcb2cb1
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[AArch64][SVE] Add patterns for some integer vector instructions
Add pattern matching for SVE vector instructions:
-- add, sub, and, or, xor instructions
-- sqadd, uqadd, sqsub, uqsub target-independent intrinsics
-- bic intrinsics
-- predicated add, sub, subr intrinsics
Patch Review: https://reviews.llvm.org/D69128
Patch authored by: dancgr (Danilo Carvalho Grael)
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2019-10-30 21:52:19 -04:00 |