fb706bc52b
Initial commit of the machine code LICM pass. It successfully hoists this:
...
_foo:
li r2, 0
LBB1_1: ; bb
li r5, 0
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
to:
_foo:
li r2, 0
li r5, 0
LBB1_1: ; bb
stw r5, 0(r3)
addi r2, r2, 1
addi r3, r3, 4
cmplw cr0, r2, r4
bne cr0, LBB1_1 ; bb
LBB1_2: ; return
blr
ZOMG!! :-)
Moar to come...
llvm-svn: 44687
2007-12-07 21:42:31 +00:00
14bbb15f07
Move subreg lowering pass to be right after regalloc, per feedback.
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llvm-svn: 40548
2007-07-27 07:36:14 +00:00
e9d738cefc
Add a MachineFunction pass, which runs post register allocation, that turns subreg insert/extract instruction into register copies. This ensures correct code gen if the coalescer isn't able to remove all subreg instructions.
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llvm-svn: 40521
2007-07-26 08:18:32 +00:00
9d5df0a5f6
Added -print-emitted-asm to print out JIT generated asm to cerr.
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llvm-svn: 40123
2007-07-20 21:56:13 +00:00
4dc35dbd3e
Modify previous patch per review comments.
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llvm-svn: 39817
2007-07-13 17:31:29 +00:00
2182f06f2d
Skeleton of post-RA scheduler; doesn't do anything yet.
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Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.
llvm-svn: 39816
2007-07-13 17:13:54 +00:00
03b274911f
Exception handling has been implemented.
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llvm-svn: 39732
2007-07-11 16:59:20 +00:00
37228f6ce5
document and hide two options.
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llvm-svn: 37651
2007-06-19 05:47:49 +00:00
f9cbdc676c
name change requested by review of previous patch
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llvm-svn: 37289
2007-05-22 18:31:04 +00:00
82810c8a13
Make tail merging the default, except on powerPC. There was no prior art
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for a target-dependent default with a command-line override; this way
should be generally usable.
llvm-svn: 37285
2007-05-22 17:14:46 +00:00
f6a6d3c8b0
move a bunch of code out of the sdisel pass into its own opt pass "codegenprepare".
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llvm-svn: 35529
2007-03-31 04:18:03 +00:00
bafc837c83
Add a -print-lsr-output option to LLC, to print the output of the LSR pass.
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llvm-svn: 35522
2007-03-31 00:24:43 +00:00
b0743b5d6a
Now LoopStrengthReduce is a LoopPass.
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llvm-svn: 34984
2007-03-06 21:14:09 +00:00
69bd45c1d2
Use exception flag.
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llvm-svn: 34496
2007-02-22 16:22:15 +00:00
523048ecde
Split the addPassesToEmitFile method up into two. This is so that we can
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do some common stuff, then on our own add an object file writer (by calling
a concrete function), and then do some finishing stuff, if need be.
llvm-svn: 34032
2007-02-08 01:36:53 +00:00
355fc5ad50
Removed more <iostream> includes
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llvm-svn: 32321
2006-12-07 20:28:15 +00:00
e0a70388c2
enable the branch folding pass for the JIT.
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llvm-svn: 31777
2006-11-16 01:00:07 +00:00
6ea4fae838
1. Add a pass to fold debug label instructions so a debug info client can detect
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empty ranges.
2. Reorg how MachineDebugInfo maintains changes to debug labels.
3. Have dwarf writer use debug label info to simplify scopes and source line
coorespondence.
4. Revert the merging of compile units until I can get the bugs ironed out.
llvm-svn: 31507
2006-11-07 19:33:46 +00:00
1941bfa361
Don't do dead block elimination in fast mode.
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llvm-svn: 31155
2006-10-24 16:11:49 +00:00
55ad08a59b
add the branch folding pass as a late cleanup pass for all targets. For now
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it just deletes empty MBB's. Soon it will do more :)
llvm-svn: 30941
2006-10-13 20:45:56 +00:00
cf6749e4c0
add setJumpBufSize() and setJumpBufAlignment() to target-lowering.
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Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example
llvm-svn: 30095
2006-09-04 06:21:35 +00:00
a916db12e4
new file
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llvm-svn: 30082
2006-09-04 04:16:09 +00:00
Bill Wendling