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5 Commits

Author SHA1 Message Date
Luis Marques 3d0fbafd0b [RISCV] Switch to the Machine Scheduler 
Most of the test changes are trivial instruction reorderings and differing
register allocations, without any obvious performance impact.

Differential Revision: https://reviews.llvm.org/D66973

llvm-svn: 372106
 2019-09-17 11:15:35 +00:00
Luis Marques 2d550d19b3 Revert Patch from Phabricator 
This reverts r372092 (git commit e38695a025)

llvm-svn: 372104
 2019-09-17 10:52:09 +00:00
Luis Marques e38695a025 Patch from Phabricator 
llvm-svn: 372092
 2019-09-17 09:43:08 +00:00
Luis Marques 72734fc7b5 [RISCV] Update setcc-logic.ll codegen test 
This should have been updated as part of D59753.

llvm-svn: 357002
 2019-03-26 15:41:45 +00:00
Alex Bradbury 3369101158 [RISCV] Allow conversion of CC logic to bitwise logic 
Indicates in the TargetLowering interface that conversions from CC logic to
bitwise logic are allowed. Adds tests that show the benefit when optimization
opportunities are detected. Also adds tests that show that when the optimization
is not applied correct code is generated (but opportunities for other
optimizations remain).

Differential Revision: https://reviews.llvm.org/D59596
Patch by Luís Marques.

llvm-svn: 356740
 2019-03-22 10:39:22 +00:00