Commit Graph

1619 Commits

Author SHA1 Message Date
Jack Carter 7ab15fafe3 This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Formatting fixes. Mostly long lines and 
blank spaces at end of lines.

Contributer: Jack Carter
 
llvm-svn: 172882
2013-01-19 02:00:40 +00:00
Jack Carter c1b17ed2e1 This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Support for Mips register information sections.

Mips ELF object files have a section that is dedicated
to register use info. Some of this information such as
the assumed Global Pointer value is used by the linker
in relocation resolution.

The register info file is .reginfo in o32 and .MIPS.options
in 64 and n32 abi files.

This patch contains the changes needed to create the sections,
but leaves the actual register accounting for a future patch.


Contributer: Jack Carter
 
llvm-svn: 172847
2013-01-18 21:20:38 +00:00
Jack Carter 86c2c564ff This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.

Removal of redundant code and formatting fixes.

Contributers: Jack Carter/Vladimir Medic
 
llvm-svn: 172842
2013-01-18 20:15:06 +00:00
Jack Carter 2a74a87b71 This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.

The Mips RDHWR (Read Hardware Register) instruction was not 
tested for assembler or dissassembler consumption. This patch
adds that functionality.

Contributer: Vladimir Medic
 
llvm-svn: 172685
2013-01-17 00:28:20 +00:00
Jack Carter 5619f91bf7 reverting 172579
llvm-svn: 172594
2013-01-16 01:29:10 +00:00
Jack Carter e0c1e1a47e Akira,
Hope you are feeling better.

The Mips RDHWR (Read Hardware Register) instruction was not 
tested for assembler or dissassembler consumption. This patch
adds that functionality.

Contributer: Vladimir Medic
 
llvm-svn: 172579
2013-01-16 00:07:45 +00:00
Jack Carter f238510c43 This patch fixes a Mips specific bug where
we need to generate a N64 compound relocation
R_MIPS_GPREL_32/R_MIPS_64/R_MIPS_NONE.

The bug was exposed by the SingleSourcetest case 
DuffsDevice.c.

Contributer: Jack Carter
llvm-svn: 172496
2013-01-15 01:08:02 +00:00
Dmitri Gribenko 2e1df0e354 Improve r172471: avoid all those extra casts on the lines nearby
llvm-svn: 172481
2013-01-14 22:08:37 +00:00
David Greene cf7ae6c2fd Fix Casting
Fix a casting-away-const compiler warning.

llvm-svn: 172471
2013-01-14 21:04:47 +00:00
NAKAMURA Takumi de45c3a485 MipsDisassembler.cpp: Prune DecodeHWRegs64RegisterClass() to suppress a warning. [-Wunused-function]
llvm-svn: 172319
2013-01-12 15:37:00 +00:00
NAKAMURA Takumi 956c123ab6 MipsAsmParser: Try to unbreak tests to add extra check.
llvm-svn: 172315
2013-01-12 15:19:10 +00:00
Jack Carter 873c724b4a This patch tackles the problem of parsing Mips
register names in the standalone assembler llvm-mc.

Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.


The problem is resolved by the Mips specific AsmParser 
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.


Contributer: Vladimir Medic
llvm-svn: 172284
2013-01-12 01:03:14 +00:00
Jack Carter c3dd91c4d7 This patch produces the correct addend value for
an R_MIPS_GPREL16 relocation.


Contributer: Jack Carter
llvm-svn: 171882
2013-01-08 19:01:28 +00:00
Jack Carter 9e28cd3fad This patch produces the correct pointer size
value in the 64 bit .eh_frame section.

It doesn't however allow exception handling to work
yet since it depends on the correct relocation model
being set in the ELF header flags.


Contributer: Jack Carter
llvm-svn: 171881
2013-01-08 18:53:20 +00:00
Eli Bendersky 4d9ada036c Renamed MCInstFragment to MCRelaxableFragment and added some comments.
No change in functionality.

llvm-svn: 171822
2013-01-08 00:22:56 +00:00
Jordan Rose e8f1eaea8a Change SMRange to be half-open (exclusive end) instead of closed (inclusive)
This is necessary not only for representing empty ranges, but for handling
multibyte characters in the input. (If the end pointer in a range refers to
a multibyte character, should it point to the beginning or the end of the
character in a char array?) Some of the code in the asm parsers was already
assuming this anyway.

llvm-svn: 171765
2013-01-07 19:00:49 +00:00
Craig Topper a8c5ec09c7 Remove # from the beginning and end of def names. The # is a paste operator and should only be used with something to paste on either side.
llvm-svn: 171697
2013-01-07 05:45:56 +00:00
Chandler Carruth 664e354de7 Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.

The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.

The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.

The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.

The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.

The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.

The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.

The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.

Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.

Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.

Commits to update DragonEgg and Clang will be made presently.

llvm-svn: 171681
2013-01-07 01:37:14 +00:00
Akira Hatanaka d35a263076 [mips] Fix data layout string. Add 64 to the list of native integer widths
and add stack alignment information.

llvm-svn: 171587
2013-01-05 02:00:56 +00:00
Akira Hatanaka b13b33359b [mips] MipsTargetLowering::getSetCCResultType should return a vector type if
vectors are being compared.

llvm-svn: 171517
2013-01-04 20:06:01 +00:00
Akira Hatanaka e067e5a13f [mips] 80 columns.
llvm-svn: 171515
2013-01-04 19:38:05 +00:00
Akira Hatanaka f412e7501a [mips] Reorder template parameters. Remove class shift_rotate_imm32 and
shift_rotate_imm64.

llvm-svn: 171513
2013-01-04 19:25:46 +00:00
Akira Hatanaka a7a9fa1c16 [mips] Refactor conditional move instructions.
llvm-svn: 171511
2013-01-04 19:16:38 +00:00
Akira Hatanaka e36e2f6876 [mips] Refactor instructions which move data from or to coprocessors.
llvm-svn: 171510
2013-01-04 19:13:49 +00:00
Chandler Carruth 9fb823bbd4 Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

llvm-svn: 171366
2013-01-02 11:36:10 +00:00
Chandler Carruth be81023d74 Resort the #include lines in include/... and lib/... with the
utils/sort_includes.py script.

Most of these are updating the new R600 target and fixing up a few
regressions that have creeped in since the last time I sorted the
includes.

llvm-svn: 171362
2013-01-02 10:22:59 +00:00
Akira Hatanaka 6ac2fc4976 [mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware
instructions.

llvm-svn: 170956
2012-12-21 23:21:32 +00:00
Akira Hatanaka beea8a34c3 [mips] Refactor SYNC and multiply/divide instructions.
llvm-svn: 170955
2012-12-21 23:17:36 +00:00
Akira Hatanaka 31ddec5887 [mips] Refactor BAL instructions.
llvm-svn: 170954
2012-12-21 23:15:59 +00:00
Akira Hatanaka d6b694f036 [mips] Fix encoding of BAL instruction. Also, fix assembler test case which
was not catching the error.

llvm-svn: 170953
2012-12-21 23:13:59 +00:00
Akira Hatanaka a158042a56 [mips] Refactor jump, jump register, jump-and-link and nop instructions.
llvm-svn: 170952
2012-12-21 23:03:50 +00:00
Akira Hatanaka e1826d7464 [mips] Refactor load/store left/right and load-link and store-conditional
instructions.

llvm-svn: 170950
2012-12-21 23:01:24 +00:00
Akira Hatanaka d9bf8424e5 [mips] Refactor load/store instructions.
llvm-svn: 170948
2012-12-21 22:58:55 +00:00
Akira Hatanaka b59b047fbe [mips] Remove unnecessary isPseudo parameter.
llvm-svn: 170947
2012-12-21 22:57:26 +00:00
Akira Hatanaka e738efc95b [mips] Refactor LUI instruction.
llvm-svn: 170944
2012-12-21 22:46:07 +00:00
Akira Hatanaka 895e1cb2aa [mips] Refactor count leading zero or one instructions.
llvm-svn: 170942
2012-12-21 22:43:58 +00:00
Akira Hatanaka 4f4c4aa05e [mips] Refactor sign-extension-in-register instructions.
llvm-svn: 170940
2012-12-21 22:41:52 +00:00
Akira Hatanaka b14c6e4e5f [mips] Refactor instructions which copy from and to HI/LO registers.
llvm-svn: 170939
2012-12-21 22:39:17 +00:00
Akira Hatanaka 9e89195dce [mips] Refactor logical NOR instructions.
llvm-svn: 170937
2012-12-21 22:35:47 +00:00
Akira Hatanaka ac10697207 [mips] Move instruction definitions in MipsInstrInfo.td.
llvm-svn: 170936
2012-12-21 22:33:43 +00:00
Reed Kotler 9bff1ead0e Call llvm_unreachable instead of assert.
llvm-svn: 170822
2012-12-21 00:44:59 +00:00
Reed Kotler d11acc7dc0 Implement cfi_def_cfa_offset. "Make check" test case for this comming in the
next few days but it's already tested a lot from test-suite and works fine.
This patch completes almost 100% pass of test-suite for mips 16.

llvm-svn: 170674
2012-12-20 06:59:37 +00:00
Reed Kotler 8965d24a2a There is one more patch to finish large frames. Make sure we assert
on code that has large frames which will not yet compile correctly.

llvm-svn: 170673
2012-12-20 06:57:00 +00:00
Reed Kotler 7bff8f1d7a set register class properly for mips16 here
llvm-svn: 170669
2012-12-20 06:06:35 +00:00
Reed Kotler 92fc33bc97 This assert is overly restrictive and does not work for mips16.
llvm-svn: 170667
2012-12-20 05:09:15 +00:00
Reed Kotler fd633229f7 Turn on register scavenger for Mips 16
We use an unused Mips 32 register for the emergency slot
instead of using the stack.

llvm-svn: 170665
2012-12-20 04:44:58 +00:00
Akira Hatanaka e7f1acc7c0 [mips] Refactor SLT (set on less than) instructions. Separate encoding
information from the rest. 

llvm-svn: 170664
2012-12-20 04:27:52 +00:00
Akira Hatanaka bbd197e9c4 [mips] Refactor unconditional branch instruction. Separate encoding information
from the rest. 

llvm-svn: 170663
2012-12-20 04:22:39 +00:00
Akira Hatanaka b1527b7505 [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass
parameter.

llvm-svn: 170661
2012-12-20 04:20:09 +00:00
Akira Hatanaka 14f9ce0f83 [mips] Delete definition of CPRESTORE instruction.
llvm-svn: 170660
2012-12-20 04:15:30 +00:00
Akira Hatanaka c0ea0bb99b [mips] Refactor conditional branch instructions with one register operand.
Separate encoding information from the rest.

llvm-svn: 170659
2012-12-20 04:13:23 +00:00
Akira Hatanaka f71ffd29d9 [mips] Refactor conditional branch instructions with two register operands.
Separate encoding information from the rest.

llvm-svn: 170657
2012-12-20 04:10:13 +00:00
Reed Kotler d019dbf75e fix most of remaining issues with large frames.
these patches are tested a lot by test-suite but
make check tests are forthcoming once the next
few patches that complete this are committed.
with the next few patches the pass rate for mips16 is
near 100%

llvm-svn: 170656
2012-12-20 04:07:42 +00:00
Akira Hatanaka f423672117 [mips] Use "or $r0, $r1, $zero" instead of "addu $r0, $zero, $r1" to copy
physical register $r1 to $r0.

GNU disassembler recognizes an "or" instruction as a "move", and this change
makes the disassembled code easier to read.

Original patch by Reed Kotler.

llvm-svn: 170655
2012-12-20 04:06:06 +00:00
Akira Hatanaka 7d75f9e3d3 [mips] Change the order of template parameters. Move the default parameters to
the end. 

llvm-svn: 170651
2012-12-20 03:52:08 +00:00
Akira Hatanaka 244f9e874c [mips] Refactor shift instructions with register operands. Separate encoding
information from the rest.

llvm-svn: 170650
2012-12-20 03:48:24 +00:00
Akira Hatanaka 7f96ad325f [mips] Refactor shift immediate instructions. Separate encoding information
from the rest.

llvm-svn: 170649
2012-12-20 03:44:41 +00:00
Akira Hatanaka ab1b715bf2 [mips] Refactor arithmetic and logic instructions with immediate operands.
Separate encoding information from the rest.

llvm-svn: 170648
2012-12-20 03:40:03 +00:00
Akira Hatanaka 1b37c4af01 [mips] Refactor arithmetic and logic instructions. Separate encoding
information from the rest.

llvm-svn: 170647
2012-12-20 03:34:05 +00:00
Akira Hatanaka 73495897b1 [mips] Delete ArithOverflowR and ArithOverflow and use ArithLogicR and
ArithLogicI as the instruction base classes.

llvm-svn: 170642
2012-12-20 03:00:16 +00:00
Roman Divacky e3d323052f Remove edis - the enhanced disassembler. Fixes PR14654.
llvm-svn: 170578
2012-12-19 19:55:47 +00:00
Reed Kotler 3aad762d1d Add some missing Defs and Uses.
llvm-svn: 170493
2012-12-19 04:06:15 +00:00
Reed Kotler aee4d5d194 This patch is needed to make c++ exceptions work for mips16.
Mips16 is really a processor decoding mode (ala thumb 1) and in the same
program, mips16 and mips32 functions can exist and can call each other.

If a jal type instruction encounters an address with the lower bit set, then
the processor switches to mips16 mode (if it is not already in it). If the
lower bit is not set, then it switches to mips32 mode.

The linker knows which functions are mips16 and which are mips32.
When relocation is performed on code labels, this lower order bit is
set if the code label is a mips16 code label.

In general this works just fine, however when creating exception handling
tables and dwarf, there are cases where you don't want this lower order
bit added in.

This has been traditionally distinguished in gas assembly source by using a
different syntax for the label.

lab1:      ; this will cause the lower order bit to be added
lab2=.     ; this will not cause the lower order bit to be added

In some cases, it does not matter because in dwarf and debug tables
the difference of two labels is used and in that case the lower order
bits subtract each other out.

To fix this, I have added to mcstreamer the notion of a debuglabel.
The default is for label and debug label to be the same. So calling
EmitLabel and EmitDebugLabel produce the same result.

For various reasons, there is only one set of labels that needs to be
modified for the mips exceptions to work. These are the "$eh_func_beginXXX" 
labels.

Mips overrides the debug label suffix from ":" to "=." .

This initial patch fixes exceptions. More changes most likely
will be needed to DwarfCFException to make all of this work
for actual debugging. These changes will be to emit debug labels in some
places where a simple label is emitted now.

Some historical discussion on this from gcc can be found at:
http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00623.html
http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01273.html 

llvm-svn: 170279
2012-12-16 04:00:45 +00:00
Reed Kotler 5fdeb21249 This code implements most of mips16 hardfloat as it is done by gcc.
In this case, essentially it is soft float with different library routines.
The next step will be to make this fully interoperational with mips32 floating
point and that requires creating stubs for functions with signatures that
contain floating point types.

I have a more sophisticated design for mips16 hardfloat which I hope to
implement at a later time that directly does floating point without the need
for function calls.

The mips16 encoding has no floating point instructions so one needs to
switch to mips32 mode to execute floating point instructions.

llvm-svn: 170259
2012-12-15 00:20:05 +00:00
Patrik Hagglund 5e6c361bc0 Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.

This is the first, in a series of patches.

This is the second attempt. In the first attempt (r169837), a few
getSimpleVT() were hoisted too far, detected by bootstrap failures.

llvm-svn: 170104
2012-12-13 06:34:11 +00:00
Akira Hatanaka cf9a61b6ee [mips] Do not copy GOT address to register $gp if the function being called has
internal linkage.

llvm-svn: 170092
2012-12-13 03:17:29 +00:00
Akira Hatanaka b2cc8a756f [mips] Delete all floating point instruction classes that are no longer used.
No functionality change.

llvm-svn: 170084
2012-12-13 02:05:02 +00:00
Akira Hatanaka 6262bbf819 [mips] Modify definitions of floating point conditional move instructions.
No functionality change.

llvm-svn: 170080
2012-12-13 01:41:15 +00:00
Akira Hatanaka 79e1cdb00b [mips] Modify definitions of floating point comparison instructions.
No functionality change.

llvm-svn: 170077
2012-12-13 01:34:09 +00:00
Akira Hatanaka fd9163b74c [mips] Modify definitions of floating point branch instructions.
No functionality change.

llvm-svn: 170076
2012-12-13 01:32:36 +00:00
Akira Hatanaka cd3dfd238e [mips] Modify definitions of floating point indexed load and store instructions.
No functionality change.

llvm-svn: 170075
2012-12-13 01:30:49 +00:00
Akira Hatanaka b0d4acbc65 [mips] Modify definitions of floating point multiply-add/sub instructions.
No functionality change.

llvm-svn: 170073
2012-12-13 01:27:48 +00:00
Akira Hatanaka 92994f4846 [mips] Modify definitions of floating point load and store instructions.
No functionality change.

llvm-svn: 170072
2012-12-13 01:24:00 +00:00
Akira Hatanaka 2b75dde5fa [mips] Modify definitions of move from/to coprocessor instructions.
No functionality change.

llvm-svn: 170071
2012-12-13 01:16:49 +00:00
Akira Hatanaka dea8f61ae0 [mips] Modify definitions of two register operand floating point instructions.
No functionality change.

llvm-svn: 170069
2012-12-13 01:14:07 +00:00
Akira Hatanaka 29b513871a [mips] Modify definitions of three register operand floating point instructions
and separate encoding information from the rest.

llvm-svn: 170066
2012-12-13 01:07:37 +00:00
Akira Hatanaka 84693d5606 [mips] Move classes that do not belong in MipsInstrFormats.td into
MipsInstrFPU.td.
 

llvm-svn: 170061
2012-12-13 00:49:23 +00:00
Akira Hatanaka db49b39200 [mips] Set isCommutable flag in a more explicit way.
llvm-svn: 170060
2012-12-13 00:46:23 +00:00
Akira Hatanaka 193e1f738a [mips] Remove fmt from the parameter list of classes FMADDSUB and FNMADDSUB.
llvm-svn: 170057
2012-12-13 00:38:59 +00:00
Akira Hatanaka caaf4dd516 [mips] Remove single-precision floating point instruction from multiclass
FFR2P_M.
 

llvm-svn: 170055
2012-12-13 00:35:54 +00:00
Akira Hatanaka 02ec5516f8 [mips] Move class IsCommutable into MipsInstrInfo.td.
llvm-svn: 170054
2012-12-13 00:32:01 +00:00
Akira Hatanaka e986a59ad9 [mips] Remove single-precision floating point instructions from multiclasses
FFR1_W_M and FFR1P_M. The new instruction definitions have one-to-one
correspondence with the instructions in the ISA manual.
 

llvm-svn: 170053
2012-12-13 00:29:29 +00:00
Akira Hatanaka 7bc144c366 [mips] Fix a memory leak bug report by NAKAMURA Takumi.
llvm-svn: 170012
2012-12-12 20:09:58 +00:00
Evan Cheng 962711ee71 Sorry about the churn. One more change to getOptimalMemOpType() hook. Did I
mention the inline memcpy / memset expansion code is a mess?

This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset.
The first indicates whether it is expanding a memset or a memcpy / memmove.
The later is whether the memset is a memset of zero. It's totally possible
(likely even) that targets may want to do different things for memcpy and
memset of zero.

llvm-svn: 169959
2012-12-12 02:34:41 +00:00
Evan Cheng c3d1aca657 - Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.
Also added more comments to explain why it is generally ok to return true.
- Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to
be true for loaded source (memcpy) or zero constants (memset). The poor name
choice is probably some kind of legacy issue.

llvm-svn: 169954
2012-12-12 01:32:07 +00:00
Patrik Hagglund e98b7a0389 Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
llvm-svn: 169854
2012-12-11 11:14:33 +00:00
Patrik Hagglund 3708e548f8 Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.

This is the first, in a series of patches.

llvm-svn: 169837
2012-12-11 09:10:33 +00:00
NAKAMURA Takumi 99feb75cb8 [CMake] Remove dependencies to intrinsics_gen I introduced in r169724.
llvm-svn: 169819
2012-12-11 05:53:54 +00:00
Evan Cheng 79e2ca90bc Some enhancements for memcpy / memset inline expansion.
1. Teach it to use overlapping unaligned load / store to copy / set the trailing
   bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies.
2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g.
   x86 and ARM.
3. When memcpy from a constant string, do *not* replace the load with a constant
   if it's not possible to materialize an integer immediate with a single
   instruction (required a new target hook: TLI.isIntImmLegal()).
4. Use unaligned load / stores more aggressively if target hooks indicates they
   are "fast".
5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8.
   Also increase the threshold to something reasonable (8 for memset, 4 pairs
   for memcpy).

This significantly improves Dhrystone, up to 50% on ARM iOS devices.

rdar://12760078

llvm-svn: 169791
2012-12-10 23:21:26 +00:00
Akira Hatanaka 5d6faed1f0 [mips] Set HWEncoding field of registers. Use delete function
getMipsRegisterNumbering and use MCRegisterInfo::getEncodingValue instead.

llvm-svn: 169760
2012-12-10 20:04:40 +00:00
NAKAMURA Takumi 6b819c5fb1 [CMake] Update dependencies to intrinsics_gen corresponding to r169711.
llvm-svn: 169724
2012-12-10 05:27:15 +00:00
Jakob Stoklund Olesen 97030e0c0e Use the new MIBundleBuilder class in the Mips target.
This is the preferred way of creating bundled machine instructions.

llvm-svn: 169585
2012-12-07 04:23:40 +00:00
Akira Hatanaka efdce0fb09 [mips] Delete nodes and instructions for dynamic alloca that are no longer in
use.

llvm-svn: 169580
2012-12-07 03:10:18 +00:00
Akira Hatanaka 97e179f9e4 [mips] Shorten predicate name.
llvm-svn: 169579
2012-12-07 03:06:09 +00:00
Akira Hatanaka c5dc055922 [mips] Delete unused sub-target features.
llvm-svn: 169578
2012-12-07 03:04:05 +00:00
Akira Hatanaka 02a346d11f [mips] Remove unnecessary predicates.
llvm-svn: 169577
2012-12-07 03:01:24 +00:00
Chandler Carruth 802d755533 Sort includes for all of the .h files under the 'lib' tree. These were
missed in the first pass because the script didn't yet handle include
guards.

Note that the script is now able to handle all of these headers without
manual edits. =]

llvm-svn: 169224
2012-12-04 07:12:27 +00:00
Akira Hatanaka 4c128509a5 Classic JIT is still being supported by MIPS, along with MCJIT.
This change adds endian-awareness to MipsJITInfo and emitWordLE in
MipsCodeEmitter has become emitWord now to support both endianness.

Patch by Petar Jovanovic.

llvm-svn: 169177
2012-12-03 23:11:12 +00:00
Akira Hatanaka 60c2837e8d Functions in MipsCodeEmitter.cpp that expand unaligned loads/stores are dead
code. Removing it.

Patch by Petar Jovanovic.

llvm-svn: 169174
2012-12-03 22:51:22 +00:00
Chandler Carruth ed0881b2a6 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131
2012-12-03 16:50:05 +00:00
Chandler Carruth f12e3a67db Switch LLVM_USE_RVALUE_REFERENCES to LLVM_HAS_RVALUE_REFERENCES.
Rationale:
1) This was the name in the comment block. ;]
2) It matches Clang's __has_feature naming convention.
3) It matches other compiler-feature-test conventions.

Sorry for the noise. =]

I've also switch the comment block to use a \brief tag and not duplicate
the name.

llvm-svn: 168996
2012-11-30 11:45:22 +00:00
Jack Carter b05cb67b81 Mips direct object xgot support
This patch provides support for the MIPS relocations:

    *)  R_MIPS_GOT_HI16
    *)  R_MIPS_GOT_LO16
    *)  R_MIPS_CALL_HI16
    *)  R_MIPS_CALL_LO16

These are used for large GOT instruction sequences.

Contributer: Jack Carter
llvm-svn: 168471
2012-11-21 23:38:59 +00:00
Akira Hatanaka bb6e74a2f1 [mips] Generate big GOT code.
llvm-svn: 168460
2012-11-21 20:40:38 +00:00
Akira Hatanaka 56d5f1bca5 [mips] Simplify lowering functions in MipsISelLowering.cpp by using the helper
functions added in r168456.

llvm-svn: 168458
2012-11-21 20:30:40 +00:00
Akira Hatanaka fd04ad4261 [mips] Add helper functions that create nodes for computing address.
llvm-svn: 168456
2012-11-21 20:26:38 +00:00
Akira Hatanaka 59f299f28e [mips] Add command line option "-mxgot".
llvm-svn: 168455
2012-11-21 20:21:11 +00:00
Akira Hatanaka dbe41ad18c [mips] When a node which loads from a GOT is created, pass a MachinePointerInfo
referring to a GOT entry.

llvm-svn: 168453
2012-11-21 20:16:34 +00:00
Akira Hatanaka 03fb5b96fc [mips] Add target operand flag enums for big GOT relocations.
llvm-svn: 168450
2012-11-21 19:59:51 +00:00
Akira Hatanaka ef83919b4c Initial implementation of MipsTargetLowering::isLegalAddressingMode.
llvm-svn: 168230
2012-11-17 00:25:41 +00:00
Akira Hatanaka 907f5f0ca7 [mips] Fix delay slot filler so that instructions with register operand $1 are
allowed in branch delay slot.

llvm-svn: 168131
2012-11-16 02:39:34 +00:00
Akira Hatanaka 3bc1beb696 [mips] Add predicate HasFPIdx for floating-point indexed load instruction
support and use it in place of HasMips32r2Or64.

llvm-svn: 168089
2012-11-15 21:17:13 +00:00
Akira Hatanaka 5fdeac3268 Add assertions in MipsLongBranch which check the size of basic blocks.
llvm-svn: 168078
2012-11-15 20:05:11 +00:00
Akira Hatanaka 28e02ec8c1 [mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node.
Patch by Sasa Stankovic.

llvm-svn: 167548
2012-11-07 19:10:58 +00:00
Akira Hatanaka 40f2d30987 Delete MipsFunctionInfo::NextStackOffset. No functionality change intended.
llvm-svn: 167546
2012-11-07 19:04:26 +00:00
Akira Hatanaka da1980f697 [mips] Set flag neverHasSideEffects flag on floating point conversion
instructions.

llvm-svn: 167348
2012-11-03 00:53:12 +00:00
Akira Hatanaka 7828331329 [mips] Set flag isAsCheapAsAMove flag on instruction LUi.
llvm-svn: 167345
2012-11-03 00:26:02 +00:00
Akira Hatanaka 5852e3b800 [mips] Stop reserving register AT and use register scavenger when a scratch
register is needed.

llvm-svn: 167341
2012-11-03 00:05:43 +00:00
Akira Hatanaka 654e3b40f5 [mips] Do not reserve all 64-bit registers, but only the ones which need to be
reserved. Without this fix, RegScavenger::getRegsAvailable incorrectly
returns an empty set of integer registers.

llvm-svn: 167335
2012-11-02 23:36:01 +00:00
Akira Hatanaka 949f8d890d [mips] Use register number instead of name to print register $AT.
llvm-svn: 167315
2012-11-02 21:26:03 +00:00
Akira Hatanaka 97b43d8bdf [mips] Add function MipsFrameLowering::estimateStackSize.
This function estimates stack size and will be called before
PrologEpilogInserter scans the callee-saved registers.

llvm-svn: 167313
2012-11-02 21:10:22 +00:00
Akira Hatanaka 719df2874c [mips] Add member field MipsFunctionInfo::IncomingArgSize which holds the size
of the incoming argument area.

llvm-svn: 167312
2012-11-02 21:03:58 +00:00
Akira Hatanaka 0dfbf1262b [mips] Delete MipsFunctionInfo::EmitNOAT. Unconditionally print directive
"set .noat" so that the assembler doesn't issue warnings when register $AT is
used.

llvm-svn: 167310
2012-11-02 20:56:25 +00:00
Akira Hatanaka 4f5ef21869 [mips] Set isAsCheapAsAMove flag on ADDiu and DADDiu, which enables
re-materialization of immediate loads.

llvm-svn: 167153
2012-10-31 18:37:55 +00:00
Reed Kotler 27a7229c47 Implement ADJCALLSTACKUP and ADJCALLSTACKDOWN
llvm-svn: 167107
2012-10-31 05:21:10 +00:00
Akira Hatanaka 9c962c02e4 [mips] Allow tail-call optimization for vararg functions and functions which
use the caller's stack.

llvm-svn: 167048
2012-10-30 20:16:31 +00:00
Akira Hatanaka 4866fe14e2 Add code for saving formal argument information to MipsFunctionInfo. This
information will be used by IsEligibleForTailCallOptimization to determine
whether a call can be tail-call optimized.

llvm-svn: 167043
2012-10-30 19:37:25 +00:00
Akira Hatanaka 6233cf565f Add definition of function MipsTargetLowering::passArgOnStack which emits nodes
for passing a function call argument on a stack.

llvm-svn: 167041
2012-10-30 19:23:25 +00:00
Akira Hatanaka 8e50aba5f9 Do not do tail-call optimization if target is mips16.
llvm-svn: 167039
2012-10-30 19:07:58 +00:00
Reed Kotler a811753716 Change mips16 delay slot jumps to non delay slot forms by default.
We will make them delay slot forms if there is something that can be
placed in the delay slot during a separate pass. Mips16 extended instructions
cannot be placed in delay slots.

llvm-svn: 166990
2012-10-30 00:54:49 +00:00
Reed Kotler 740981e35c Implement patterns for extloadi8 and extloadi16
llvm-svn: 166960
2012-10-29 19:39:04 +00:00
Reed Kotler aebb8b034c Expand all atomic ops for mips16.
llvm-svn: 166935
2012-10-29 16:16:54 +00:00
Reed Kotler e6c31579be Implement brind operator for mips16.
llvm-svn: 166903
2012-10-28 23:08:07 +00:00
Rafael Espindola d957cb2584 Remove TargetELFWriterInfo.
All the credit goes to Jan Voung for noticing it was dead!

llvm-svn: 166902
2012-10-28 21:34:43 +00:00
Reed Kotler 3589dd74ac This patch is for the implementation of mips16 complex pattern addr16.
Previously mips16 was sharing the pattern addr which is used for mips32
and mips64. This had a number of problems:
1) Storing and loading byte and halfword quantities for mips16 has particular
problems due to the primarily non mips16 nature of SP. When we must
load/store byte/halfword stack objects in a function, we must create a mips16
alias register for SP. This functionality is tested in stchar.ll.
2) We need to have an FP register under certain conditions (such as 
dynamically sized alloca). We use mips16 register S0 for this purpose.
In this case, we also use this register when accessing frame objects so this
issue also affects the complex pattern addr16. This functionality is
tested in alloca16.ll.

The Mips16InstrInfo.td has been updated to use addr16 instead of addr.

The complex pattern C++ function for addr has been copied to addr16 and
updated to reflect the above issues.

llvm-svn: 166897
2012-10-28 06:02:37 +00:00
Reed Kotler 7e4d9969cb Implement MipsHi for mips16
llvm-svn: 166852
2012-10-27 00:57:14 +00:00
Akira Hatanaka 6a124a84dc [mips] Do not tail-call optimize vararg functions or functions with byval
arguments.

This is rather conservative and should be fixed later to be more aggressive.

llvm-svn: 166851
2012-10-27 00:56:56 +00:00
Akira Hatanaka 2c07f1f140 [mips] Make sure FuncArg doesn't advance when OrigArgIndex is the same as in the
previous iteration.

llvm-svn: 166850
2012-10-27 00:44:39 +00:00
Akira Hatanaka ac8c669985 Use the methods and classes that were added to simplify LowerCall and
LowerFormalArguments in MipsTargetLowering.

No functionality change intended.

llvm-svn: 166846
2012-10-27 00:29:43 +00:00
Akira Hatanaka 2a13402a66 Add method MipsTargetLowering::writeVarArgRegs which copies argument registers
of vararg functions back to the stack.

llvm-svn: 166844
2012-10-27 00:21:13 +00:00
Akira Hatanaka 35f55b1622 Add method MipsTargetLowering::passByValArg.
This method emits nodes for passing byval arguments in registers and stack.
This has the same functionality as existing functions PassByValArg64 and
WriteByValArg which will be deleted later.

llvm-svn: 166843
2012-10-27 00:16:36 +00:00
Akira Hatanaka 25dad19f0e Add method MipsTargetLowering::copyByValRegs.
This method copies byval arguments passed in registers onto the stack and has
the same functionality as existing functions CopyMips64ByValRegs and
ReadByValArg which will be deleted later.

llvm-svn: 166841
2012-10-27 00:10:18 +00:00
Akira Hatanaka 4a3711d077 Add class MipsCC which provides methods used to analyze formal and call
arguments and inquire about calling convention information.

llvm-svn: 166840
2012-10-26 23:56:38 +00:00
Akira Hatanaka e485c65642 Delete MipsFunctionInfo::InArgFIRange.
llvm-svn: 166837
2012-10-26 23:49:51 +00:00
Reed Kotler b650f6bbe7 implement mips16 tls global addr
llvm-svn: 166827
2012-10-26 22:57:32 +00:00
Reed Kotler 4e1c629567 (no commit message)
llvm-svn: 166780
2012-10-26 16:18:19 +00:00
Reed Kotler 287f0449a2 Implement carry for subtract/add for mips16
llvm-svn: 166755
2012-10-26 04:46:26 +00:00
Reed Kotler e47873ab89 implement large (>16 bit) constant loading.
llvm-svn: 166749
2012-10-26 03:09:34 +00:00
Reed Kotler 097556d6bd implement mips16 patterns for select nodes
llvm-svn: 166721
2012-10-25 21:33:30 +00:00
Chad Rosier f0e8720054 [ms-inline asm] Add support for creating AsmRewrites in the target specific
AsmParser logic.  To be used/tested in a subsequent commit.

llvm-svn: 166714
2012-10-25 20:41:34 +00:00
Nadav Rotem 2289f2c932 Implement a basic VectorTargetTransformInfo interface to be used by the loop and bb vectorizers for modeling the cost of instructions.
llvm-svn: 166593
2012-10-24 17:22:41 +00:00