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Author SHA1 Message Date
Pablo Barrio e28cb8399a [ARM] Allow 64- and 128-bit types with 't' inline asm constraint 
Summary:
In LLVM, 't' selects a floating-point/SIMD register and only supports
32-bit values. This is appropriately documented in the LLVM Language
Reference Manual. However, this behaviour diverges from that of GCC, where
't' selects the s0-s31 registers and its qX and dX variants depending on
additional operand modifiers (q/P).

For example, the following C code:

#include <arm_neon.h>
float32x4_t a, b, x;
asm("vadd.f32 %0, %1, %2" : "=t" (x) : "t" (a), "t" (b))

results in the following assembly if compiled with GCC:

vadd.f32 s0, s0, s1

whereas LLVM will show "error: couldn't allocate output register for
constraint 't'", since a, b, x are 128-bit variables, not 32-bit.

This patch extends the use of 't' to mean that of GCC, thus allowing
selection of the lower Q vector regs and their D/S variants. For example,
the earlier code will now compile as:

vadd.f32 q0, q0, q1

This behaviour still differs from that of GCC but I think it is actually
more correct, since LLVM picks up the right register type based on the
datatype of x, while GCC would need an extra operand modifier to achieve
the same result, as follows:

asm("vadd.f32 %q0, %q1, %q2" : "=t" (x) : "t" (a), "t" (b))

Since this is only an extension of functionality, existing code should not
be affected by this change. Note that operand modifiers q/P are already
supported by LLVM, so this patch should suffice to support inline
assembly with constraint 't' originally built for GCC.

Reviewers: grosbach, rengolin

Reviewed By: rengolin

Subscribers: rogfer01, efriedma, olista01, aemerson, javed.absar, eraman, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D42962

llvm-svn: 325244
 2018-02-15 14:44:22 +00:00
Elena Demikhovsky 945b7e5aa6 Adding a width of the GEP index to the Data Layout. 
Making a width of GEP Index, which is used for address calculation, to be one of the pointer properties in the Data Layout.
p[address space]:size:memory_size:alignment:pref_alignment:index_size_in_bits.
The index size parameter is optional, if not specified, it is equal to the pointer size.

Till now, the InstCombiner normalized GEPs and extended the Index operand to the pointer width.
It works fine if you can convert pointer to integer for address calculation and all registered targets do this.
But some ISAs have very restricted instruction set for the pointer calculation. During discussions were desided to retrieve information for GEP index from the Data Layout.
http://lists.llvm.org/pipermail/llvm-dev/2018-January/120416.html

I added an interface to the Data Layout and I changed the InstCombiner and some other passes to take the Index width into account.
This change does not affect any in-tree target. I added tests to cover data layouts with explicitly specified index size.

Differential Revision: https://reviews.llvm.org/D42123

llvm-svn: 325102
 2018-02-14 06:58:08 +00:00
Yaxun Liu 0124b5484c [AMDGPU] Change constant addr space to 4 
Differential Revision: https://reviews.llvm.org/D43170

llvm-svn: 325030
 2018-02-13 18:00:25 +00:00
Matt Arsenault 923712b6b5 Reapply "AMDGPU: Add 32-bit constant address space" 
This reverts r324494 and reapplies r324487.

llvm-svn: 324747
 2018-02-09 16:57:57 +00:00
Yaxun Liu 976f317f0c [AMDGPU] Updae documentation about address space 
llvm-svn: 324617
 2018-02-08 15:41:19 +00:00
Jonas Devlieghere d4034d24da Re-land [dsymutil] Upstream update feature 
This commit attempts to re-land the r324480 which was reverted in
r324493 because it broke the Windows bots. For now I disabled the two
update tests on Windows until I'm able to debug this.

Differential revision: https://reviews.llvm.org/D42880

llvm-svn: 324592
 2018-02-08 10:48:54 +00:00
Rafael Espindola f4e3f3e31c Revert "AMDGPU: Add 32-bit constant address space" 
This reverts commit r324487.

It broke clang tests.

llvm-svn: 324494
 2018-02-07 18:09:35 +00:00
Jonas Devlieghere 36df7631b4 Revert dsymutil -update commits 
Revert "[dsymutil][test] Check the updated dSYM instead of companion file."
Revert "[dsymutil] Upstream update feature."

llvm-svn: 324493
 2018-02-07 17:35:27 +00:00
Marek Olsak 871c30e540 AMDGPU: Add 32-bit constant address space 
Note: This is a candidate for LLVM 6.0, because it was planned to be
      in that release but was delayed due to a long review period.

Merge conflict in release_60 - resolution:
    Add "-p6:32:32" into the second (non-amdgiz) string.

Only scalar loads support 32-bit pointers. An address in a VGPR will
fail to compile. That's OK because the results of loads will only be used
in places where VGPRs are forbidden.

Updated AMDGPUAliasAnalysis and used SReg_64_XEXEC.
The tests cover all uses cases we need for Mesa.

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D41651

llvm-svn: 324487
 2018-02-07 16:01:00 +00:00
Jonas Devlieghere a4b9417b52 [dsymutil] Upstream update feature. 
Now that dsymutil can generate accelerator tables, we can upstream the
update logic that, as the name implies, updates the accelerator tables
in an existing dSYM bundle. In combination with `-minimize` this can be
used to remove redundant .debug_(inlines|pubtypes|pubnames).

Differential revision: https://reviews.llvm.org/D42880

llvm-svn: 324480
 2018-02-07 13:51:29 +00:00
Lang Hames f3fb98365d [docs] Add out-of-date warnings to the BuildingAJIT tutorial text. 
The text will be updated once the ORC API churn dies down.

llvm-svn: 324406
 2018-02-06 21:25:20 +00:00
Daniel Neilson 01fb57e7a0 Add release note on change to memcpy/memmove/memset builtin signatures 
Summary:
The signatures for the builtins @llvm.memcpy, @llvm.memmove, and @llvm.memset
where changed in rL322965. The number of arguments has decreased from five to
four with the removal of the alignment argument. Alignment is now conveyed
by supplying the align parameter attribute on the destination and/or source of
the cpy/move/set.

llvm-svn: 324265
 2018-02-05 19:39:38 +00:00
David Blaikie 47ff8f457f Coding Standards: Document library layering requirements & header isolation. 
(I suppose these two pieces could be separated - but seemed related
enough)

As discussed on llvm-dev, this documents the general expectation of how
library layering should be handled. There are a few existing cases where
these constraints are not met, but as with most style guide things -
this is forward looking and provides guidance when cleaning up existing
code, it doesn't immediately require that all previous code be cleaned
up to match. (see: naming conventions, etc)

Differential Revision: https://reviews.llvm.org/D42771

llvm-svn: 324004
 2018-02-01 21:03:35 +00:00
Saleem Abdulrasool 0443499b89 docs: wordsmith some of the linker option extension 
Apply the grammatical improvements suggested by Rafael Avila de
Espindola in post-commit review.

llvm-svn: 323839
 2018-01-31 00:16:23 +00:00
Tony Tye db6c993faf [AMDGPU] Update relocation documentation and elf flag machine architecture numbers 
Differential Revision: https://reviews.llvm.org/D42714

llvm-svn: 323835
 2018-01-30 23:59:43 +00:00
Rui Ueyama 79755dca63 Rename path libpath in .linker-options. 
"path" is too generic name for -L or --library-path because a lot of
linker options take paths as arguments. This change renames the option
to avoid confusion.

Differential Revision: https://reviews.llvm.org/D42705

llvm-svn: 323833
 2018-01-30 23:49:27 +00:00
Tony Tye e039d0ee12 [AMDGPU] Clarify ReqdWorkGroupSize and MaxFlatWorkGroupSize metadata 
- If ReqdWorkGroupSize is present it must have all elements >=1.
- If MaxFlatWorkGroupSize must be consistent with ReqdWorkGroupSize.
- Remove FixedWorkGroupSize as now equivalent to ReqdWorkGroupSize.

llvm-svn: 323829
 2018-01-30 23:07:10 +00:00
Jonas Devlieghere cca341bb4e [dsymutil] Enable -minimize feature. 
Passing -minimize to dsymutil prevents the emission of .debug_inlines,
.debug_pubnames, and .debug_pubtypes in favor of the Apple accelerator
tables.

The actual check in the DWARF linker was added in r323655. This patch
simply enables it.

Differential revision: https://reviews.llvm.org/D42688

llvm-svn: 323812
 2018-01-30 19:54:16 +00:00
Saleem Abdulrasool b36fbbc3ec CodeGen: support an extension to pass linker options on ELF 
Introduce an extension to support passing linker options to the linker.
These would be ignored by older linkers, but newer linkers which support
this feature would be able to process the linker.

Emit a special discarded section `.linker-option`.  The content of this
section is a pair of strings (key, value).  The key is a type identifier for
the parameter.  This allows for an argument free parameter that will be
processed by the linker with the value being the parameter.  As an example,
`lib` identifies a library to be linked against, traditionally the `-l`
argument for Unix-based linkers with the parameter being the library name.

Thanks to James Henderson, Cary Coutant, Rafael Espinolda, Sean Silva
for the valuable discussion on the design of this feature.

llvm-svn: 323783
 2018-01-30 16:29:29 +00:00
Hiroshi Inoue c8e9245816 [NFC] fix trivial typos in comments and documents 
"to to" -> "to"

llvm-svn: 323628
 2018-01-29 05:17:03 +00:00
Vedant Kumar 51ce668d12 [LangRef] Update out-of-date instrprof names 
llvm-svn: 323575
 2018-01-26 23:54:25 +00:00
Matt Davis b6616ae662 [NFC] Remove apostrophe to use 'it' in the possessive form. 
Summary: This is  a simple change to test commit access with.

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D42586

llvm-svn: 323544
 2018-01-26 18:43:57 +00:00
Hiroshi Inoue 0909ca132f [NFC] fix trivial typos in comments and documents 
"in in" -> "in", "on on" -> "on" etc.

llvm-svn: 323508
 2018-01-26 08:15:29 +00:00
Amjad Aboud f1f57a3137 Another try to commit 323321 (aggressive instruction combine). 
llvm-svn: 323416
 2018-01-25 12:06:32 +00:00
Paul Robinson 052f14ef5a Fix up and document controlling ccache via CMake options. 
Patch by Matthew Davis!

Differential Revision: https://reviews.llvm.org/D41757

llvm-svn: 323357
 2018-01-24 18:15:08 +00:00
Amjad Aboud d53504e379 Reverted 323321. 
llvm-svn: 323326
 2018-01-24 14:48:49 +00:00
Amjad Aboud e4453233d7 [InstCombine] Introducing Aggressive Instruction Combine pass (-aggressive-instcombine). 
Combine expression patterns to form expressions with fewer, simple instructions.
This pass does not modify the CFG.

For example, this pass reduce width of expressions post-dominated by TruncInst
into smaller width when applicable.

It differs from instcombine pass in that it contains pattern optimization that
requires higher complexity than the O(1), thus, it should run fewer times than
instcombine pass.

Differential Revision: https://reviews.llvm.org/D38313

llvm-svn: 323321
 2018-01-24 12:42:42 +00:00
Sander de Smalen 1cb9431e69 Fixes Sphinx issue ('undefined label') introduced in r323313. 
(and also slightly reformatted the related lines to look better in
the rendered HTML)

llvm-svn: 323317
 2018-01-24 10:30:23 +00:00
Sander de Smalen fdf40917d9 [Metadata] Extend 'count' field of DISubrange to take a metadata node 
Summary:
This patch extends the DISubrange 'count' field to take either a
(signed) constant integer value or a reference to a DILocalVariable
or DIGlobalVariable.

This is patch [1/3] in a series to extend LLVM's DISubrange Metadata
node to support debugging of C99 variable length arrays and vectors with
runtime length like the Scalable Vector Extension for AArch64. It is
also a first step towards representing more complex cases like arrays
in Fortran.

Reviewers: echristo, pcc, aprantl, dexonsmith, clayborg, kristof.beyls, dblaikie

Reviewed By: aprantl

Subscribers: rnk, probinson, fhahn, aemerson, rengolin, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D41695

llvm-svn: 323313
 2018-01-24 09:56:07 +00:00
David Chisnall 83a561584d [Doc] Guideline on adding exception handling support for a target 
Summary:
This is the first attempt to write down a guideline on adding exception handling support for a target. The content basically bases on the discussion on [1]. If you guys know who is exception handling expert, please add him as the reviewer. Thanks.

[1] http://lists.llvm.org/pipermail/llvm-dev/2018-January/120405.html

Reviewers: t.p.northover, theraven, nemanjai

Reviewed By: theraven

Subscribers: sdardis, llvm-commits

Differential Revision: https://reviews.llvm.org/D42178

llvm-svn: 323311
 2018-01-24 09:53:01 +00:00
Vedant Kumar a9ae2fe782 docs: Remove reference to a deprecated flag 
llvm-svn: 323254
 2018-01-23 20:22:37 +00:00
Daniel Neilson aac0f8f399 Additional fixes for docs in addition to r322968. 
llvm-svn: 322969
 2018-01-19 17:32:33 +00:00
Daniel Neilson 39eb6a50ad Fix docs build break caused by r322965 
llvm-svn: 322968
 2018-01-19 17:24:21 +00:00
Daniel Neilson 1e68724d24 Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 
Summary:
 This is a resurrection of work first proposed and discussed in Aug 2015:
   http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
and initially landed (but then backed out) in Nov 2015:
   http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html

 The @llvm.memcpy/memmove/memset intrinsics currently have an explicit argument
which is required to be a constant integer. It represents the alignment of the
dest (and source), and so must be the minimum of the actual alignment of the
two.

 This change is the first in a series that allows source and dest to each
have their own alignments by using the alignment attribute on their arguments.

 In this change we:
1) Remove the alignment argument.
2) Add alignment attributes to the source & dest arguments. We, temporarily,
   require that the alignments for source & dest be equal.

 For example, code which used to read:
  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 100, i32 4, i1 false)
will now read
  call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %dest, i8* align 4 %src, i32 100, i1 false)

 Downstream users may have to update their lit tests that check for
@llvm.memcpy/memmove/memset call/declaration patterns. The following extended sed script
may help with updating the majority of your tests, but it does not catch all possible
patterns so some manual checking and updating will be required.

s~declare void @llvm\.mem(set|cpy|move)\.p([^(]*)\((.*), i32, i1\)~declare void @llvm.mem\1.p\2(\3, i1)~g
s~call void @llvm\.memset\.p([^(]*)i8\(i8([^*]*)\* (.*), i8 (.*), i8 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i8(i8\2* \3, i8 \4, i8 \5, i1 \6)~g
s~call void @llvm\.memset\.p([^(]*)i16\(i8([^*]*)\* (.*), i8 (.*), i16 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i16(i8\2* \3, i8 \4, i16 \5, i1 \6)~g
s~call void @llvm\.memset\.p([^(]*)i32\(i8([^*]*)\* (.*), i8 (.*), i32 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i32(i8\2* \3, i8 \4, i32 \5, i1 \6)~g
s~call void @llvm\.memset\.p([^(]*)i64\(i8([^*]*)\* (.*), i8 (.*), i64 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i64(i8\2* \3, i8 \4, i64 \5, i1 \6)~g
s~call void @llvm\.memset\.p([^(]*)i128\(i8([^*]*)\* (.*), i8 (.*), i128 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i128(i8\2* \3, i8 \4, i128 \5, i1 \6)~g
s~call void @llvm\.memset\.p([^(]*)i8\(i8([^*]*)\* (.*), i8 (.*), i8 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i8(i8\2* align \6 \3, i8 \4, i8 \5, i1 \7)~g
s~call void @llvm\.memset\.p([^(]*)i16\(i8([^*]*)\* (.*), i8 (.*), i16 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i16(i8\2* align \6 \3, i8 \4, i16 \5, i1 \7)~g
s~call void @llvm\.memset\.p([^(]*)i32\(i8([^*]*)\* (.*), i8 (.*), i32 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i32(i8\2* align \6 \3, i8 \4, i32 \5, i1 \7)~g
s~call void @llvm\.memset\.p([^(]*)i64\(i8([^*]*)\* (.*), i8 (.*), i64 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i64(i8\2* align \6 \3, i8 \4, i64 \5, i1 \7)~g
s~call void @llvm\.memset\.p([^(]*)i128\(i8([^*]*)\* (.*), i8 (.*), i128 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i128(i8\2* align \6 \3, i8 \4, i128 \5, i1 \7)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i8\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i8 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i8(i8\3* \4, i8\5* \6, i8 \7, i1 \8)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i16\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i16 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i16(i8\3* \4, i8\5* \6, i16 \7, i1 \8)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i32\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i32 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i32(i8\3* \4, i8\5* \6, i32 \7, i1 \8)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i64\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i64 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i64(i8\3* \4, i8\5* \6, i64 \7, i1 \8)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i128\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i128 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i128(i8\3* \4, i8\5* \6, i128 \7, i1 \8)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i8\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i8 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i8(i8\3* align \8 \4, i8\5* align \8 \6, i8 \7, i1 \9)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i16\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i16 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i16(i8\3* align \8 \4, i8\5* align \8 \6, i16 \7, i1 \9)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i32\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i32 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i32(i8\3* align \8 \4, i8\5* align \8 \6, i32 \7, i1 \9)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i64\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i64 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i64(i8\3* align \8 \4, i8\5* align \8 \6, i64 \7, i1 \9)~g
s~call void @llvm\.mem(cpy|move)\.p([^(]*)i128\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i128 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i128(i8\3* align \8 \4, i8\5* align \8 \6, i128 \7, i1 \9)~g

 The remaining changes in the series will:
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
   source and dest alignments.
Step 3) Update Clang to use the new IRBuilder API.
Step 4) Update Polly to use the new IRBuilder API.
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
        and those that use use MemIntrinsicInst::[get|set]Alignment() to use
        getDestAlignment() and getSourceAlignment() instead.
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
        MemIntrinsicInst::[get|set]Alignment() methods.

Reviewers: pete, hfinkel, lhames, reames, bollu

Reviewed By: reames

Subscribers: niosHD, reames, jholewinski, qcolombet, jfb, sanjoy, arsenm, dschuff, dylanmckay, mehdi_amini, sdardis, nemanjai, david2050, nhaehnle, javed.absar, sbc100, jgravelle-google, eraman, aheejin, kbarton, JDevlieghere, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, llvm-commits

Differential Revision: https://reviews.llvm.org/D41675

llvm-svn: 322965
 2018-01-19 17:13:12 +00:00
Joel Jones 57c22698f5 [docs] Make ReleaseProcess.rst 80 column. NFCI 
llvm-svn: 322849
 2018-01-18 14:57:55 +00:00
Florian Hahn edae5a6e11 [LangRef] Clarify Varargs forwarding for musttail calls. 
This clarification was suggested by @efriedma in D41335, which uses this
behavior to inline musttail calls with varargs.

Reviewers: hfinkel, efriedma, rnk

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D41861

llvm-svn: 322786
 2018-01-17 23:29:25 +00:00
Sean Eveson 2ae6037dd1 [MC] Fix -stack-size-section on ARM 
Change symbol values in the stack_size section from being 8 bytes, to being a target dependent size.

Differential Revision: https://reviews.llvm.org/D42108

llvm-svn: 322619
 2018-01-17 09:01:29 +00:00
Hiroshi Inoue 760c0c9ed3 [NFC] fix trivial typos in documents 
"the the" -> "the"

llvm-svn: 322552
 2018-01-16 13:19:48 +00:00
Brian Gesiak 17dfa193a5 [docs] Only LLVM IR bitstreams begin with 'BC' 
Summary:
The LLVM Bitcode File Format documentation states that all bitstreams
begin with the magic number 'BC', and that generic bitstream analyzer
tools may check for this number in order to determine whether the
stream is a bitstream.

However, in practice:

* Only LLVM IR bitcode begins with 'BC'. Other bitstreams -- Clang
  AST files and precompiled headers, Clang serialized diagnostics,
  Swift modules -- do not start with 'BC'. A tool that actually checked
  for 'BC' would only be able to recognize LLVM IR.
* The `llvm-bcanalyzer`, arguably the most used generic bitstream
  analyzer tool, does not check for a magic number 'BC' (except to
  determine whether the file is LLVM IR).

Update the bitcode format documentation to make it clear that not all
bitstreams begin with 'BC', and that tools should not rely on that
particular magic number value.

Test Plan:
Build the `docs-llvm-html` target and confirm the changes render in
a Safari web browser.

Reviewers: harlanhaskins, eugenis, mehdi_amini, pcc, angerman

Reviewed By: angerman

Subscribers: angerman, llvm-commits

Differential Revision: https://reviews.llvm.org/D42002

llvm-svn: 322520
 2018-01-15 21:23:32 +00:00
Jan Korous 8a3735c006 [docs] Fix mention of GCC frontend 
llvm-svn: 322491
 2018-01-15 17:11:22 +00:00
Zachary Turner 89d0889bf4 Update MSF File Documentation. 
This adds some more detail about the PDB container format,
specifically surrounding the layout of the Free Page Map.

Patch by Colden Cullen
Differential Revision: https://reviews.llvm.org/D41825

llvm-svn: 322404
 2018-01-12 21:42:39 +00:00
Ben Hamilton e0d2f7678d [docs] Tweak update to Phabricator docs about setting repository for diffs uploaded via web 
Summary:
In D41919, I missed that there was a *second* step when uploading
diffs via web where the repository should be specified.

Reviewers: asb, probinson

Reviewed By: asb

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41956

llvm-svn: 322375
 2018-01-12 15:44:35 +00:00
Ben Hamilton 9bcc957a29 [docs] Update Phabricator docs about setting repository for diffs uploaded via web 
Summary:
Docs are out of date now that we have separate repositories for LLVM,
Clang, etc.

Reviewers: asb

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D41919

llvm-svn: 322290
 2018-01-11 16:30:08 +00:00
Francis Visoiu Mistrih 5836790955 [MIR] Update MIRLangRef with documentation on bundled instructions 
Differential Revision: https://reviews.llvm.org/D41872

llvm-svn: 322198
 2018-01-10 17:53:16 +00:00
Sam Clegg ea7caceedc [WebAssembly] Add COMDAT support 
This adds COMDAT support to the Wasm object-file format.
Spec: https://github.com/WebAssembly/tool-conventions/pull/31

Corresponding LLD change:
https://bugs.llvm.org/show_bug.cgi?id=35533, and D40845

Patch by Nicholas Wilson

Differential Revision: https://reviews.llvm.org/D40844

llvm-svn: 322135
 2018-01-09 23:43:14 +00:00
Francis Visoiu Mistrih dbf2c48fc7 [MIR] Add support for the frame-destroy MachineInstr flag 
We are printing / parsing the `frame-setup` MachineInstr flag but not
the `frame-destroy` one.

Differential Revision: https://reviews.llvm.org/D41509

llvm-svn: 322071
 2018-01-09 11:33:22 +00:00
Tim Hammerquist 91078c4c39 remove unreferenced footnotes 
llvm-svn: 321840
 2018-01-05 00:24:55 +00:00
Tim Hammerquist 680671eb26 fix invalid footnote syntax 
llvm-svn: 321839
 2018-01-05 00:24:54 +00:00
Max Moroz 1ef3a778ac [llvm-cov] Refactor "export" command implementation and add support for SOURCES. 
Summary: Define an interface for Exporter + split JSON exporter into .h and .cpp.

Reviewers: vsk, morehouse

Reviewed By: vsk

Subscribers: llvm-commits, Dor1s, kcc

Differential Revision: https://reviews.llvm.org/D41600

llvm-svn: 321815
 2018-01-04 19:33:29 +00:00
Kostya Kortchinsky b84053291f [docs] Update Scudo documentation 
Summary:
The documentation has fallen a bit behind, update it with the latest evolution
of the allocator:
- clarify a couple of expectations regarding what is meant to be achieved;
- update the header format;
- document `-fsanitize=scudo`.

Reviewers: alekseyshl, flowerhack

Reviewed By: alekseyshl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41670

llvm-svn: 321811
 2018-01-04 18:31:22 +00:00