e4dbeb40c6
[X86][AVX] Enabled MULHS/MULHU v16i16 vectors on AVX1 targets
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Correct splitting of v16i16 vectors into v8i16 vectors to prevent scalarization
Differential Revision: http://reviews.llvm.org/D18307
llvm-svn: 264512
2016-03-26 15:44:55 +00:00
3eef33a806
[X86][SSE] Add MULHS/MULHU custom lowering for i8 vectors
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Currently this is to mainly to prevent scalarization of integer division by constants.
Differential Revision: http://reviews.llvm.org/D18307
llvm-svn: 264511
2016-03-26 15:27:20 +00:00
cc41495eb8
[X86][AVX] Added AVX1 tests for 256-bit vector idiv-by-constant
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Prep work based on feedback for D18307
llvm-svn: 264086
2016-03-22 20:10:49 +00:00
4af44f3c13
[X86][SSE] Add vector integer division by constant tests
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Expanded tests and split into sdiv/srem and udiv/urem cases for 128 and 256 bit vectors.
llvm-svn: 263917
2016-03-20 21:46:58 +00:00
Simon Pilgrim