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3 Commits

Author SHA1 Message Date
Tom Stellard cb6ba62d6f AMDGPU/SI: Enable the post-ra scheduler 
Summary:
This includes a hazard recognizer implementation to replace some of
the hazard handling we had during frame index elimination.

Reviewers: arsenm

Subscribers: qcolombet, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D18602

llvm-svn: 268143
 2016-04-30 00:23:06 +00:00
Matt Arsenault efa3fe14d1 AMDGPU: Re-visit nodes in performAndCombine 
This fixes test regressions when i64 loads/stores are made promote.

llvm-svn: 267240
 2016-04-22 22:48:38 +00:00
Matt Arsenault 8d1052f55c DAGCombiner: Reduce 64-bit BFE pattern to pattern on 32-bit component 
If the extracted bits are restricted to the upper half or lower half,
this can be truncated.

llvm-svn: 267024
 2016-04-21 18:03:06 +00:00