07a4cb9382
[avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads.
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This results in things such as
vmovups 16(%rdi), %xmm0
vinsertf128 $1, %xmm0, %ymm0, %ymm0
to be combined to
vinsertf128 $1, 16(%rdi), %ymm0, %ymm0
rdar://11076953
llvm-svn: 153092
2012-03-20 17:08:51 +00:00
32a49333ec
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
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llvm-svn: 153089
2012-03-20 15:54:56 +00:00
a95e449804
test commit
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llvm-svn: 153086
2012-03-20 13:12:38 +00:00
7caea33dfa
Test Commit - add a newline
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llvm-svn: 153083
2012-03-20 10:50:35 +00:00
7315c4b9cd
It's possible to have a constant expression who's size is quite big (e.g.,
...
i128). In that case, we may not be able to print out the MCExpr as an
expression. For instance, we could have an MCExpr like this:
0xBEEF0000BEEF0000 | (0xBEEF0000BEEF0000 << 64)
The MCExpr printer handles sizes up to 64-bits, but this expression would
require 128-bits. In this situation, try to evaluate the constant expression and
emit that as the value into 64-bit chunks.
<rdar://problem/11070338>
llvm-svn: 153081
2012-03-20 08:56:43 +00:00
b34d96c614
Remove code that prevented lowering shuffles if they are used by load and themselves used by a extract_vector_elt. This was done to allow the DAG combiner to collapse to a single element load. Unfortunately, sometimes the extract_vector_elt would disappear before DAG combine could do the transformation leaving a vector_shuffle that isel couldn't handle. New code lets the shuffle be converted to a target specific node, but then adds a combine routine that can convert target specific nodes back to vector_shuffles if the folding criteria are met.
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llvm-svn: 153080
2012-03-20 07:17:59 +00:00
cbc96a6e90
Factor out target shuffle mask decoding from getShuffleScalarElt and use a SmallVector of int instead of unsigned for shuffle mask in decode functions. Preparation for another change.
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llvm-svn: 153079
2012-03-20 06:42:26 +00:00
aaeae98936
When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add users of the final load to the worklist too. Needed by changes I'm preparing to make to X86 backend.
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llvm-svn: 153078
2012-03-20 05:28:39 +00:00
60e01c560a
Do everything up to generating code to try to get a register for
...
a variable. The previous code would break the debug info changing
code invariant. This will regress debug info for arguments where
we elide the alloca created.
Fixes rdar://11066468
llvm-svn: 153074
2012-03-20 01:07:58 +00:00
997aaa9237
Untabify.
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llvm-svn: 153073
2012-03-20 01:07:56 +00:00
e5e54c87fa
Add another debugging statement here.
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llvm-svn: 153072
2012-03-20 01:07:53 +00:00
1a06cc9ae6
Use lookUpRegForValue here instead of duplicating the code.
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llvm-svn: 153071
2012-03-20 01:07:47 +00:00
0a2ac90525
Fix two bugpoint bugs:
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1) opt is not usually in the same path as the target program. Even for
the bugpoint as a standalone app, it should be more portable to search
in PATH, isn't it?
2) bugpoint driver accounts opt plugins, but does not list them in the
final output command.
Patch by Dmitry Mikushin!
llvm-svn: 153066
2012-03-19 23:42:11 +00:00
633ab168a8
fix PR12301 - llvm-bcanalyze should print to stdout, not stderr (except for errors).
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llvm-svn: 153065
2012-03-19 23:40:48 +00:00
e69be6df4f
f16 FDIV can now be legalized by promoting to f32
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llvm-svn: 153064
2012-03-19 23:38:12 +00:00
8c3c65067d
fix a build failure with libc++
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llvm-svn: 153063
2012-03-19 23:31:01 +00:00
c4aa60ffe9
ARM branch relaxation for unconditional t1 branches.
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rdar://11059157
llvm-svn: 153055
2012-03-19 21:32:32 +00:00
67e76babd3
ARM assembly, accept optional '#' on lane index number.
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rdar://11057160
llvm-svn: 153053
2012-03-19 20:39:53 +00:00
9da9e6937f
[Object/COFF]: Expose getSectionContents.
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llvm-svn: 153051
2012-03-19 20:27:37 +00:00
53c2d5477a
[Object/COFF]: Expose getSectionName.
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Also add some documentation.
llvm-svn: 153050
2012-03-19 20:27:15 +00:00
3edd854d64
Perform mul combine when multiplying wiht negative constants.
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Patch by Weiming Zhao!
This fixes PR12212
llvm-svn: 153049
2012-03-19 19:19:50 +00:00
dd98c497b9
Add an option to the MI scheduler to cut off scheduling after a fixed number of
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instructions have been scheduled. Handy for tracking down scheduler bugs, or
bugs exposed by scheduling.
llvm-svn: 153045
2012-03-19 18:38:38 +00:00
c58dc9fcd2
[asan] don't emit __asan_mapping_offset/__asan_mapping_scale by default -- they are currently used only for experiments
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llvm-svn: 153040
2012-03-19 16:40:35 +00:00
bed1cb1e13
llvm/test/DebugInfo: Move two tests to DebugInfo/X86. They are X86-dependent.
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llvm-svn: 153038
2012-03-19 16:16:03 +00:00
3fb2fc6edb
Fix DAG combine which creates illegal vector shuffles. Patch by Heikki Kultala.
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llvm-svn: 153035
2012-03-19 15:35:44 +00:00
48ccc4df0b
This patch adds X86 instruction itineraries for non-pseudo opcodes in
...
X86InstrCompiler.td.
It also adds –mcpu-generic to the legalize-shift-64.ll test so the test
will pass if run on an Intel Atom CPU, which would otherwise
produce an instruction schedule which differs from that which the test expects.
llvm-svn: 153033
2012-03-19 14:10:12 +00:00
57003a6768
Add a note for -ffast-math optimization of vector norm.
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llvm-svn: 153031
2012-03-19 00:43:34 +00:00
93f2c7b584
Make the formatting of this file more consistent, and fix the 80-columns
...
violations I introduced. Also sort some of the instructions to get
a more consistent ordering.
Suggestions on still better / more consistent formatting would be
welcome. I'm actually tempted to use a macro to define all of the
delegate methods...
llvm-svn: 153030
2012-03-18 23:45:14 +00:00
609522e2cc
Teach InstVisitor about the UnaryInstruction layer in the instruction
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type hierarchy. I wanted to use this for the inline cost rewrite, and
found it was missing.
llvm-svn: 153029
2012-03-18 23:31:28 +00:00
fa30607eca
Factor out the multiply analysis code in ComputeMaskedBits and apply it to the
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overflow checking multiply intrinsic as well.
Add a test for this, updating the test from grep to FileCheck.
llvm-svn: 153028
2012-03-18 23:28:48 +00:00
129f9ef669
isCommutedMOVLMask should only look at 128-bit vectors to match isMOVLMask.
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llvm-svn: 153027
2012-03-18 22:50:10 +00:00
f70a2bde45
This clause (although matching parts of the implementation) can't be correct.
...
Thanks to Eli for noticing the discrepancy.
llvm-svn: 153011
2012-03-18 09:35:50 +00:00
5d1bca8016
CriticalAntiDepBreaker: Replace a SmallSet of regs with a much denser BitVector.
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llvm-svn: 152999
2012-03-17 20:22:57 +00:00
b25fda95f6
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
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llvm-svn: 152997
2012-03-17 18:46:09 +00:00
97f889f43b
MachineInstr: Inline the fast path (non-bundle instruction) of hasProperty.
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This is particularly helpful as both arguments tend to be constants.
llvm-svn: 152991
2012-03-17 17:03:45 +00:00
f3f6650f8f
Fix some copy and paste remnants of Cell and SPU in Hexagon files.
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llvm-svn: 152981
2012-03-17 09:39:20 +00:00
bc3168b128
Fix typo in file header.
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llvm-svn: 152980
2012-03-17 09:28:37 +00:00
b545408116
Pass TargetOptions to HexagonTargetMachine constructor by reference to match other targets and the base class.
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llvm-svn: 152979
2012-03-17 09:24:09 +00:00
188ed9d56e
Reorder includes to match coding standards. Fix an issue or two exposed by that.
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llvm-svn: 152978
2012-03-17 07:33:42 +00:00
2c8e0ac85c
MC asm parser macro argument count was wrong when empty.
...
evaluated to '1' when the argument list was empty (should be '0').
rdar://11057257
llvm-svn: 152967
2012-03-17 00:11:42 +00:00
23f8c4a50c
Check if we can handle the arguments of a call (and therefore the call) in
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fast-isel before emitting code. If the program bails after code was emitted,
then it could lead to the stack being adjusted more than once (two
CALLSEQ_BEGINs emitted) but being adjuste back only once after the call. This
leads to general badness and gnashing of teeth.
<rdar://problem/11050630>
llvm-svn: 152959
2012-03-16 23:11:07 +00:00
b7ae23fb66
Revert r152915. Chapuni's WinWaitReleased refactoring: It doesn't work for me
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llvm-svn: 152958
2012-03-16 22:50:01 +00:00
c9de7e5281
clarify the coding standards a bit.
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llvm-svn: 152957
2012-03-16 22:34:37 +00:00
c40b0f72bb
ARM fix silly typo in optional operand alias.
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rdar://11065671
llvm-svn: 152954
2012-03-16 22:18:29 +00:00
db7db7d3a3
ARM divided syntax fmrx/fmxr mnemonics.
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llvm-svn: 152946
2012-03-16 21:06:13 +00:00
905686a82a
ARM ldm/stm register lists can be out of order.
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It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.
rdar://11064740
llvm-svn: 152943
2012-03-16 20:48:38 +00:00
55b6b2b6a9
Revert r152907.
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llvm-svn: 152935
2012-03-16 18:20:54 +00:00
411d5a2026
ScheduleDAGInstrs: When adding uses we add them into a set that's empty at the beginning, no need to maintain another set for the added regs.
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llvm-svn: 152934
2012-03-16 17:38:19 +00:00
d03878bdf2
Limit the number of memory operands in MachineInstr to 2^16 and store the number in padding.
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Saves one machine word on MachineInstr (88->80 bytes on x86_64, 48->44 on i386).
llvm-svn: 152930
2012-03-16 16:39:27 +00:00
8e5af375db
CriticalAntiDepBreaker: BasicBlock::size is an expensive operation, reuse the cached value.
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No functionality change.
llvm-svn: 152927
2012-03-16 15:46:47 +00:00
Chad Rosier