Commit Graph

95570 Commits

Author SHA1 Message Date
Bill Wendling d14f153a7e Run clang-format on these header files. Part of a WIP.
llvm-svn: 190250
2013-09-07 11:55:36 +00:00
Akira Hatanaka 9f9bc4f770 [mips] Fix typos.
llvm-svn: 190236
2013-09-07 01:14:42 +00:00
Akira Hatanaka 6379121694 [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
precision loads and stores as well as reg+imm double precision loads and stores.

Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.

llvm-svn: 190235
2013-09-07 00:52:30 +00:00
Akira Hatanaka 92ec3bd50b [mips] Place parentheses around && to silence warning.
llvm-svn: 190234
2013-09-07 00:26:26 +00:00
Richard Smith d9e5ff24e6 Remove verifier check that attribute 'builtin' is only applied to calls to
functions marked 'nobuiltin'. That approach doesn't play well with LTO, and
there's no harm in marking a call as 'builtin' if it was going to be a builtin
regardless.

llvm-svn: 190233
2013-09-07 00:25:48 +00:00
Akira Hatanaka 6a3fe57444 [mips] Add definition of instruction "drotr32" (double rotate right plus 32).
llvm-svn: 190232
2013-09-07 00:18:01 +00:00
Manman Ren c4ae9b3aeb Debug Info: Use identifier to reference DIType in containing type field of
a DISubprogram.
    
Verifier is updated accordingly.

llvm-svn: 190229
2013-09-07 00:04:05 +00:00
Akira Hatanaka 3121353c99 [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
into a 5-bit or 6-bit field.

llvm-svn: 190226
2013-09-07 00:02:02 +00:00
Manman Ren 275520608b Debug Info: pass in VTableHolder as DIType instead of MDNode *.
Remove one cast and improve readability. No functionality change.

llvm-svn: 190225
2013-09-06 23:54:23 +00:00
Akira Hatanaka 79e38cde37 [mips] Define "trap" as a pseudo instruction that turns into "break 0, 0".
llvm-svn: 190224
2013-09-06 23:52:46 +00:00
Akira Hatanaka 50eebac68b [mips] Delete unused classes and defs.
llvm-svn: 190221
2013-09-06 23:42:58 +00:00
Akira Hatanaka 2c544d8ed5 [mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, which is
equivalent to "beq $zero, $zero, offset".

llvm-svn: 190220
2013-09-06 23:40:15 +00:00
Akira Hatanaka dffc542123 [mips] Set instruction itineraries of loads, stores and conditional moves.
llvm-svn: 190219
2013-09-06 23:28:24 +00:00
Manman Ren d8c68b1852 TBAA: add isTBAAVtableAccess to MDNode so clients can call the function
instead of having its own implementation.

The implementation of isTBAAVtableAccess is in TypeBasedAliasAnalysis.cpp
since it is related to the format of TBAA metadata.

The path for struct-path tbaa will be exercised by
test/Instrumentation/ThreadSanitizer/read_from_global.ll, vptr_read.ll, and
vptr_update.ll when struct-path tbaa is on by default.

llvm-svn: 190216
2013-09-06 22:47:05 +00:00
Manman Ren deeafd8a58 Debug Info Testing: updated to use NULL instead of "i32 0" in a few fields.
Field 2 of DIType (Context), field 9 of DIDerivedType (TypeDerivedFrom),
field 12 of DICompositeType (ContainingType), fields 2, 7, 12 of DISubprogram
(Context, Type, ContainingType).

llvm-svn: 190205
2013-09-06 21:03:58 +00:00
Aaron Watry 372cecf642 R600: Add support for LDS atomic subtract
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 190200
2013-09-06 20:17:42 +00:00
Manman Ren d8f798ea97 Debug Info: Use identifier to reference DIType in containing type field of
a DICompositeType.
    
Verifier is updated accordingly.

llvm-svn: 190190
2013-09-06 18:46:00 +00:00
Manman Ren 277206fa28 Debug Info: Move a helper function getTypeIdentifier from DIBuilder to be part
of DIType.
    
Implement DIType::generateRef to return a type reference. This function will be
used in setContaintingType and in DIBuilder to generete the type reference.
    
No functionality change.

llvm-svn: 190188
2013-09-06 18:27:00 +00:00
Manman Ren 4c12bf5ac7 Debug Info Testing: Updated to use null instead of "i32 0" for containing-type
field of DICompositeType.

This will help the follow-on patch of using DITypeRef for containing-type field.

llvm-svn: 190187
2013-09-06 18:13:59 +00:00
Adrian Prantl e8010fa54c debuginfo-tests: Add support for an lldb wrapper script
to be used on darwin in lieu of gdb.

llvm-svn: 190186
2013-09-06 18:12:01 +00:00
Andrew Trick b248b4a1de mi-sched: cleanup register pressure update, remove a FIXME.
llvm-svn: 190181
2013-09-06 17:32:47 +00:00
Andrew Trick c573cd905a mi-sched: improve regpressure tracing.
llvm-svn: 190180
2013-09-06 17:32:44 +00:00
Andrew Trick 7609b7d1b5 mi-sched: print tree size in -view-misched-dags
llvm-svn: 190179
2013-09-06 17:32:42 +00:00
Andrew Trick ffdbefb90c mi-sched: register pressure update tracing.
llvm-svn: 190178
2013-09-06 17:32:39 +00:00
Andrew Trick ddffae9027 mi-sched: Reorder Cyclicpath (latency) and CriticalMax (pressure) heuristics.
The latency based scheduling could induce spills in some cases.

llvm-svn: 190177
2013-09-06 17:32:36 +00:00
Andrew Trick 75e411cc8e Added MachineSchedPolicy.
Allow subtargets to customize the generic scheduling strategy.
This is convenient for targets that don't need to add new heuristics
by specializing the strategy.

llvm-svn: 190176
2013-09-06 17:32:34 +00:00
Hans Wennborg 8df6417683 msbuild integration: provide separate files for VS2010 and VS2012
The previous msbuild integration only worked if VS2010 was installed. This patch
renames the current integration to LLVM-vs2010 and adds LLVM-vs2012.

Differential Revision: http://llvm-reviews.chandlerc.com/D1614

llvm-svn: 190173
2013-09-06 17:05:46 +00:00
Matthias Braun 305ef7f5b0 avoid unnecessary direct access to LiveInterval::ranges
llvm-svn: 190170
2013-09-06 16:44:32 +00:00
Matthias Braun 90e0d3c03a remove unused argument from LiveRanges::join()
llvm-svn: 190169
2013-09-06 16:44:29 +00:00
Matthias Braun c0ad7bfa62 remove pointless assert
The if above it ensures the property anyway.

llvm-svn: 190168
2013-09-06 16:44:27 +00:00
Matthias Braun b348d9703c fix comment
There's no 'B3' in the example.

llvm-svn: 190167
2013-09-06 16:44:25 +00:00
Matthias Braun 9804f81fde fix typo in comment
llvm-svn: 190165
2013-09-06 16:19:22 +00:00
Daniel Sanders af7f805b96 [mips][msa] Indentation
llvm-svn: 190156
2013-09-06 13:25:06 +00:00
Daniel Sanders 636f72fc08 [mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance
Tested with 'llvm-tblgen -print-records' which outputs identical records before
and after this patch.

llvm-svn: 190155
2013-09-06 13:15:05 +00:00
Vladimir Medic b936da159e This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
llvm-svn: 190154
2013-09-06 13:08:00 +00:00
Daniel Sanders 563e5eabe5 [mips][msa] Made the operand register sets optional for the VEC formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190153
2013-09-06 13:01:47 +00:00
Vladimir Medic 457ba56b05 This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
llvm-svn: 190152
2013-09-06 12:53:21 +00:00
Daniel Sanders 41fb2c0d0e [mips][msa] Made the operand register sets optional for the ELM_INSVE formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190151
2013-09-06 12:50:52 +00:00
Daniel Sanders fa1b0fa77e [mips][msa] Made the operand register sets optional for the 3RF_4RF format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190150
2013-09-06 12:44:13 +00:00
Vladimir Medic e0fbb44a48 This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
llvm-svn: 190148
2013-09-06 12:41:17 +00:00
Tim Northover 950fcc0577 SelectionDAG: create correct BooleanContent constants
Occasionally DAGCombiner can spot that a SETCC operation is completely
redundant and reduce it to "all true" or "all false". If this happens to a
vector, the value produced has to take account of what a normal comparison
would have produced, which may be an all-1s bitmask.

The fix in SelectionDAG.cpp is tested, however, as far as I can see the code in
TargetLowering.cpp is possibly unreachable and almost certainly irrelevant when
triggered so there are no tests. However, I believe it's still clearly the
right change and may save someone else some hassle if it suddenly becomes
reachable. So I'm doing it anyway.

llvm-svn: 190147
2013-09-06 12:38:12 +00:00
Daniel Sanders d719f5281c [mips][msa] Made the operand register sets optional for the 3RF formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190146
2013-09-06 12:32:57 +00:00
Daniel Sanders b2b7c0a044 [mips][msa] Made the operand register sets optional for the 3R_4R format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190145
2013-09-06 12:30:43 +00:00
Vladimir Medic dde3d582a2 This patch adds support for microMIPS disassembler and disassembler make check tests.
llvm-svn: 190144
2013-09-06 12:30:36 +00:00
Daniel Sanders 2322f5d090 [mips][msa] Made the operand register sets optional for the 2RF format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190143
2013-09-06 12:28:13 +00:00
Daniel Sanders 9148218cbe [mips][msa] Made the operand register sets optional for the I8 format
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190142
2013-09-06 12:25:47 +00:00
Daniel Sanders 92c40a5796 [mips][msa] Made the operand register sets optional for the I5 and SI5 formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190141
2013-09-06 12:23:19 +00:00
Daniel Sanders 13d5e2f376 [mips][msa] Made the operand register sets optional for the BIT_[BHWD] formats
Their default is to be the same as the result register set.

No functional change

llvm-svn: 190140
2013-09-06 12:10:24 +00:00
Richard Sandiford 5bc670bb55 [SystemZ] Tweak integer comparison code
The architecture has many comparison instructions, including some that
extend one of the operands.  The signed comparison instructions use sign
extensions and the unsigned comparison instructions use zero extensions.
In cases where we had a free choice between signed or unsigned comparisons,
we were trying to decide at lowering time which would best fit the available
instructions, taking things like extension type into account.  The code
to do that was getting increasingly hairy and was also making some bad
decisions.  E.g. when comparing the result of two LLCs, it is better to use
CR rather than CLR, since CR can be fused with a branch while CLR can't.

This patch removes the lowering code and instead adds an operand to
integer comparisons to say whether signed comparison is required,
whether unsigned comparison is required, or whether either is OK.
We can then leave the choice of instruction up to the normal isel code.

llvm-svn: 190138
2013-09-06 11:51:39 +00:00
Daniel Sanders 63b97d5ae5 [mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size
No functional change

llvm-svn: 190134
2013-09-06 11:01:38 +00:00