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5946 Commits

Author SHA1 Message Date
Chris Lattner 49c45d3a13 Fix some X86 JIT failures. This should really come from TargetJITInfo. 
llvm-svn: 30102
 2006-09-04 18:48:41 +00:00
Duraid Madina cf6749e4c0 add setJumpBufSize() and setJumpBufAlignment() to target-lowering. 
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example

llvm-svn: 30095
 2006-09-04 06:21:35 +00:00
Chris Lattner 12e97307a1 Completely rearchitect the interface between targets and the pass manager. 
This pass:

1. Splits TargetMachine into TargetMachine (generic targets, can be implemented
any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by
things using libcodegen and other support).
2. Instead of having each target fully populate the passmgr for file or JIT
   output, move all this to common code, and give targets hooks they can
   implement.
3. Commonalize the target population stuff between file emission and JIT
   emission.
4. All (native code) codegen stuff now happens in a FunctionPassManager, which
   paves the way for "fast -O0" stuff in the CFE later, and now LLC could
   lazily stream .bc files from disk to use less memory.
5. There are now many fewer #includes and the targets don't depend on the
   scalar xforms or libanalysis anymore (but codegen does).
6. Changing common code generator pass ordering stuff no longer requires
   touching all targets.
7. The JIT now has the option of "-fast" codegen or normal optimized codegen,
   which is now orthogonal to the fact that JIT'ing is being done.

llvm-svn: 30081
 2006-09-04 04:14:57 +00:00
Chris Lattner e8ce162969 Add accessor 
llvm-svn: 30080
 2006-09-04 04:08:58 +00:00
Chris Lattner 2f93c0fd33 remove #include 
llvm-svn: 30078
 2006-09-04 04:06:01 +00:00
Chris Lattner 0fc4541c67 Simplify target construction. 
llvm-svn: 30070
 2006-09-03 18:44:02 +00:00
Rafael Espindola 5328ba96e1 add the SETULT condition code 
llvm-svn: 30067
 2006-09-03 13:19:16 +00:00
Rafael Espindola c585b6919b add more condition codes 
llvm-svn: 30056
 2006-09-02 20:24:25 +00:00
Evan Cheng 2c4e0f120f Oops. Bad typo. Without the check of N1.hasOneUse() bad things can happen. 
Suppose the TokenFactor can reach the Op:

       [Load chain]
           ^
           |
         [Load]
         ^    ^
         |    |
        /      \-
       /         |
      /          [Op]
     /          ^ ^
     |        ..  |
     |       /    |
   [TokenFactor]  |
       ^          |
       |          |
        \        /
         \      /
         [Store]

If we move the Load below the TokenFactor, we would have created a cycle in
the DAG.

llvm-svn: 30040
 2006-09-01 22:52:28 +00:00
Chris Lattner bad9d2ee49 Use a couple of multiclass patterns to factor some integer ops. 
llvm-svn: 30039
 2006-09-01 22:28:02 +00:00
Chris Lattner 38e6d1d5af remove a bunch of comments 
llvm-svn: 30038
 2006-09-01 22:16:22 +00:00
Evan Cheng 6d464146d0 Minor asm fix. 
llvm-svn: 29965
 2006-08-29 22:14:48 +00:00
Evan Cheng b28800f4d5 Remove dead code. 
llvm-svn: 29962
 2006-08-29 21:42:58 +00:00
Evan Cheng dfb85155dc Don't performance load/op/store transformation if op produces a floating point 
or vector result. X86 does not have load/mod/store variants of those
instructions.

llvm-svn: 29957
 2006-08-29 18:37:37 +00:00
Evan Cheng 358b9ed98a - Enable x86 isel preprocessing by default unless -fast is specified. 
- Also disable isel load folding if -fast.

llvm-svn: 29956
 2006-08-29 18:28:33 +00:00
Jim Laskey 2eebe8b05e Handle callee saved registers in dwarf frame info (lead up to exception 
handling.)

llvm-svn: 29954
 2006-08-29 16:24:26 +00:00
Jim Laskey 82dc16c0a7 Tidy up options. 
llvm-svn: 29953
 2006-08-29 15:13:10 +00:00
Evan Cheng c07feb14b0 Avoid making unneeded load/mod/store transformation which can hurt performance. 
llvm-svn: 29952
 2006-08-29 06:44:17 +00:00
Nate Begeman 18f0329cfc Make ppc64 jit kinda work right. About 2/3 of Olden passes with this, 
there are clearly some encoding bugs lurking in there somewhere.

llvm-svn: 29949
 2006-08-29 02:30:59 +00:00
Evan Cheng 00884b51c5 On Mac, print jump table entries after the function to work around a linker issue. 
llvm-svn: 29946
 2006-08-28 22:14:16 +00:00
Evan Cheng 64a9e28846 Add an optional pass to preprocess the DAG before x86 isel to allow selecting more load/mod/store instructions. 
llvm-svn: 29943
 2006-08-28 20:10:17 +00:00
Reid Spencer e7141c8be6 For PR387: 
Close out this long standing bug by removing the remaining overloaded
virtual functions in LLVM. The -Woverloaded-virtual option is now turned on.

llvm-svn: 29934
 2006-08-28 01:02:49 +00:00
Chris Lattner 3d27be1333 s|llvm/Support/Visibility.h|llvm/Support/Compiler.h| 
llvm-svn: 29911
 2006-08-27 12:54:02 +00:00
Evan Cheng c3acfc0b10 Do not use getTargetNode() and SelectNodeTo() which takes more than 3 
SDOperand arguments. Use the variants which take an array and number instead.

llvm-svn: 29907
 2006-08-27 08:14:06 +00:00
Chris Lattner 4042e871ce Fix target matching weights, so that ppc-darwin modules are codegen with the 
ppc target, not the itanium target, when run on an itanium machine.
This should fix the CodeGen/PowerPC regtest failures on itanium.

llvm-svn: 29903
 2006-08-26 21:33:05 +00:00
Evan Cheng 34b70eea5c SelectNodeTo now returns a SDNode*. 
llvm-svn: 29901
 2006-08-26 08:00:10 +00:00
Evan Cheng 61413a3d72 Select() no longer require Result operand by reference. 
llvm-svn: 29898
 2006-08-26 05:34:46 +00:00
Evan Cheng ab8297f92d Match tblgen changes. 
llvm-svn: 29895
 2006-08-26 01:07:58 +00:00
Evan Cheng 2d48722e92 Match tblgen changes; clean up. 
llvm-svn: 29894
 2006-08-26 01:05:16 +00:00
Chris Lattner c664efe223 Give a good error message when we try to jit inline asm. 
llvm-svn: 29891
 2006-08-26 00:47:03 +00:00
Evan Cheng 1b200574ad Add a comment. 
llvm-svn: 29889
 2006-08-25 23:29:06 +00:00
Evan Cheng d7572fb234 Encode pc-relative conditional branch offset as pc+(num of bytes / 4). The 
asm printer will print it as offset*4. e.g. bne cr0, $+8.

The PPC code emitter was expecting the offset to be number of instructions, not
number of bytes. This fixes a whole bunch of JIT failures.

llvm-svn: 29885
 2006-08-25 21:54:44 +00:00
Jim Laskey d51ce619c3 Fix some comments. 
llvm-svn: 29880
 2006-08-25 19:40:59 +00:00
Rafael Espindola 98dc23fd1f use @ for comments 
store LR in an arbitrary stack slot
add support for writing varargs functions

llvm-svn: 29876
 2006-08-25 17:55:16 +00:00
Chris Lattner ac40a81253 We compile this into: 
_swap_16:
        slwi r2, r3, 24
        rlwimi r2, r3, 8, 8, 15
        srwi r3, r2, 16
        blr

now.

llvm-svn: 29864
 2006-08-24 23:06:02 +00:00
Chris Lattner fb6bc15d5d Owen implemented this. 
llvm-svn: 29863
 2006-08-24 23:03:33 +00:00
Rafael Espindola 29e4875f57 add the "eq" condition code 
implement a movcond instruction

llvm-svn: 29857
 2006-08-24 17:19:08 +00:00
Rafael Espindola fe03fe9bf4 create a generic bcond instruction that has a conditional code argument 
llvm-svn: 29856
 2006-08-24 16:13:15 +00:00
Rafael Espindola e08b9853cc initial support for branches 
llvm-svn: 29854
 2006-08-24 13:45:55 +00:00
Nate Begeman 3cb3921a60 Initial checkin of the Mach-O emitter. There's plenty of fixmes, but it 
does emit linkable .o files in very simple cases.

llvm-svn: 29850
 2006-08-23 21:08:52 +00:00
Rafael Espindola ea500426d6 add a README.txt 
llvm-svn: 29814
 2006-08-22 12:22:46 +00:00
Rafael Espindola d0dee77718 initial support for select 
llvm-svn: 29802
 2006-08-21 22:00:32 +00:00
Rafael Espindola 9d77f9fd24 add the and instruction 
llvm-svn: 29793
 2006-08-21 13:58:59 +00:00
Rafael Espindola 8a675a5d09 call computeRegisterProperties 
llvm-svn: 29780
 2006-08-20 01:49:49 +00:00
Chris Lattner 60f1eecd3a Constify some methods. Patch provided by Anton Vayvod, thanks! 
llvm-svn: 29756
 2006-08-17 22:00:08 +00:00
Chris Lattner 162f2d5d4c Revert this patch, the front-end has been fixed to make it unneccesary. 
llvm-svn: 29752
 2006-08-17 18:43:24 +00:00
Chris Lattner dfb3f0591d 'g' is handled by the front-end. 
llvm-svn: 29751
 2006-08-17 18:12:28 +00:00
Andrew Lenharth 4a063c5ffb Fix handling of 'g'. Closes 883 
llvm-svn: 29750
 2006-08-17 17:50:12 +00:00
Rafael Espindola c3ed77e1b9 add a "load effective address" 
llvm-svn: 29748
 2006-08-17 17:09:40 +00:00
Andrew Lenharth 1c3210d08d Add the 'c' constraint as needed by the linux kernel 
llvm-svn: 29747
 2006-08-17 16:07:50 +00:00
Andrew Lenharth fc60fb974c Add support for S and D constraints, as needed to compile the linux kernel. 
llvm-svn: 29746
 2006-08-17 15:35:43 +00:00
Evan Cheng 29ab7c42a8 Doh. Incorrectly inverted condition. Also add a isOnlyUse check to match tablegen. 
llvm-svn: 29741
 2006-08-16 23:59:00 +00:00
Rafael Espindola bf8e751488 Declare the callee saved regs 
Remove the hard coded store and load of the link register
Implement ARMFrameInfo

llvm-svn: 29727
 2006-08-16 14:43:33 +00:00
Evan Cheng 63d178f473 SelectNodeTo() may return a SDOperand that is different from the input. 
llvm-svn: 29726
 2006-08-16 07:30:09 +00:00
Evan Cheng f2a7d5768a RET_FLAG has an optional input flag, but it does not produce a flag result. 
llvm-svn: 29725
 2006-08-16 07:28:58 +00:00
Chris Lattner 08a5f38c5c add a note 
llvm-svn: 29722
 2006-08-16 02:47:44 +00:00
Chris Lattner bc485fdc4c Fix PowerPC/2006-08-15-SelectionCrash.ll and simplify selection code. 
llvm-svn: 29715
 2006-08-15 23:48:22 +00:00
Rafael Espindola 157971b04a select code like 
ldr rx, [ry, #offset]

llvm-svn: 29664
 2006-08-14 19:01:24 +00:00
Nate Begeman 984c1a4a8f Emit .set directives for jump table entries when possible, which reduces 
the number of relocations in object files, shrinkifying them.

llvm-svn: 29650
 2006-08-12 21:29:52 +00:00
Chris Lattner 095e4ad2ea Fix a bug in a recent refactoring that broke a bunch of stuff. 
llvm-svn: 29649
 2006-08-12 07:20:05 +00:00
Chris Lattner 20b461a97f eliminate extraneous blank line 
llvm-svn: 29627
 2006-08-11 21:08:16 +00:00
Chris Lattner ed728e8dc9 Eliminate use of getNode that takes a vector. 
llvm-svn: 29614
 2006-08-11 17:38:39 +00:00
Chris Lattner c62914880f elimiante use of getNode that takes vector of operands. 
llvm-svn: 29612
 2006-08-11 17:22:35 +00:00
Chris Lattner 56565b5cb9 eliminate use of getNode that takes vector of operands. 
llvm-svn: 29611
 2006-08-11 17:21:12 +00:00
Chris Lattner 2aa76cf371 eliminate use of getNode that takes vector<SDOperand>. Wrap a really long line. 
llvm-svn: 29610
 2006-08-11 17:19:54 +00:00
Chris Lattner d66f14e846 Convert vectors to fixed sized arrays and smallvectors. Eliminate use of getNode that takes a vector. 
llvm-svn: 29609
 2006-08-11 17:18:05 +00:00
Chris Lattner 66f1fbaaad Fix miscompilation of float vector returns. Compile code to this: 
_func:
        vsldoi v2, v3, v2, 12
        vsldoi v2, v2, v2, 4
        blr

instead of:

_func:
        vsldoi v2, v3, v2, 12
        vsldoi v2, v2, v2, 4
***     vor f1, v2, v2
        blr

llvm-svn: 29607
 2006-08-11 16:47:32 +00:00
Evan Cheng bd1c5a8fb8 Match tablegen changes. 
llvm-svn: 29604
 2006-08-11 09:08:15 +00:00
Evan Cheng 81b645a76b CALLSEQ_* produces chain even if that's not needed. 
llvm-svn: 29603
 2006-08-11 09:03:33 +00:00
Evan Cheng 5c68bba085 Convert more calls of getNode() that takes a vector to pass in the start of an array. 
llvm-svn: 29601
 2006-08-11 07:35:45 +00:00
Rafael Espindola 1c41fc9b06 correctly set LocalAreaOffset of TargetFrameInfo 
llvm-svn: 29589
 2006-08-09 17:37:45 +00:00
Rafael Espindola f5ce475540 fix the spill code 
llvm-svn: 29583
 2006-08-09 16:41:12 +00:00
Rafael Espindola 58159b36a3 fix the loading of the link register in emitepilogue 
llvm-svn: 29580
 2006-08-09 13:15:47 +00:00
Rafael Espindola 8c41f99e6f change the addressing mode of the str instruction to reg+imm 
llvm-svn: 29571
 2006-08-08 20:35:03 +00:00
Rafael Espindola 39083e7836 initial support for variable number of arguments 
llvm-svn: 29567
 2006-08-08 13:02:29 +00:00
Chris Lattner c24a1d3093 Start eliminating temporary vectors used to create DAG nodes. Instead, pass 
in the start of an array and a count of operands where applicable.  In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap.  In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.

I updated a lot of code calling getNode that takes a vector, but ran out of
time.  The rest of the code should be updated, and these methods should be
removed.

We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.

It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.

llvm-svn: 29566
 2006-08-08 02:23:42 +00:00
Evan Cheng 72bb66a4b8 Eliminate reachability matrix. It has to be calculated before any instruction 
selection is done. That's rather expensive especially in situations where it
isn't really needed.
Move back to a searching the predecessors, but make use of topological order
to trim the search space.

llvm-svn: 29559
 2006-08-08 00:31:00 +00:00
Evan Cheng b9d34bd098 Match tablegen isel changes. 
llvm-svn: 29549
 2006-08-07 22:28:20 +00:00
Evan Cheng d5e38e017c Make XMM, FP register dwarf register numbers consistent with gcc. 
llvm-svn: 29543
 2006-08-07 21:02:39 +00:00
Rafael Espindola 2bcb8c0f05 use a 'register pressure reducing' scheduler 
make sure only one move is used in a hello world

llvm-svn: 29520
 2006-08-04 12:48:42 +00:00
Rafael Espindola e19f6fde2d Bug fix: always generate a RET_FLAG in LowerRET 
fixes ret_null.ll and call.ll

llvm-svn: 29519
 2006-08-03 22:50:11 +00:00
Chris Lattner fef2c5f0a2 remove some more dead sparcv9 support stuff 
llvm-svn: 29506
 2006-08-03 18:55:44 +00:00
Chris Lattner 682ff0dd15 remove a dead proto 
llvm-svn: 29505
 2006-08-03 18:51:04 +00:00
Jim Laskey f2c14591e6 Get darwin intel debugging up and running. 
llvm-svn: 29504
 2006-08-03 17:27:09 +00:00
Rafael Espindola a94b9e33af add and use ARMISD::RET_FLAG 
llvm-svn: 29499
 2006-08-03 17:02:20 +00:00
Evan Cheng 8f585196e1 Reflect change to AssignTopologicalOrder(). 
llvm-svn: 29480
 2006-08-02 22:01:32 +00:00
Evan Cheng 8101dd67d1 Use of vector<bool> causes some horrendous compile time regression (2x)! 
Looks like libstdc++ implementation does not scale very well. Switch back
to using directly managed arrays.

llvm-svn: 29469
 2006-08-02 09:18:33 +00:00
Nate Begeman 6025c92e50 Update the readme to remove duplicate information and clarify the loop 
problem.

llvm-svn: 29468
 2006-08-02 05:31:20 +00:00
Nate Begeman d573cc7938 Disable LSR at -fast 
llvm-svn: 29467
 2006-08-02 05:29:40 +00:00
Rafael Espindola 8b7bd8264b start comments with # 
move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save

llvm-svn: 29451
 2006-08-01 18:53:10 +00:00
Rafael Espindola 95035cf001 implement LowerConstantPool and LowerGlobalAddress 
llvm-svn: 29433
 2006-08-01 12:58:43 +00:00
Evan Cheng 45af287957 Factor topological order code to SelectionDAG. Clean up. 
llvm-svn: 29430
 2006-08-01 08:17:22 +00:00
Chris Lattner 524129dd64 Fix PR850 and CodeGen/X86/2006-07-31-SingleRegClass.ll. 
The CFE refers to all single-register constraints (like "A") by their 16-bit
name, even though the 8 or 32-bit version of the register may be needed.
The X86 backend should realize what is going on and redecode the name back
to its proper form.

llvm-svn: 29420
 2006-07-31 23:26:50 +00:00
Rafael Espindola 7cc2d19fc1 handle GlobalValue::InternalLinkage in doFinalization 
llvm-svn: 29417
 2006-07-31 20:38:13 +00:00
Evan Cheng ac8be4338c Remove a duplicate pattern. 
llvm-svn: 29414
 2006-07-31 18:43:10 +00:00
Evan Cheng 2af3a67902 Remove a duplicate pattern/ 
llvm-svn: 29413
 2006-07-31 18:42:49 +00:00
Chris Lattner ebb592be39 Make functions with an "asm" name propagate that asm name into the cbe.c file. 
This fixes link errors on programs with these on targets with prefixes.

llvm-svn: 29390
 2006-07-28 20:58:47 +00:00
Chris Lattner 8298265042 Fix some ppc64 issues with vector code. 
llvm-svn: 29384
 2006-07-28 16:45:47 +00:00
Evan Cheng e8071ecc3b Can't spell. 
llvm-svn: 29383
 2006-07-28 06:33:41 +00:00
Evan Cheng 2e94538b8e Some clean up. 
llvm-svn: 29382
 2006-07-28 06:05:06 +00:00
Evan Cheng e2a3f7014d Rename IsFoldableBy to CanBeFoldedleBy 
llvm-svn: 29376
 2006-07-28 01:03:48 +00:00
Evan Cheng 11a4d8c2f4 Node selected into address mode cannot be folded. 
llvm-svn: 29374
 2006-07-28 00:49:31 +00:00
Evan Cheng b572401bea Remove InFlightSet hack. No longer needed. 
llvm-svn: 29373
 2006-07-28 00:47:19 +00:00
Evan Cheng 3b5e0cafd1 Another duh. Determine topological order before any target node is added. 
llvm-svn: 29371
 2006-07-28 00:10:59 +00:00
Evan Cheng f38707b8d4 Brain cramp.. 
llvm-svn: 29370
 2006-07-27 23:35:40 +00:00
Evan Cheng 390dd7eb7d Allocating too large an array for ReachibilityMatrix. 
llvm-svn: 29367
 2006-07-27 22:35:40 +00:00
Evan Cheng 87585760ab Calculate the portion of reachbility matrix on demand. 
llvm-svn: 29366
 2006-07-27 22:10:00 +00:00
Evan Cheng d6c0c2dfd9 isNonImmUse is replaced by IsFoldableBy 
llvm-svn: 29365
 2006-07-27 21:19:10 +00:00
Evan Cheng 78bf1074fc Resolve BB references with relocation. 
llvm-svn: 29351
 2006-07-27 18:21:10 +00:00
Evan Cheng 7ec7b467df synchronizeICache removeed from TargetJITInfo. 
llvm-svn: 29348
 2006-07-27 17:33:48 +00:00
Evan Cheng 691a63d564 Use reachbility information to determine whether a node can be folded into another during isel. 
llvm-svn: 29346
 2006-07-27 16:44:36 +00:00
Rafael Espindola 89e5cbd897 emit global constants 
llvm-svn: 29344
 2006-07-27 11:38:51 +00:00
Evan Cheng f300896420 Remove NodeDepth 
llvm-svn: 29338
 2006-07-27 06:40:15 +00:00
Chris Lattner 85ea83e821 Add some advice 
llvm-svn: 29324
 2006-07-27 04:24:14 +00:00
Jim Laskey 3b4866e194 Use the predicate. 
llvm-svn: 29322
 2006-07-27 02:05:13 +00:00
Nate Begeman 787565024a Support jump tables when in PIC relocation model 
llvm-svn: 29318
 2006-07-27 01:13:04 +00:00
Jim Laskey c169b8798f Prevent creation of MachineDebugInfo for intel unless it is darwin. RC842. 
llvm-svn: 29317
 2006-07-27 01:12:23 +00:00
Evan Cheng 23a21c19d9 New entry. 
llvm-svn: 29310
 2006-07-26 21:49:52 +00:00
Chris Lattner 9e56e5c003 Rename RelocModel::PIC to PIC_, to avoid conflicts with -DPIC. 
llvm-svn: 29307
 2006-07-26 21:12:04 +00:00
Evan Cheng f6acb34d23 - Refactor the code that resolve basic block references to a TargetJITInfo 
method.
- Added synchronizeICache() to TargetJITInfo. It is called after each block
  of code is emitted to flush the icache. This ensures correct execution
  on targets that have separate dcache and icache.
- Added PPC / Mac OS X specific code to do icache flushing.

llvm-svn: 29276
 2006-07-25 20:40:54 +00:00
Evan Cheng 66ed41cac1 Can't commute shufps. The high / low parts elements come from different vectors. 
llvm-svn: 29275
 2006-07-25 20:25:40 +00:00
Rafael Espindola 8902fd702b implement function calling of functions with up to 4 arguments 
llvm-svn: 29274
 2006-07-25 20:17:20 +00:00
Evan Cheng c0577648c0 Done. 
llvm-svn: 29262
 2006-07-21 23:07:23 +00:00
Rafael Espindola 976c93a110 implemented sub 
correctly update the stack pointer in the prologue and epilogue

llvm-svn: 29244
 2006-07-21 12:26:16 +00:00
Evan Cheng 74065bedf2 This opt is now handled in DAG combine. 
llvm-svn: 29243
 2006-07-21 08:26:46 +00:00
Evan Cheng 4cf0238720 A splat of a vector constant of all zero or all one is the vector constant. 
llvm-svn: 29234
 2006-07-20 23:09:47 +00:00
Evan Cheng f98bc5288e Missing a space. 
llvm-svn: 29233
 2006-07-20 22:52:28 +00:00
Evan Cheng 683b966485 Clean up. 
llvm-svn: 29228
 2006-07-20 21:37:39 +00:00
Evan Cheng 8a881f2309 New entry. 
llvm-svn: 29215
 2006-07-19 21:29:30 +00:00
Jim Laskey 181fb1c4d7 Do once flag never set to true. 
llvm-svn: 29214
 2006-07-19 19:33:08 +00:00
Jim Laskey 7c860afec6 Tidy up a few things. 
llvm-svn: 29213
 2006-07-19 19:32:06 +00:00
Jim Laskey 18debc21db Reduce size of routine. Shrinks .o by 37%. 
llvm-svn: 29210
 2006-07-19 17:53:32 +00:00
Chris Lattner 4f8eb5ccaf bswapped load/store instructions are only availble in indexed addressing form. 
As such, use xoaddr (indexed only), not xaddr for address selection.

This fixes CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll, a crash compiling lencod.

llvm-svn: 29208
 2006-07-19 17:15:36 +00:00
Jim Laskey 5ba7c23cdd Bug#834 ICE (crash in code generator?) when building PCH . 
Missing Darwin check in Intel ATT ASM printer.

llvm-svn: 29204
 2006-07-19 11:54:50 +00:00
Evan Cheng 968a0b0309 Misc. new entry. 
llvm-svn: 29202
 2006-07-19 06:06:24 +00:00
Evan Cheng 02d8836cd5 INC / DEC instructions have shorter code size than ADD32ri8, etc. 
llvm-svn: 29194
 2006-07-19 00:27:29 +00:00
Evan Cheng c767acd25a Add code size to target instruction use it as the 3rd isel sorting tie-breaker. 
llvm-svn: 29193
 2006-07-19 00:24:41 +00:00
Rafael Espindola bf3a17cd32 initial prologue and epilogue implementation. Need to define add and sub before finishing it :-) 
llvm-svn: 29175
 2006-07-18 17:00:30 +00:00
Chris Lattner b00b6c2e86 Make the implicit def instructions look like other instrs. 
llvm-svn: 29174
 2006-07-18 16:33:26 +00:00
Rafael Espindola 75269be065 skeleton of a lowerCall implementation for ARM 
llvm-svn: 29159
 2006-07-16 01:02:57 +00:00
Chris Lattner e1758d4cef Remove what little AIX support we have. It has never been tested and isn't 
complete.

llvm-svn: 29156
 2006-07-15 01:24:23 +00:00
Chris Lattner 2e1d01541a Add an out-of-line virtual method for X86DwarfWriter to give it a home. 
llvm-svn: 29153
 2006-07-14 23:05:05 +00:00
Chris Lattner 96aecb5d76 Add missing PPC64 extload/truncstores 
llvm-svn: 29140
 2006-07-14 04:42:02 +00:00
Chris Lattner 950dffaed6 Add a note 
llvm-svn: 29139
 2006-07-14 04:07:29 +00:00
Chris Lattner 077b86a078 Another fix in the rotate encodings, needed when the first two operands are not 
the same.

llvm-svn: 29136
 2006-07-13 21:52:41 +00:00
Chris Lattner b42a945fd2 Print negative immediates as negative values instead of large constants 
when using the immshifted addressing mode.

llvm-svn: 29130
 2006-07-12 23:24:02 +00:00
Chris Lattner dd57ac4871 Fix encoding of rotates, such as rldicl 
llvm-svn: 29128
 2006-07-12 22:08:13 +00:00
Chris Lattner 5b17dee741 Implement PPC64 relocations types 
llvm-svn: 29125
 2006-07-12 21:23:20 +00:00
Chris Lattner 1ec5e73b32 An overaggressive #ifdef allows a function to fall off the bottom of the 
function instead of returning a value.  This sometimes allowed the ppc32 jit
to be used in 64-bit mode.

llvm-svn: 29123
 2006-07-12 20:42:10 +00:00
Chris Lattner c8db10725b Add information preventing several register class constraints from working. 
This implements PR828 and CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll

llvm-svn: 29118
 2006-07-12 16:59:49 +00:00
Chris Lattner 6e662083d9 The PPC64 JIT needs register numbers to encode instructions. 
llvm-svn: 29114
 2006-07-11 20:53:55 +00:00
Evan Cheng d5a086ab12 Emit inc / dec of registers as one byte instruction. 
llvm-svn: 29110
 2006-07-11 19:49:49 +00:00
Jim Laskey f7300b2706 It was pointed out that DEBUG() is only available with -debug. 
llvm-svn: 29106
 2006-07-11 18:25:13 +00:00
Jim Laskey c3d341ea98 Ensure that dump calls that are associated with asserts are removed from 
non-debug build.

llvm-svn: 29105
 2006-07-11 17:58:07 +00:00
Rafael Espindola 185c5c2bdf add the memri memory operand 
this makes it possible for ldr instructions with non-zero immediate

llvm-svn: 29103
 2006-07-11 11:36:48 +00:00
Chris Lattner 298ef37e02 Implement the inline asm 'A' constraint. This implements PR825 and 
CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll

llvm-svn: 29101
 2006-07-11 02:54:03 +00:00
Chris Lattner 71227c23b1 In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones. 
llvm-svn: 29096
 2006-07-11 00:48:23 +00:00
Evan Cheng 32860f42bb New entry. 
llvm-svn: 29091
 2006-07-10 21:42:16 +00:00
Evan Cheng 79cf9a5342 Fixed stack objects do not specify alignments, but their offsets are known. 
Use that information when doing the transformation to merge multiple loads
into a 128-bit load.

llvm-svn: 29090
 2006-07-10 21:37:44 +00:00
Chris Lattner a7976d329e Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps 
into i16/i32 load/stores.

llvm-svn: 29089
 2006-07-10 20:56:58 +00:00
Chris Lattner 9aabc1e16f Mark internal function static 
llvm-svn: 29085
 2006-07-10 19:53:12 +00:00
Rafael Espindola e40a7e2aa2 create the raddr addressing mode that matches any register and the frame index 
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot

llvm-svn: 29079
 2006-07-10 01:41:35 +00:00
Evan Cheng af5ae57333 Fix a typo that causes 2006-07-07-ComputeMaskedBits.ll to fail. 
llvm-svn: 29072
 2006-07-07 21:37:21 +00:00
Evan Cheng 5987cfb7b1 X86 target specific DAG combine: turn build_vector (load x), (load x+4), 
(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).

e.g.

__m128 test(float a, float b, float c, float d) {
  return _mm_set_ps(d, c, b, a);
}

_test:
        movups 4(%esp), %xmm0
        ret

llvm-svn: 29042
 2006-07-07 08:33:52 +00:00
Chris Lattner 59b6e8a683 Undisable ppc64 jit 
llvm-svn: 29011
 2006-07-06 17:10:42 +00:00
Evan Cheng 0441746468 Added option -code-model to set code model (only used in 64-bit) mode. Valid 
values include small, kernel, medium, large, and default.

llvm-svn: 29009
 2006-07-06 01:53:36 +00:00
Evan Cheng 0261242aa6 Reorg. No functionality change. 
llvm-svn: 28999
 2006-07-05 22:17:51 +00:00
Evan Cheng 41816100f4 Fix JIT on non MacOS X i386 systems. 
llvm-svn: 28992
 2006-07-05 07:09:13 +00:00
Andrew Lenharth 01078dc60b These are already implemented 
llvm-svn: 28990
 2006-07-03 18:00:29 +00:00
Andrew Lenharth 042f5076ed 0 offsets for memory operands 
llvm-svn: 28989
 2006-07-03 17:57:34 +00:00
Evan Cheng 390922f979 Should just use xorps to clear XMM registers for all data types. pxor is also one byte longer. 
llvm-svn: 28984
 2006-06-29 18:04:54 +00:00
Evan Cheng 28a95491d9 Let X86CompilationCallback pass previous frame and return address to X86CompilationCallback2. Remove alloca hack. 
llvm-svn: 28982
 2006-06-29 01:48:36 +00:00
Evan Cheng fa9e60895b Add shift and rotate by 1 instructions / patterns. 
llvm-svn: 28980
 2006-06-29 00:36:51 +00:00
Evan Cheng fc8cdda070 Always use xorps to clear XMM registers. 
llvm-svn: 28979
 2006-06-29 00:34:23 +00:00
Evan Cheng 56737d4fe3 Move .literal4 and .literal8 support into AsmPrinter.cpp 
llvm-svn: 28978
 2006-06-29 00:33:06 +00:00
Chris Lattner 0cc5907728 Hide x86 symbols 
llvm-svn: 28976
 2006-06-28 23:27:49 +00:00
Chris Lattner 996795b0dd Use hidden visibility to make symbols in an anonymous namespace get 
dropped.  This shrinks libllvmgcc.dylib another 67K

llvm-svn: 28975
 2006-06-28 23:17:24 +00:00
Chris Lattner 2f8c2d8ef2 shrink libllvmgcc.dylib another 25K 
llvm-svn: 28971
 2006-06-28 22:00:36 +00:00
Evan Cheng 87813744ba Doh. 
llvm-svn: 28963
 2006-06-28 17:56:43 +00:00
Evan Cheng 0687b04455 Oops. Need to keep CP index. 
llvm-svn: 28958
 2006-06-28 07:55:24 +00:00
Evan Cheng 7f88856d95 Darwin puts float and double literal constants into literal4 and literal8 sections. 
llvm-svn: 28957
 2006-06-28 07:35:41 +00:00
Andrew Lenharth a53a22e5fe this case isn't handled 
llvm-svn: 28948
 2006-06-27 23:19:14 +00:00
Rafael Espindola f6f5aff038 handle the "mov reg1, reg2" case in isMoveInstr 
llvm-svn: 28945
 2006-06-27 21:52:45 +00:00
Chris Lattner ca9c488528 Don't match 64-bit bitfield inserts into rlwimi's. todo add rldimi. :) 
llvm-svn: 28944
 2006-06-27 21:08:52 +00:00
Chris Lattner f882c54505 Fix ppc64 jump tables 
llvm-svn: 28941
 2006-06-27 20:46:17 +00:00
Evan Cheng 2aed9ebded Remove dead code. 
llvm-svn: 28938
 2006-06-27 20:34:14 +00:00
Chris Lattner 82ab3e21b1 Print stubs for external globals right. 
llvm-svn: 28936
 2006-06-27 20:20:53 +00:00
Chris Lattner 8aed3cc46b Implement 64-bit select, bswap, etc. 
llvm-svn: 28935
 2006-06-27 20:14:52 +00:00
Chris Lattner a2af3f47ea Add a pattern for i64 sra. Print 8-byte units with a space between the .quad 
and the data

llvm-svn: 28934
 2006-06-27 20:07:26 +00:00
Chris Lattner db9a95b775 Fix rewriting frame offsets with ixaddr instructions, which implicitly shift 
the offset two bits to the left.

llvm-svn: 28933
 2006-06-27 18:55:49 +00:00
Chris Lattner a07410c95b PPC doesn't have bit converts to/from i64 
llvm-svn: 28932
 2006-06-27 18:40:08 +00:00
Chris Lattner 3b5873456e Add 64-bit MTCTR so that indirect calls work. 
llvm-svn: 28931
 2006-06-27 18:36:44 +00:00
Chris Lattner e27d51e0d8 Fix an incorrect store pattern. This fixes em3d. 
llvm-svn: 28930
 2006-06-27 18:22:50 +00:00
Chris Lattner d48ce27532 Implement 64-bit undef, sub, shl/shr, srem/urem 
llvm-svn: 28929
 2006-06-27 18:18:41 +00:00
Chris Lattner cb5a84f446 Use i32 for shift amounts instead of i64. This gets bisort working. 
llvm-svn: 28927
 2006-06-27 17:34:57 +00:00
Chris Lattner f7fd88356a Add zextload from i32 -> i64, with this, perimeter works. 
llvm-svn: 28926
 2006-06-27 17:30:08 +00:00
Chris Lattner 1df0839067 Print darwin stub stuff correctly in 64-bit mode. With this, treeadd works in 
ppc64 mode!

llvm-svn: 28923
 2006-06-27 01:02:25 +00:00
Chris Lattner 9a40cca40f Fix variable shadowing issue 
llvm-svn: 28922
 2006-06-27 00:10:13 +00:00
Chris Lattner 97b3da1519 Implement a bunch of 64-bit cleanliness work. With this, treeadd builds (but 
doesn't work right).

llvm-svn: 28921
 2006-06-27 00:04:13 +00:00
Chris Lattner 7ecbd301b1 Rearrange compares, add ADDI8, add sext from 32-to-64 bit register 
llvm-svn: 28920
 2006-06-26 23:53:10 +00:00
Chris Lattner ec78cade34 Improve PPC64 calling convention support 
llvm-svn: 28919
 2006-06-26 22:48:35 +00:00
Chris Lattner b6a65f4661 Remove two more definitions 
llvm-svn: 28918
 2006-06-26 22:47:37 +00:00
Chris Lattner 86e6046515 remove two unused instructions. 
llvm-svn: 28917
 2006-06-26 22:44:13 +00:00
Evan Cheng 38c5aee959 Simplify X86CompilationCallback: always align to 16-byte boundary; don't save EAX/EDX if unnecessary. 
llvm-svn: 28910
 2006-06-24 08:36:10 +00:00
Jim Laskey a7b2bd5997 Add and sort "sections" in debug lines. This always stepping through 
code in sections other than ".text", including weak sections like ctors and
dtors.

llvm-svn: 28909
 2006-06-23 12:51:53 +00:00
Evan Cheng 0c9b90aba3 Eliminate unneeded parameter. 
llvm-svn: 28907
 2006-06-22 00:02:55 +00:00
Evan Cheng fc1b27dad1 variable_ops instructions such as call can have any number of operands. 
llvm-svn: 28906
 2006-06-21 23:37:07 +00:00
Andrew Lenharth 680ac12e53 Add memory operand and int regs 
llvm-svn: 28896
 2006-06-21 15:42:36 +00:00
Andrew Lenharth b0316eada6 inline asm, at least for floats 
llvm-svn: 28895
 2006-06-21 13:37:27 +00:00
Andrew Lenharth 336313ce3d fix argument problem 
llvm-svn: 28893
 2006-06-21 01:00:43 +00:00
Chris Lattner dc38e6f322 Correct returns of 64-bit values, though they seemed to work before... 
llvm-svn: 28892
 2006-06-21 00:34:03 +00:00
Chris Lattner 1f1b096142 Make these predicates correct in 64-bit mode too. 
llvm-svn: 28890
 2006-06-20 23:21:20 +00:00
Chris Lattner 52a956da52 Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file 
llvm-svn: 28889
 2006-06-20 23:18:58 +00:00
Chris Lattner 5705d4d519 remove unused flag 
llvm-svn: 28888
 2006-06-20 23:15:07 +00:00
Chris Lattner 9d65f3507e add some logical ops 
llvm-svn: 28887
 2006-06-20 23:11:59 +00:00
Chris Lattner 7a856a6d88 remove some unused patterns 
llvm-svn: 28886
 2006-06-20 23:11:36 +00:00
Chris Lattner d881f8257b Add some more immediate patterns. This allows us to compile: 
void test6() {
  Y = 0xABCD0123BCDE4567;
}

into:

_test6:
        lis r2, -21555
        lis r3, ha16(_Y)
        ori r2, r2, 291
        rldicr r2, r2, 32, 31
        oris r2, r2, 48350
        ori r2, r2, 17767
        std r2, lo16(_Y)(r3)
        blr

llvm-svn: 28885
 2006-06-20 23:03:01 +00:00
Chris Lattner 9834ad2fc6 Instead of li/xoris use li/oris. Note that this doesn't work if bit 15 is 
set, so disable the pattern in that case.

llvm-svn: 28884
 2006-06-20 22:38:59 +00:00
Chris Lattner 7e742e46ac Add some 64-bit logical ops. 
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation.  For example, we now compile this:

static unsigned long long Y;
void test3() {
  Y = 0xF0F00F00;
}

into:

_test3:
        li r2, 3840
        lis r3, ha16(_Y)
        xoris r2, r2, 61680
        std r2, lo16(_Y)(r3)
        blr

GCC produces:

_test3:
        li r0,0
        lis r2,ha16(_Y)
        ori r0,r0,61680
        sldi r0,r0,16
        ori r0,r0,3840
        std r0,lo16(_Y)(r2)
        blr

llvm-svn: 28883
 2006-06-20 22:34:10 +00:00
Evan Cheng 164a221b65 __i386__, __i386, etc. are not defined for x86-64. Use __x86_64__. 
llvm-svn: 28881
 2006-06-20 22:11:12 +00:00
Chris Lattner d6e160d14d 64-bit bugfix: 0xFFFF0000 cannot be formed with a single lis. 
llvm-svn: 28880
 2006-06-20 21:39:30 +00:00
Chris Lattner 2d4e8f7e86 Add some patterns for globals, so we can now compile this: 
static unsigned long long X, Y;
void test1() {
  X = Y;
}

into:

_test1:
        lis r2, ha16(_Y)
        lis r3, ha16(_X)
        ld r2, lo16(_Y)(r2)
        std r2, lo16(_X)(r3)
        blr

llvm-svn: 28879
 2006-06-20 21:23:06 +00:00
Chris Lattner 868a75bec6 Remove some now-unneeded casts from instruction patterns. With the casts 
removed, tblgen produces identical output to with them in.

llvm-svn: 28867
 2006-06-20 00:39:56 +00:00
Chris Lattner 94d18df658 Add some patterns for ppc64 
llvm-svn: 28866
 2006-06-20 00:38:36 +00:00
Chris Lattner dbec49d574 Remove some ugly now-redundant casts. 
llvm-svn: 28864
 2006-06-20 00:25:29 +00:00
Chris Lattner 55594634d7 Fix some mismatched type constraints 
llvm-svn: 28862
 2006-06-20 00:12:37 +00:00
Evan Cheng cd58e9d8b9 Minor clean up. 
llvm-svn: 28860
 2006-06-19 19:25:30 +00:00
Rafael Espindola a88966fd5e initial implementation of ARMRegisterInfo::eliminateFrameIndex 
fixes test/Regression/CodeGen/ARM/ret_arg5.ll

llvm-svn: 28854
 2006-06-18 00:08:07 +00:00
Evan Cheng a54b9643aa A new entry. 
llvm-svn: 28848
 2006-06-17 00:45:49 +00:00
Chris Lattner 49cadab385 Implement the getPointerRegClass method, which is required for the ptr_rc 
magic to work.

llvm-svn: 28847
 2006-06-17 00:01:04 +00:00
Evan Cheng d2e9a67cd9 Later models likely to have Yonah like attributes. 
llvm-svn: 28843
 2006-06-16 21:58:49 +00:00
Chris Lattner 638ee4ee15 Upgrade some load/store instructions to use the proper addressing mode stuff. 
llvm-svn: 28841
 2006-06-16 21:29:41 +00:00
Chris Lattner e8fe5e2bf4 In 64-bit mode, addr mode operands use G8RC instead of GPRC. 
llvm-svn: 28840
 2006-06-16 21:29:03 +00:00
Chris Lattner a5190ae7a9 fix some assumptions that pointers can only be 32-bits. With this, we can 
now compile:

static unsigned long X;
void test1() {
  X = 0;
}

into:

_test1:
        lis r2, ha16(_X)
        li r3, 0
        stw r3, lo16(_X)(r2)
        blr

Totally amazing :)

llvm-svn: 28839
 2006-06-16 21:01:35 +00:00
Chris Lattner b429983988 Split 64-bit instructions out into a separate .td file 
llvm-svn: 28838
 2006-06-16 20:22:01 +00:00
Chris Lattner 61d703183e Force 64-bit register availability in 64-bit mode. For real. 
llvm-svn: 28837
 2006-06-16 20:05:06 +00:00
Chris Lattner a7d9db2fa5 Remove the -darwin and -aix llc options, inferring darwinism and aixism from 
the target triple & subtarget info.  woo.

llvm-svn: 28835
 2006-06-16 18:50:48 +00:00
Chris Lattner f3b5b92e58 Don't pass target name into TargetData anymore, it is never used or needed. 
Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.

llvm-svn: 28830
 2006-06-16 18:22:52 +00:00
Chris Lattner 7f043b52ff Remove ctor with each piece specifyable (which causes overload ambiguities), 
add a new init method.

llvm-svn: 28828
 2006-06-16 18:11:26 +00:00
Chris Lattner 16682fff2b Document the subtarget features better, make sure that 64-bit mode, 64-bit 
support, and 64-bit register use are all consistent with each other.

Add a new "IsPPC" feature, to distinguish ppc32 vs ppc64 targets, use this
to configure TargetData differently.  This not makes ppc64 blow up on lots
of stuff :)

llvm-svn: 28825
 2006-06-16 17:50:12 +00:00
Chris Lattner a35f306740 Rename some subtarget features. A CPU now can *have* 64-bit instructions, 
can in 32-bit mode we can choose to optionally *use* 64-bit registers.

llvm-svn: 28824
 2006-06-16 17:34:12 +00:00
Chris Lattner 0c4aa14deb First baby step towards ppc64 support. This adds a new -march=ppc64 backend 
that is currently just like ppc32 :)

llvm-svn: 28813
 2006-06-16 01:37:27 +00:00
Chris Lattner cb29586ce4 Add a note that Nate noticed. 
llvm-svn: 28808
 2006-06-15 21:33:31 +00:00
Jim Laskey 19f964e048 1. Support standard dwarf format (was bootstrapping in Apple format.) 
2. Add vector support.

llvm-svn: 28807
 2006-06-15 20:51:43 +00:00
Evan Cheng 66f0e09313 Vector extract / insert index operand should have ptr type. 
llvm-svn: 28798
 2006-06-15 08:19:05 +00:00
Evan Cheng 94bb93f8f7 Type of extract_element index operand should be iPTR. 
llvm-svn: 28797
 2006-06-15 08:18:06 +00:00
Evan Cheng de7156f12c Type of vector extract / insert index operand should be iPTR. 
llvm-svn: 28796
 2006-06-15 08:14:54 +00:00
Evan Cheng c8734381ac X86 call instructions can take variable number of operands. Parameters of 
vector types are passed via XMM registers.

llvm-svn: 28789
 2006-06-14 22:24:55 +00:00
Chris Lattner 37c1c44c14 add a note 
llvm-svn: 28787
 2006-06-14 21:26:18 +00:00
Evan Cheng ca25486603 Add argument registers to the end of call operand list (partial fix). 
llvm-svn: 28783
 2006-06-14 18:17:40 +00:00