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5946 Commits

Author SHA1 Message Date
Chris Lattner f11327daab more notes 
llvm-svn: 30598
 2006-09-25 17:12:14 +00:00
Andrew Lenharth 5e2bacd6be Fix jump tables to match gcc (and the ABI and whatnot) 
llvm-svn: 30594
 2006-09-24 19:46:56 +00:00
Andrew Lenharth 783a4a9d86 Add support for other relocation bases to jump tables, as well as custom asm directives 
llvm-svn: 30593
 2006-09-24 19:45:58 +00:00
Andrew Lenharth 68324f8f85 jump table note 
llvm-svn: 30591
 2006-09-24 13:13:10 +00:00
Evan Cheng 1da0ab2f58 Delete dead code; fix 80 col violations. 
llvm-svn: 30583
 2006-09-22 21:43:59 +00:00
Rafael Espindola 72d4c070c0 add a note 
llvm-svn: 30581
 2006-09-22 11:36:17 +00:00
Nate Begeman d31efd190f Fold AND and ROTL more often 
llvm-svn: 30577
 2006-09-22 05:01:56 +00:00
Rafael Espindola 7b700e517a more condition codes 
llvm-svn: 30567
 2006-09-21 13:06:26 +00:00
Rafael Espindola 0c71a5adc8 if a constant can't be an immediate, add it to the constant pool 
llvm-svn: 30566
 2006-09-21 11:29:52 +00:00
Chris Lattner 08a8ccaaf1 implemented 
llvm-svn: 30559
 2006-09-21 06:14:54 +00:00
Chris Lattner 1c18c0db79 Fit in 80-cols 
llvm-svn: 30556
 2006-09-21 05:46:00 +00:00
Nick Lewycky c68bbef874 Fix compile error. 
llvm-svn: 30553
 2006-09-21 02:08:31 +00:00
Anton Korobeynikov 3c5b3df6a0 Adding codegeneration for StdCall & FastCall calling conventions 
llvm-svn: 30549
 2006-09-20 22:03:51 +00:00
Andrew Lenharth ccdaecc448 Account for pseudo-ops correctly 
llvm-svn: 30548
 2006-09-20 20:08:52 +00:00
Chris Lattner a81a75c390 The DarwinAsmPrinter need not check for isDarwin. createPPCAsmPrinterPass 
should create the right asmprinter subclass.

llvm-svn: 30542
 2006-09-20 17:12:19 +00:00
Chris Lattner 8597a2fc4e Wrap some darwin'isms with isDarwin checks. 
llvm-svn: 30541
 2006-09-20 17:07:15 +00:00
Andrew Lenharth f007f21c8a catch constants more often 
llvm-svn: 30534
 2006-09-20 15:05:49 +00:00
Andrew Lenharth 97a4e99aff clarify with test case 
llvm-svn: 30531
 2006-09-20 14:48:00 +00:00
Andrew Lenharth e2d138a462 Add Note 
llvm-svn: 30530
 2006-09-20 14:40:01 +00:00
Chris Lattner fba9e8f422 item done 
llvm-svn: 30518
 2006-09-20 06:41:56 +00:00
Chris Lattner 27d8985a71 add a note 
llvm-svn: 30515
 2006-09-20 06:32:10 +00:00
Chris Lattner f62f090ea1 This is already done 
llvm-svn: 30512
 2006-09-20 04:59:33 +00:00
Chris Lattner da9b1a9322 Improve PPC64 equality comparisons like PPC32 comparisons. 
llvm-svn: 30510
 2006-09-20 04:33:27 +00:00
Chris Lattner aa3926b7ea Two improvements: 
1. Codegen this comparison:
     if (X == 0x8000)

as:

        cmplwi cr0, r3, 32768
        bne cr0, LBB1_2 ;cond_next

instead of:

        lis r2, 0
        ori r2, r2, 32768
        cmpw cr0, r3, r2
        bne cr0, LBB1_2 ;cond_next


2. Codegen this comparison:
      if (X == 0x12345678)

as:

        xoris r2, r3, 4660
        cmplwi cr0, r2, 22136
        bne cr0, LBB1_2 ;cond_next

instead of:

        lis r2, 4660
        ori r2, r2, 22136
        cmpw cr0, r3, r2
        bne cr0, LBB1_2 ;cond_next

llvm-svn: 30509
 2006-09-20 04:25:47 +00:00
Chris Lattner ab33d350a7 Add a note that we should match rlwnm better 
llvm-svn: 30508
 2006-09-20 03:59:25 +00:00
Chris Lattner 601b86513d Legalize is no longer limited to cleverness with just constant shift amounts. 
Allow it to be clever when possible and fall back to the gross code when needed.

This allows us to compile:

long long foo1(long long X, int C) {
  return X << (C|32);
}
long long foo2(long long X, int C) {
  return X << (C&~32);
}

to:
_foo1:
        rlwinm r2, r5, 0, 27, 31
        slw r3, r4, r2
        li r4, 0
        blr


        .globl  _foo2
        .align  4
_foo2:
        rlwinm r2, r5, 0, 27, 25
        subfic r5, r2, 32
        slw r3, r3, r2
        srw r5, r4, r5
        or r3, r3, r5
        slw r4, r4, r2
        blr

instead of:

_foo1:
        ori r2, r5, 32
        subfic r5, r2, 32
        addi r6, r2, -32
        srw r5, r4, r5
        slw r3, r3, r2
        slw r6, r4, r6
        or r3, r3, r5
        slw r4, r4, r2
        or r3, r3, r6
        blr


        .globl  _foo2
        .align  4
_foo2:
        rlwinm r2, r5, 0, 27, 25
        subfic r5, r2, 32
        addi r6, r2, -32
        srw r5, r4, r5
        slw r3, r3, r2
        slw r6, r4, r6
        or r3, r3, r5
        slw r4, r4, r2
        or r3, r3, r6
        blr

llvm-svn: 30507
 2006-09-20 03:47:40 +00:00
Rafael Espindola fa7217f970 fix header 
add comments
untabify

llvm-svn: 30486
 2006-09-19 16:41:40 +00:00
Rafael Espindola f7d4a9900c Implement a MachineFunctionPass to fix the mul instruction 
llvm-svn: 30485
 2006-09-19 15:49:25 +00:00
Chris Lattner b94df039c0 item done 
llvm-svn: 30483
 2006-09-19 06:19:03 +00:00
Chris Lattner 3c48ea54ee Fold the PPCISD shifts when presented with 0 inputs. This occurs for code 
like:
long long test(long long X, int Y) {
  return 1ULL << Y;
}
long long test2(long long X, int Y) {
  return -1LL << Y;
}

which we used to compile to:

_test:
        li r2, 1
        subfic r3, r5, 32
        li r4, 0
        addi r6, r5, -32
        srw r3, r2, r3
        slw r4, r4, r5
        slw r6, r2, r6
        or r3, r4, r3
        slw r4, r2, r5
        or r3, r3, r6
        blr
_test2:
        li r2, -1
        subfic r3, r5, 32
        addi r6, r5, -32
        srw r3, r2, r3
        slw r4, r2, r5
        slw r2, r2, r6
        or r3, r4, r3
        or r3, r3, r2
        blr

Now we produce:

_test:
        li r2, 1
        addi r3, r5, -32
        subfic r4, r5, 32
        slw r3, r2, r3
        srw r4, r2, r4
        or r3, r4, r3
        slw r4, r2, r5
        blr
_test2:
        li r2, -1
        subfic r3, r5, 32
        addi r6, r5, -32
        srw r3, r2, r3
        slw r4, r2, r5
        slw r2, r2, r6
        or r3, r4, r3
        or r3, r3, r2
        blr

llvm-svn: 30479
 2006-09-19 05:22:59 +00:00
Andrew Lenharth f23e3bfcb2 A pass to remove the worst of the replay trap offenders, and as a bonus, align basic blocks when it is free to do so 
llvm-svn: 30467
 2006-09-18 19:44:29 +00:00
Andrew Lenharth 3aa3ad780e Jump tables on Alpha 
llvm-svn: 30463
 2006-09-18 18:01:03 +00:00
Chris Lattner 523dbc5c19 add a note. Our 64-bit shifts are ~30% slower than gcc's 
llvm-svn: 30457
 2006-09-18 05:36:54 +00:00
Chris Lattner 4a13d3b391 This is closer to what we really want. 
llvm-svn: 30451
 2006-09-18 04:54:35 +00:00
Anton Korobeynikov 6f7072c66a Added some eye-candy for Subtarget type checking 
Added X86 StdCall & FastCall calling conventions. Codegen will follow.

llvm-svn: 30446
 2006-09-17 20:25:45 +00:00
Anton Korobeynikov 0ab01ff6e2 Small fixes for supporting dll* linkage types 
llvm-svn: 30441
 2006-09-17 13:06:18 +00:00
Chris Lattner f7e3478745 add a note noticed through source inspection 
llvm-svn: 30418
 2006-09-16 23:57:51 +00:00
Chris Lattner 63b113f68c add a note 
llvm-svn: 30406
 2006-09-16 03:30:19 +00:00
Chris Lattner c9dc375d3e add a nate note 
llvm-svn: 30399
 2006-09-15 20:31:36 +00:00
Evan Cheng f8464da015 Remove a unnecessary check. 
llvm-svn: 30382
 2006-09-14 23:55:02 +00:00
Chris Lattner 2aa98e0363 add a note 
llvm-svn: 30377
 2006-09-14 20:56:30 +00:00
Anton Korobeynikov d61d39ec53 Adding dllimport, dllexport and external weak linkage types. 
DLL* linkages got full (I hope) codegeneration support in C & both x86
assembler backends.
External weak linkage added for future use, we don't provide any
codegeneration, etc. support for it.

llvm-svn: 30374
 2006-09-14 18:23:27 +00:00
Chris Lattner 1463377ddb add note about switch lowering 
llvm-svn: 30308
 2006-09-13 23:37:16 +00:00
Evan Cheng 92e5113d48 Skip over first operand when determining REX prefix for two-address code. 
llvm-svn: 30300
 2006-09-13 19:07:28 +00:00
Chris Lattner 971e33930d Turn X < 0 -> TEST X,X js 
llvm-svn: 30294
 2006-09-13 17:04:54 +00:00
Chris Lattner 0c9ae46c5f The sense of this branch was inverted :( 
llvm-svn: 30293
 2006-09-13 16:56:12 +00:00
Rafael Espindola 3130a756ef add shifts to addressing mode 1 
llvm-svn: 30291
 2006-09-13 12:09:43 +00:00
Chris Lattner 706dd3e0d4 Fix a regression in the 32-bit port from the 64-bit port landing. 
We now compile CodeGen/X86/lea-2.ll into:

_test:
        movl 4(%esp), %eax
        movl 8(%esp), %ecx
        leal -5(%ecx,%eax,4), %eax
        ret

instead of:

_test:
        movl 4(%esp), %eax
        leal (,%eax,4), %eax
        addl 8(%esp), %eax
        addl $4294967291, %eax
        ret

llvm-svn: 30288
 2006-09-13 04:45:25 +00:00
Chris Lattner e413fea6ac new note 
llvm-svn: 30286
 2006-09-13 04:19:50 +00:00
Chris Lattner 3496710f25 new note 
llvm-svn: 30285
 2006-09-13 03:54:54 +00:00
Chris Lattner 7a627676be Compile X > -1 -> text X,X; js dest 
This implements CodeGen/X86/jump_sign.ll.

llvm-svn: 30283
 2006-09-13 03:22:10 +00:00
Evan Cheng 9a083a4121 Reflects MachineConstantPoolEntry changes. 
llvm-svn: 30279
 2006-09-12 21:04:05 +00:00
Chris Lattner cfb2c32724 add a note 
llvm-svn: 30271
 2006-09-12 06:36:01 +00:00
Chris Lattner 8b4de218d9 Testcase noticed from PR906 
llvm-svn: 30269
 2006-09-11 23:00:56 +00:00
Chris Lattner 6e7286f72a add compilable testcase 
llvm-svn: 30268
 2006-09-11 22:57:51 +00:00
Rafael Espindola c7829d62c0 implement SRL and MUL 
llvm-svn: 30262
 2006-09-11 19:24:19 +00:00
Rafael Espindola bccf9c2f1b add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1 
llvm-svn: 30261
 2006-09-11 19:23:32 +00:00
Rafael Espindola e45a79a9e2 partial implementation of the ARM Addressing Mode 1 
llvm-svn: 30252
 2006-09-11 17:25:40 +00:00
Rafael Espindola ecb0d686f8 call AsmPrinter::doInitialization in ARMAsmPrinter::doInitialization 
llvm-svn: 30246
 2006-09-11 12:49:38 +00:00
Evan Cheng 21a75acc3e Updates. 
llvm-svn: 30245
 2006-09-11 05:35:17 +00:00
Evan Cheng 9e77d9a96b Update README file. 
llvm-svn: 30244
 2006-09-11 05:25:15 +00:00
Evan Cheng 4259a0f654 X86ISD::CMP now produces a chain as well as a flag. Make that the chain 
operand of a conditional branch to allow load folding into CMP / TEST
instructions.

llvm-svn: 30241
 2006-09-11 02:19:56 +00:00
Nate Begeman a0d95a8da9 Behold, more work on relocations. Things are looking pretty good now. 
llvm-svn: 30240
 2006-09-10 23:03:44 +00:00
Anton Korobeynikov fbee8bfe48 Removed unnecessary Mangler creation. 
llvm-svn: 30239
 2006-09-10 21:17:03 +00:00
Chris Lattner fdb3a75942 Add cbe support for powi 
llvm-svn: 30226
 2006-09-09 06:17:12 +00:00
Nate Begeman 69df6132d7 First pass at supporting relocations. Relocations are written correctly to 
the file now, however the relocated address is currently wrong.  Fixing
that will require some deep pondering.

llvm-svn: 30207
 2006-09-08 22:42:09 +00:00
Evan Cheng de33f66286 Fixed a FuseTwoAddrInst() bug: consider GlobalAddress and JumpTableIndex 
in addition to immediate operands.

llvm-svn: 30205
 2006-09-08 21:08:13 +00:00
Rafael Espindola d11fb5d13b implement shl and sra 
llvm-svn: 30191
 2006-09-08 17:36:23 +00:00
Chris Lattner 6c003a7c2d Use __USER_LABEL_PREFIX__ to get the prefix added by the current host. 
llvm-svn: 30190
 2006-09-08 17:03:56 +00:00
Rafael Espindola 4443c7d60a add the eor (xor) instruction 
llvm-svn: 30189
 2006-09-08 16:59:47 +00:00
Jim Laskey 177405376c Missing tab 
llvm-svn: 30188
 2006-09-08 13:06:56 +00:00
Rafael Espindola 778769aafb implement unconditional branches 
fix select.ll

llvm-svn: 30186
 2006-09-08 12:47:03 +00:00
Evan Cheng 7348403d42 Remove TEST64mr. It's same as TEST64rm since and is commutative. 
llvm-svn: 30178
 2006-09-08 06:56:55 +00:00
Evan Cheng 11b0a5dbd4 Committing X86-64 support. 
llvm-svn: 30177
 2006-09-08 06:48:29 +00:00
Nate Begeman c9db83306f We actually do support object file writing, so don't return true (error) 
llvm-svn: 30173
 2006-09-08 03:42:15 +00:00
Evan Cheng 89c5d04b9b - Identify a vector_shuffle that can be turned into an undef, e.g. 
shuffle V1, <undef>, <undef, undef, 4, 5>
- Fix some suspicious logic into LowerVectorShuffle that cause less than
  optimal code by failing to identify MOVL (move to lowest element of a
  vector).

llvm-svn: 30171
 2006-09-08 01:50:06 +00:00
Jim Laskey ae92ce8798 1. Remove condition on delete. 
2. Protect and outline createTargetAsmInfo.

3. Misc. kruft.

llvm-svn: 30169
 2006-09-07 23:39:26 +00:00
Chris Lattner 2785d55446 add a new value for the command line optn 
llvm-svn: 30165
 2006-09-07 22:32:28 +00:00
Chris Lattner b9e0a9e82f Fix a cross-build issue. The asmsyntax shouldn't be affected by the build 
host, it should be affected by the target.  Allow the command line option to
override in either case.

llvm-svn: 30164
 2006-09-07 22:29:41 +00:00
Jim Laskey 261779bb45 Make target asm info a property of the target machine. 
llvm-svn: 30162
 2006-09-07 22:06:40 +00:00
Jim Laskey 0e83541f8b Break out target asm info into separate files. 
llvm-svn: 30161
 2006-09-07 22:05:02 +00:00
Chris Lattner dc4ff5311f Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patterns 
using test, which provides nice simplifications like:

-       movl %edi, %ecx
-       andl $2, %ecx
-       cmpl $0, %ecx
+       testl $2, %edi
        je LBB1_11      #cond_next90

There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.

llvm-svn: 30156
 2006-09-07 20:33:45 +00:00
Chris Lattner 1b7f09cdf7 Some notes on better load folding we could do 
llvm-svn: 30155
 2006-09-07 20:32:01 +00:00
Evan Cheng a9411c0977 Consistency. 
llvm-svn: 30152
 2006-09-07 19:03:48 +00:00
Jim Laskey c7abe471fe Make the x86 asm flavor part of the subtarget info. 
llvm-svn: 30146
 2006-09-07 12:23:47 +00:00
Evan Cheng 7f3f0973e6 Clean up. 
llvm-svn: 30140
 2006-09-07 01:17:57 +00:00
Evan Cheng 4c7a3fbdea Watch out for variable_ops instructions. 
llvm-svn: 30135
 2006-09-06 20:32:45 +00:00
Evan Cheng ac22e54131 Variable ops instructions may ignore the last few operands for code emission. 
llvm-svn: 30134
 2006-09-06 20:24:14 +00:00
Jim Laskey ef94ebb666 Oops - forgot to update banner. 
llvm-svn: 30131
 2006-09-06 19:21:41 +00:00
Jim Laskey 681ecbb3b3 Separate target specifc asm properties from asm printers. 
llvm-svn: 30127
 2006-09-06 18:35:33 +00:00
Jim Laskey a6211dcdad Separate target specific asm properties from the asm printers. 
llvm-svn: 30126
 2006-09-06 18:34:40 +00:00
Rafael Espindola abd8bcbe5e add the orr instruction 
llvm-svn: 30125
 2006-09-06 18:03:12 +00:00
Chris Lattner 2656932979 Bugfix to work with the two-addr changes that have been made in the tree recently 
llvm-svn: 30121
 2006-09-05 20:27:32 +00:00
Evan Cheng 7a150d3113 Fix a few dejagnu failures. e.g. fast-cc-merge-stack-adj.ll 
llvm-svn: 30113
 2006-09-05 08:32:49 +00:00
Evan Cheng 17c28b2e0e JIT encoding bug. 
llvm-svn: 30112
 2006-09-05 05:59:25 +00:00
Chris Lattner e3d2e1e41e Update the X86 JIT to make it work with the new two-addr changes. This also 
adds assertions that check to make sure every operand gets emitted.

llvm-svn: 30110
 2006-09-05 02:52:35 +00:00
Chris Lattner af23f9b5f6 Completely eliminate def&use operands. Now a register operand is EITHER a 
def operand or a use operand.

llvm-svn: 30109
 2006-09-05 02:31:13 +00:00
Chris Lattner 13a5dcddce Fix a long-standing wart in the code generator: two-address instruction lowering 
actually *removes* one of the operands, instead of just assigning both operands
the same register.  This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.

Changing this also gets rid of a bunch of hacky code in various places.

This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.

llvm-svn: 30108
 2006-09-05 02:12:02 +00:00
Andrew Lenharth 3852b2ce7e jmp_bufs are this big on alpha. 
llvm-svn: 30107
 2006-09-05 00:22:25 +00:00
Rafael Espindola 8386105f3f add support for returning 64bit values 
llvm-svn: 30103
 2006-09-04 19:05:01 +00:00
Chris Lattner 49c45d3a13 Fix some X86 JIT failures. This should really come from TargetJITInfo. 
llvm-svn: 30102
 2006-09-04 18:48:41 +00:00
Duraid Madina cf6749e4c0 add setJumpBufSize() and setJumpBufAlignment() to target-lowering. 
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example

llvm-svn: 30095
 2006-09-04 06:21:35 +00:00
Chris Lattner 12e97307a1 Completely rearchitect the interface between targets and the pass manager. 
This pass:

1. Splits TargetMachine into TargetMachine (generic targets, can be implemented
any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by
things using libcodegen and other support).
2. Instead of having each target fully populate the passmgr for file or JIT
   output, move all this to common code, and give targets hooks they can
   implement.
3. Commonalize the target population stuff between file emission and JIT
   emission.
4. All (native code) codegen stuff now happens in a FunctionPassManager, which
   paves the way for "fast -O0" stuff in the CFE later, and now LLC could
   lazily stream .bc files from disk to use less memory.
5. There are now many fewer #includes and the targets don't depend on the
   scalar xforms or libanalysis anymore (but codegen does).
6. Changing common code generator pass ordering stuff no longer requires
   touching all targets.
7. The JIT now has the option of "-fast" codegen or normal optimized codegen,
   which is now orthogonal to the fact that JIT'ing is being done.

llvm-svn: 30081
 2006-09-04 04:14:57 +00:00
Chris Lattner e8ce162969 Add accessor 
llvm-svn: 30080
 2006-09-04 04:08:58 +00:00
Chris Lattner 2f93c0fd33 remove #include 
llvm-svn: 30078
 2006-09-04 04:06:01 +00:00
Chris Lattner 0fc4541c67 Simplify target construction. 
llvm-svn: 30070
 2006-09-03 18:44:02 +00:00
Rafael Espindola 5328ba96e1 add the SETULT condition code 
llvm-svn: 30067
 2006-09-03 13:19:16 +00:00
Rafael Espindola c585b6919b add more condition codes 
llvm-svn: 30056
 2006-09-02 20:24:25 +00:00
Evan Cheng 2c4e0f120f Oops. Bad typo. Without the check of N1.hasOneUse() bad things can happen. 
Suppose the TokenFactor can reach the Op:

       [Load chain]
           ^
           |
         [Load]
         ^    ^
         |    |
        /      \-
       /         |
      /          [Op]
     /          ^ ^
     |        ..  |
     |       /    |
   [TokenFactor]  |
       ^          |
       |          |
        \        /
         \      /
         [Store]

If we move the Load below the TokenFactor, we would have created a cycle in
the DAG.

llvm-svn: 30040
 2006-09-01 22:52:28 +00:00
Chris Lattner bad9d2ee49 Use a couple of multiclass patterns to factor some integer ops. 
llvm-svn: 30039
 2006-09-01 22:28:02 +00:00
Chris Lattner 38e6d1d5af remove a bunch of comments 
llvm-svn: 30038
 2006-09-01 22:16:22 +00:00
Evan Cheng 6d464146d0 Minor asm fix. 
llvm-svn: 29965
 2006-08-29 22:14:48 +00:00
Evan Cheng b28800f4d5 Remove dead code. 
llvm-svn: 29962
 2006-08-29 21:42:58 +00:00
Evan Cheng dfb85155dc Don't performance load/op/store transformation if op produces a floating point 
or vector result. X86 does not have load/mod/store variants of those
instructions.

llvm-svn: 29957
 2006-08-29 18:37:37 +00:00
Evan Cheng 358b9ed98a - Enable x86 isel preprocessing by default unless -fast is specified. 
- Also disable isel load folding if -fast.

llvm-svn: 29956
 2006-08-29 18:28:33 +00:00
Jim Laskey 2eebe8b05e Handle callee saved registers in dwarf frame info (lead up to exception 
handling.)

llvm-svn: 29954
 2006-08-29 16:24:26 +00:00
Jim Laskey 82dc16c0a7 Tidy up options. 
llvm-svn: 29953
 2006-08-29 15:13:10 +00:00
Evan Cheng c07feb14b0 Avoid making unneeded load/mod/store transformation which can hurt performance. 
llvm-svn: 29952
 2006-08-29 06:44:17 +00:00
Nate Begeman 18f0329cfc Make ppc64 jit kinda work right. About 2/3 of Olden passes with this, 
there are clearly some encoding bugs lurking in there somewhere.

llvm-svn: 29949
 2006-08-29 02:30:59 +00:00
Evan Cheng 00884b51c5 On Mac, print jump table entries after the function to work around a linker issue. 
llvm-svn: 29946
 2006-08-28 22:14:16 +00:00
Evan Cheng 64a9e28846 Add an optional pass to preprocess the DAG before x86 isel to allow selecting more load/mod/store instructions. 
llvm-svn: 29943
 2006-08-28 20:10:17 +00:00
Reid Spencer e7141c8be6 For PR387: 
Close out this long standing bug by removing the remaining overloaded
virtual functions in LLVM. The -Woverloaded-virtual option is now turned on.

llvm-svn: 29934
 2006-08-28 01:02:49 +00:00
Chris Lattner 3d27be1333 s|llvm/Support/Visibility.h|llvm/Support/Compiler.h| 
llvm-svn: 29911
 2006-08-27 12:54:02 +00:00
Evan Cheng c3acfc0b10 Do not use getTargetNode() and SelectNodeTo() which takes more than 3 
SDOperand arguments. Use the variants which take an array and number instead.

llvm-svn: 29907
 2006-08-27 08:14:06 +00:00
Chris Lattner 4042e871ce Fix target matching weights, so that ppc-darwin modules are codegen with the 
ppc target, not the itanium target, when run on an itanium machine.
This should fix the CodeGen/PowerPC regtest failures on itanium.

llvm-svn: 29903
 2006-08-26 21:33:05 +00:00
Evan Cheng 34b70eea5c SelectNodeTo now returns a SDNode*. 
llvm-svn: 29901
 2006-08-26 08:00:10 +00:00
Evan Cheng 61413a3d72 Select() no longer require Result operand by reference. 
llvm-svn: 29898
 2006-08-26 05:34:46 +00:00
Evan Cheng ab8297f92d Match tblgen changes. 
llvm-svn: 29895
 2006-08-26 01:07:58 +00:00
Evan Cheng 2d48722e92 Match tblgen changes; clean up. 
llvm-svn: 29894
 2006-08-26 01:05:16 +00:00
Chris Lattner c664efe223 Give a good error message when we try to jit inline asm. 
llvm-svn: 29891
 2006-08-26 00:47:03 +00:00
Evan Cheng 1b200574ad Add a comment. 
llvm-svn: 29889
 2006-08-25 23:29:06 +00:00
Evan Cheng d7572fb234 Encode pc-relative conditional branch offset as pc+(num of bytes / 4). The 
asm printer will print it as offset*4. e.g. bne cr0, $+8.

The PPC code emitter was expecting the offset to be number of instructions, not
number of bytes. This fixes a whole bunch of JIT failures.

llvm-svn: 29885
 2006-08-25 21:54:44 +00:00
Jim Laskey d51ce619c3 Fix some comments. 
llvm-svn: 29880
 2006-08-25 19:40:59 +00:00
Rafael Espindola 98dc23fd1f use @ for comments 
store LR in an arbitrary stack slot
add support for writing varargs functions

llvm-svn: 29876
 2006-08-25 17:55:16 +00:00
Chris Lattner ac40a81253 We compile this into: 
_swap_16:
        slwi r2, r3, 24
        rlwimi r2, r3, 8, 8, 15
        srwi r3, r2, 16
        blr

now.

llvm-svn: 29864
 2006-08-24 23:06:02 +00:00
Chris Lattner fb6bc15d5d Owen implemented this. 
llvm-svn: 29863
 2006-08-24 23:03:33 +00:00
Rafael Espindola 29e4875f57 add the "eq" condition code 
implement a movcond instruction

llvm-svn: 29857
 2006-08-24 17:19:08 +00:00
Rafael Espindola fe03fe9bf4 create a generic bcond instruction that has a conditional code argument 
llvm-svn: 29856
 2006-08-24 16:13:15 +00:00
Rafael Espindola e08b9853cc initial support for branches 
llvm-svn: 29854
 2006-08-24 13:45:55 +00:00
Nate Begeman 3cb3921a60 Initial checkin of the Mach-O emitter. There's plenty of fixmes, but it 
does emit linkable .o files in very simple cases.

llvm-svn: 29850
 2006-08-23 21:08:52 +00:00
Rafael Espindola ea500426d6 add a README.txt 
llvm-svn: 29814
 2006-08-22 12:22:46 +00:00
Rafael Espindola d0dee77718 initial support for select 
llvm-svn: 29802
 2006-08-21 22:00:32 +00:00
Rafael Espindola 9d77f9fd24 add the and instruction 
llvm-svn: 29793
 2006-08-21 13:58:59 +00:00
Rafael Espindola 8a675a5d09 call computeRegisterProperties 
llvm-svn: 29780
 2006-08-20 01:49:49 +00:00
Chris Lattner 60f1eecd3a Constify some methods. Patch provided by Anton Vayvod, thanks! 
llvm-svn: 29756
 2006-08-17 22:00:08 +00:00
Chris Lattner 162f2d5d4c Revert this patch, the front-end has been fixed to make it unneccesary. 
llvm-svn: 29752
 2006-08-17 18:43:24 +00:00
Chris Lattner dfb3f0591d 'g' is handled by the front-end. 
llvm-svn: 29751
 2006-08-17 18:12:28 +00:00
Andrew Lenharth 4a063c5ffb Fix handling of 'g'. Closes 883 
llvm-svn: 29750
 2006-08-17 17:50:12 +00:00
Rafael Espindola c3ed77e1b9 add a "load effective address" 
llvm-svn: 29748
 2006-08-17 17:09:40 +00:00
Andrew Lenharth 1c3210d08d Add the 'c' constraint as needed by the linux kernel 
llvm-svn: 29747
 2006-08-17 16:07:50 +00:00