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46 Commits

Author SHA1 Message Date
Hrvoje Varga dbe4d96b4f [mips][microMIPS] Implement DBITSWAP, DLSA and LWUPC and add tests for AUI instructions 
Differential Revision: https://reviews.llvm.org/D16452

llvm-svn: 280909
 2016-09-08 07:41:43 +00:00
Hrvoje Varga f0ed16eae5 [mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations 
Differential Revision: https://reviews.llvm.org/D22667

llvm-svn: 279429
 2016-08-22 12:17:59 +00:00
Hrvoje Varga 846bdb746d [mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructions 
Differential Revision: https://reviews.llvm.org/D22347

llvm-svn: 277719
 2016-08-04 11:22:52 +00:00
Simon Dardis 273fc26b79 [mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases 
Add the instruction alias sgtu (register form only), two operand forms of
s[rl]l and sra, and missing single/two operand forms of dnegu/neg.

Reviewers: dsanders

Differential Revision: https://reviews.llvm.org/D22752

llvm-svn: 276736
 2016-07-26 09:13:46 +00:00
Zlatko Buljan cba9f80ba8 [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support 
Differential Revision: http://reviews.llvm.org/D18824

llvm-svn: 275050
 2016-07-11 07:41:56 +00:00
Hrvoje Varga 24b975dc66 [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions 
Differential Revision: http://reviews.llvm.org/D16625

llvm-svn: 273850
 2016-06-27 08:23:28 +00:00
Hrvoje Varga f1e0a03d08 [mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions 
Differential Revision: http://reviews.llvm.org/D16917

llvm-svn: 272876
 2016-06-16 07:06:25 +00:00
Zlatko Buljan d2ed9c6c2c [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and NOR instructions 
Differential Revision: http://reviews.llvm.org/D16719

llvm-svn: 272764
 2016-06-15 07:46:24 +00:00
Zlatko Buljan e663e34e79 [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions 
Differential Revision: http://reviews.llvm.org/D18352

llvm-svn: 270030
 2016-05-19 07:31:28 +00:00
Zlatko Buljan 6afea51a58 [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add CodeGen support 
Differential Revision: http://reviews.llvm.org/D15418

llvm-svn: 269883
 2016-05-18 06:54:59 +00:00
Hrvoje Varga aeb1fe8f20 [mips][micromips] Implement DSBH, DSHD, DSLL, DSLL32, DSLLV, DSRA, DSRA32 and DSRAV instructions 
Differential Revision: http://reviews.llvm.org/D16800

llvm-svn: 269169
 2016-05-11 11:17:04 +00:00
Zlatko Buljan ba553a6e0a [mips][microMIPS] Implement LWP and SWP instructions 
Differential Revision: http://reviews.llvm.org/D10640

llvm-svn: 268896
 2016-05-09 08:07:28 +00:00
Zlatko Buljan 31c9ebe281 [mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions 
Differential Revision: http://reviews.llvm.org/D15744

llvm-svn: 268714
 2016-05-06 08:24:14 +00:00
Zlatko Buljan 4807f829b4 [mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions 
Differential Revision: http://reviews.llvm.org/D19857

llvm-svn: 268491
 2016-05-04 12:02:12 +00:00
Zlatko Buljan de0bbe6d1c [mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU instructions 
Differential Revision: http://reviews.llvm.org/D16676

llvm-svn: 267694
 2016-04-27 11:31:44 +00:00
Zlatko Buljan 29813620bc [mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions 
Differential Revision: http://reviews.llvm.org/D17989

llvm-svn: 267693
 2016-04-27 11:02:23 +00:00
Zlatko Buljan b43d4bcbd5 [mips][microMIPS] Revert commit r266977 
Commit r266977 was reason for failing LLVM test suite with error message: fatal error: error in backend: Cannot select: t17: i32 = rotr t2, t11 ...

llvm-svn: 267418
 2016-04-25 15:34:57 +00:00
Zlatko Buljan ae720dbbb6 [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructions 
Differential Revision: http://reviews.llvm.org/D18687

llvm-svn: 267114
 2016-04-22 06:44:34 +00:00
Zoran Jovanovic 9360c10a88 [mips][microMIPS] Implement ldpc instruction 
Differential Revision: http://reviews.llvm.org/D15009

llvm-svn: 266990
 2016-04-21 14:32:12 +00:00
Zlatko Buljan dd4151504a [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions 
Differential Revision: http://reviews.llvm.org/D18855

llvm-svn: 266980
 2016-04-21 11:32:40 +00:00
Zlatko Buljan d370f440e2 [mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL instructions and add tests for LWM32 and SWM32 
Differential Revision: http://reviews.llvm.org/D19150

llvm-svn: 266977
 2016-04-21 11:01:51 +00:00
Zlatko Buljan 58d6a959be [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions 
Differential Revision: http://reviews.llvm.org/D17137

This patch was reverted after the revertion of dependant patch http://reviews.llvm.org/D17068.
There was the problem with test-suite failure.
The problem is hopefully solved with dependant patch so this patch is commited again.

llvm-svn: 266179
 2016-04-13 08:02:26 +00:00
Zlatko Buljan 53a037f5cc [mips][microMIPS] Add CodeGen support for ADD, ADDIU*, ADDU* and DADD* instructions 
Differential Revision: http://reviews.llvm.org/D16454

llvm-svn: 265772
 2016-04-08 07:27:26 +00:00
Zoran Jovanovic 2b7cc5a4ae [mips][microMIPS] Revert commits r264245 and r264248. 
Commit r264245 was the reason for failing tests in LLVM test suite.
Commit r264248 depends on the first one.

llvm-svn: 265249
 2016-04-02 23:06:13 +00:00
Zlatko Buljan 6221be8e46 [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructions 
Differential Revision: http://reviews.llvm.org/D17334

llvm-svn: 265002
 2016-03-31 08:51:24 +00:00
Zlatko Buljan 94af4cbcf4 [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions 
Differential Revision: http://reviews.llvm.org/D17137

llvm-svn: 264248
 2016-03-24 09:22:45 +00:00
Hrvoje Varga 2cb74ac3c3 [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions 
Differential Revision: http://reviews.llvm.org/D17328

llvm-svn: 264246
 2016-03-24 08:02:09 +00:00
Hrvoje Varga 46458d0bcc [mips][microMIPS] Implement DINSU, DINSM, DINS instructions 
Differential Revision: http://reviews.llvm.org/D16181

llvm-svn: 261860
 2016-02-25 12:53:29 +00:00
Zlatko Buljan f034021443 [mips][microMIPS] Implement TLBINV and TLBINVF instructions 
Differential Revision: http://reviews.llvm.org/D16849

llvm-svn: 261211
 2016-02-18 14:10:52 +00:00
Hrvoje Varga 02f99ea13d [mips][micromips] Written missing test for CEIL.L.S, CEIL.L.D, FLOOR.L.S and FLOOR.L.D instructions 
Differential Revision: http://reviews.llvm.org/D17192

llvm-svn: 260673
 2016-02-12 12:11:26 +00:00
Zlatko Buljan 5da2f6cd03 [mips][microMIPS] Implement DERET and DI instructions and check size operand for EXT and DEXT* instructions 
Differential Revision: http://reviews.llvm.org/D15570

llvm-svn: 256152
 2015-12-21 13:08:58 +00:00
Zlatko Buljan 48f1f39bfe Revert r254897 "[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions" 
Commited patch was intended to implement LH, LHE, LHU and LHUE instructions.
After commit test-suite failed with error message in the form of:
fatal error: error in backend: Cannot select: t124: i32,ch = load<LD2[%d](tbaa=<0x94acc48>), sext from i16> t0, t2, undef:i32
For that reason I decided to revert commit r254897 and make new patch which besides implementation and standard regression tests will also have dedicated tests (CodeGen) for the above error. 

llvm-svn: 255109
 2015-12-09 13:07:45 +00:00
Daniel Sanders 59d092f883 [mips][ias] Range check uimm6 operands and fix a bug this revealed. 
Summary:
We don't check the size operand on ext/dext*/ins/dins* yet because the
permitted range depends on the pos argument and we can't check that using
this mechanism.

The bug was that dextu/dinsu accepted 0..31 in the pos operand instead of 32..63.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D15190

llvm-svn: 255015
 2015-12-08 13:49:19 +00:00
Zlatko Buljan 1a01c15027 [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions 
Differential Revision: http://reviews.llvm.org/D9824

llvm-svn: 254897
 2015-12-07 08:29:31 +00:00
Hrvoje Varga e51b0e13f3 [mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt 
Differential Revision: http://reviews.llvm.org/D13885

llvm-svn: 254405
 2015-12-01 11:59:21 +00:00
Zlatko Buljan 797c2aec6b [mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions 
Differential Revision: http://reviews.llvm.org/D11406

llvm-svn: 252885
 2015-11-12 13:21:33 +00:00
Hrvoje Varga 3a3c4b8a39 [mips][microMIPS] Implement BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 instructions 
Differential Revision: http://reviews.llvm.org/D11292#inline-103143

llvm-svn: 250381
 2015-10-15 08:39:07 +00:00
Zoran Jovanovic 5a8dffc618 [mips][microMIPS] Implement JALRC16, JRCADDIUSP and JRC16 instructions 
Differential Revision: http://reviews.llvm.org/D11219

llvm-svn: 249317
 2015-10-05 14:00:09 +00:00
Zoran Jovanovic 2960f3a346 [mips][microMIPS] Implement CACHEE, WRPGPR and WSBH instructions 
Differential Revision: http://reviews.llvm.org/D10337

llvm-svn: 249004
 2015-10-01 12:49:27 +00:00
Zoran Jovanovic 7ba636cb4c [mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructions 
Differential Revision: http://reviews.llvm.org/D9658

llvm-svn: 247880
 2015-09-17 10:14:09 +00:00
Zoran Jovanovic 68be5f21a9 [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit LBU16, LHU16, LW16, LWGP and LWSP instructions 
Differential Revision: http://reviews.llvm.org/D10956

llvm-svn: 246987
 2015-09-08 08:25:34 +00:00
Zoran Jovanovic ada7091812 [mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions 
Differential Revision: http://reviews.llvm.org/D11181

llvm-svn: 246963
 2015-09-07 11:56:37 +00:00
Zoran Jovanovic 14f308e44f [mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, MAX.fmt, MIN.fmt, MAXA.fmt, MINA.fmt and CMP.condn.fmt instructions 
Differential Revision: http://reviews.llvm.org/D12141

llvm-svn: 246960
 2015-09-07 10:31:31 +00:00
Zoran Jovanovic 89ca2b982e [mips][microMIPS] Implement ADD.fmt, SUB.fmt, MOV.fmt, MUL.fmt, DIV.fmt, MADDF.fmt, MSUBF.fmt and NEG.fmt instructions 
Differential Revision: http://reviews.llvm.org/D11978

llvm-svn: 246919
 2015-09-05 09:25:30 +00:00
Zoran Jovanovic 56585d517b [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit ADDIUR1SP, ADDIUR2, ADDIUS5 and ADDIUSP instructions 
Differential Revision: http://reviews.llvm.org/D10955

llvm-svn: 245554
 2015-08-20 11:51:49 +00:00
Zoran Jovanovic 2fe8466f6e [mips][microMIPS] Implement DDIV, DMOD, DDIVU and DMODU instructions 
Differential Revision: http://reviews.llvm.org/D10953

llvm-svn: 245297
 2015-08-18 14:40:43 +00:00