2 Commits

Author	SHA1	Message	Date
Zoran Jovanovic	973405bec5	[mips] Addition of a third operand to the instructions [d]div, [d]divu ... Author: obucina Reviewers: dsanders Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register Differential Revision: http://reviews.llvm.org/D16888 llvm-svn: 269636	2016-05-16 08:57:59 +00:00
Daniel Sanders	3ebcaf6685	[mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler. ... Summary: Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11675 llvm-svn: 246763	2015-09-03 12:31:22 +00:00