Commit Graph

258377 Commits

Author SHA1 Message Date
Rui Ueyama ca7818ebca Update comment.
llvm-svn: 298403
2017-03-21 17:22:13 +00:00
Reid Kleckner f76a8ac5a9 Remove stray paren that got in while attempting to fix the build for AttributeList
llvm-svn: 298402
2017-03-21 17:15:50 +00:00
Adrian Prantl 4dc0324ff8 Revert 298388 and 298389 because they broke some AMDGPU tests.
llvm-svn: 298401
2017-03-21 17:14:30 +00:00
Krzysztof Parzyszek d033d1fd82 Recommit r298282 with fixes for memory allocation/deallocation
[Hexagon] Recognize polynomial-modulo loop idiom again

Regain the ability to recognize loops calculating polynomial modulo
operation. This ability has been lost due to some changes in the
preceding optimizations. Add code to preprocess the IR to a form
that the pattern matching code can recognize.

llvm-svn: 298400
2017-03-21 17:09:27 +00:00
Reid Kleckner a3e3715c3e Update for LLVM API rename of AttributeSet -> AttributeList
llvm-svn: 298399
2017-03-21 17:09:20 +00:00
Reid Kleckner 974a349bf8 Fix RST docs AttributeList heading underline
llvm-svn: 298398
2017-03-21 17:05:00 +00:00
Marek Olsak 5c7a61d221 AMDGPU: Buffer descriptor changes for GFX9
Reviewers: arsenm

Subscribers: qcolombet, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, dstuttard, tpr

Differential Revision: https://reviews.llvm.org/D31158

llvm-svn: 298397
2017-03-21 17:00:39 +00:00
Marek Olsak e22fdb9cac AMDGPU: Always use VGPR indexing on GFX9
Reviewers: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, dstuttard, tpr

Differential Revision: https://reviews.llvm.org/D31157

llvm-svn: 298396
2017-03-21 17:00:32 +00:00
Krzysztof Parzyszek 5e7f06f354 [Hexagon] Add -march=hexagon to a testcase
llvm-svn: 298395
2017-03-21 16:59:40 +00:00
Reid Kleckner de86482ce0 Update Clang for LLVM rename AttributeSet -> AttributeList
llvm-svn: 298394
2017-03-21 16:57:30 +00:00
Reid Kleckner b518054b87 Rename AttributeSet to AttributeList
Summary:
This class is a list of AttributeSetNodes corresponding the function
prototype of a call or function declaration. This class used to be
called ParamAttrListPtr, then AttrListPtr, then AttributeSet. It is
typically accessed by parameter and return value index, so
"AttributeList" seems like a more intuitive name.

Rename AttributeSetImpl to AttributeListImpl to follow suit.

It's useful to rename this class so that we can rename AttributeSetNode
to AttributeSet later. AttributeSet is the set of attributes that apply
to a single function, argument, or return value.

Reviewers: sanjoy, javed.absar, chandlerc, pete

Reviewed By: pete

Subscribers: pete, jholewinski, arsenm, dschuff, mehdi_amini, jfb, nhaehnle, sbc100, void, llvm-commits

Differential Revision: https://reviews.llvm.org/D31102

llvm-svn: 298393
2017-03-21 16:57:19 +00:00
Argyrios Kyrtzidis 3b25c91a9e [index/AST] Determine if a typedef shares a name and spelling location with its underlying tag type
In such a case, as when using the NS_ENUM macro, for indexing purposes treat the typedef as 'transparent',
meaning we treat its references as symbols of the underlying tag symbol.
Also provide a libclang API to check for such typedefs.

llvm-svn: 298392
2017-03-21 16:56:02 +00:00
Bruno Cardoso Lopes 08ebd61a80 [Modules] Find PrivateHeaders when looking into subframeworks
Fix the current parsing of subframeworks in modulemaps to lookup for
headers based on whether they are frameworks.

rdar://problem/30563982

llvm-svn: 298391
2017-03-21 16:43:51 +00:00
Matt Arsenault 5af82a7ae1 AMDGPU: Fix not including v2i16/v2f16 in register class
llvm-svn: 298390
2017-03-21 16:42:50 +00:00
Adrian Prantl 1db6486fb1 Don't compose DWARF expressions with multiple subregisters.
If a register location can only be described by a complex expression
(i.e., multiple subregisters) it doesn't safely compose with another
complex expression. For example, it is not possible to apply a
DW_OP_deref operation to multiple DW_OP_pieces.

llvm-svn: 298389
2017-03-21 16:37:39 +00:00
Adrian Prantl dabee8e57c DwarfExpression: Defer emitting DWARF register operations
until the rest of the expression is known.

This is still an NFC refactoring in preparation of a subsequent bugfix.

llvm-svn: 298388
2017-03-21 16:37:35 +00:00
Matt Arsenault f8fb605a68 AMDGPU: Fix asserting on 0 dmask for image intrinsics
Fold these to undef during lowering so users get eliminated.

llvm-svn: 298387
2017-03-21 16:32:17 +00:00
Matt Arsenault 964a848514 AMDGPU: Convert image intrinsic uses in tests
llvm-svn: 298386
2017-03-21 16:24:12 +00:00
Matt Arsenault dce313c3cf DAG: Fold bitcast/extract_vector_elt of undef to undef
Fixes not eliminating store when intrinsic is lowered to undef.

llvm-svn: 298385
2017-03-21 16:20:16 +00:00
Dmitry Vyukov 3bf24449b0 tsan: fix pie_no_aslr test
It failed on clang-cmake-aarch64-39vma.
Restrict it to x86_64 only.

llvm-svn: 298383
2017-03-21 15:37:48 +00:00
Chandler Carruth 985f1a9417 Revert r298274: "Use pthreads for thread-local lsan allocator cache on darwin"
This fixes a failure currently present on the upstream linux boxes (and
reproduces for me as well):
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/1130/steps/64-bit%20check-asan-dynamic/logs/stdio

llvm-svn: 298382
2017-03-21 15:31:15 +00:00
Simon Pilgrim 5e39cbaee5 Fix shufpd test name.
llvm-svn: 298381
2017-03-21 15:12:53 +00:00
Sanne Wouda 2409c6403d [ARM] [Assembler] Support negative immediates for A32, T32 and T16
Summary:
To support negative immediates for certain arithmetic instructions, the
instruction is converted to the inverse instruction with a negated (or inverted)
immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD
instruction.  However, "SUB r0, r1, #1" is equivalent.

These conversions are different from instruction aliases.  An alias maps
several assembler instructions onto one encoding.  A conversion, however, maps
an *invalid* instruction--e.g. with an immediate that cannot be represented in
the encoding--to a different (but equivalent) instruction.

Several instructions with negative immediates were being converted already, but
this was not systematically tested, nor did it cover all instructions.

This patch implements all possible substitutions for ARM, Thumb1 and
Thumb2 assembler and adds tests.  It also adds a feature flag
(-mattr=+no-neg-immediates) to turn these substitutions off.  This is
helpful for users who want their code to assemble to exactly what they
wrote.

Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin

Reviewed By: javed.absar

Subscribers: aadg, aemerson, llvm-commits

Differential Revision: https://reviews.llvm.org/D30571

llvm-svn: 298380
2017-03-21 14:59:17 +00:00
Yi Kong 019e1c4f99 Test commit access
Remove some trailing whitespaces.

llvm-svn: 298379
2017-03-21 14:49:19 +00:00
Dmitry Vyukov de033e6cdb tsan: support __ATOMIC_HLE_ACQUIRE/RELEASE flags
HLE flags can be combined with memory order in atomic operations.
Currently tsan runtime crashes on e.g. IsStoreOrder(mo) in atomic store
if any of these additional flags are specified.

Filter these flags out.
See the comment as to why it is safe.

llvm-svn: 298378
2017-03-21 14:28:55 +00:00
Sanjay Patel 00ece756c3 [InstCombine] auto-generate better checks; NFC
llvm-svn: 298377
2017-03-21 14:04:44 +00:00
Sanjay Patel 79379cae15 [x86] use PMOVMSK for vector-sized equality comparisons
We could do better by splitting any oversized type into whatever vector size the target supports, 
but I left that for future work if it ever comes up. The motivating case is memcmp() calls on 16-byte
structs, so I think we can wire that up with a TLI hook that feeds into this.

Differential Revision: https://reviews.llvm.org/D31156

llvm-svn: 298376
2017-03-21 13:50:33 +00:00
Pavel Labath e3ad2e2e73 Replace std::ofstream with llvm::raw_fd_ostream
Summary:
ofstream does not handle paths with non-ascii characters correctly on
windows, so I am switching these to llvm streams to fix that.

Reviewers: zturner, eugene

Subscribers: lldb-commits

Differential Revision: https://reviews.llvm.org/D31079

llvm-svn: 298375
2017-03-21 13:49:50 +00:00
Pavel Labath 1593086232 Remove ProcFileReader
This removes the last usage of ProcFileReader from NativeProcessLinux
and then deletes the class itself.

llvm-svn: 298374
2017-03-21 13:49:45 +00:00
Andrey Churbanov 435b419d26 Fixed intermittent hang on tests with "target teams if(0)" construct with no parallel inside.
Differential Revision: https://reviews.llvm.org/D29597

llvm-svn: 298373
2017-03-21 13:48:52 +00:00
Dmitry Vyukov ae9f13855b tsan: add test for pie/no aslr
Just ensure that such combination works.

llvm-svn: 298372
2017-03-21 13:44:01 +00:00
Ekaterina Romanova 6a5702a093 [DOXYGEN] Improvements to smmintrin.h and emmintrin.h intrinsics.
I made some small changes in smmintrin.h and emmintrin.h intrinsics.
 - changed some regular comments '//' into doxygen-style comments '///' where necessary
 - removed some trailing spaces in doxygen comments.

I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream.

llvm-svn: 298371
2017-03-21 13:34:06 +00:00
Simon Pilgrim 8bda035121 [X86][AVX] Tests showing missing SHUFPD + ZERO lowering
This lowers to SHUFPD if the input is zeroinitializer but not with a demanded elts optimized build vector.

llvm-svn: 298370
2017-03-21 13:30:40 +00:00
Egor Churaev 392a507103 [OpenCL] Added diagnostic for checking length of vector
Reviewers: Anastasia, cfe-commits

Reviewed By: Anastasia

Subscribers: bader, yaxunl

Differential Revision: https://reviews.llvm.org/D30937

llvm-svn: 298369
2017-03-21 13:20:57 +00:00
Valery Pykhtin fd4c410f4d [AMDGPU] Iterative scheduling infrastructure + minimal registry scheduler
Differential revision: https://reviews.llvm.org/D31046

llvm-svn: 298368
2017-03-21 13:15:46 +00:00
Volkan Keles 044e003203 [GlobalISel] Fix shufflevector tests
clang-lld-x86_64-2stage fails because of the order
of the instructions. `CHECK-DAG` directives should
fix the problem.

llvm-svn: 298367
2017-03-21 13:12:59 +00:00
Egor Churaev c217f37cb6 [OpenCL] Added implicit conversion rank for overloading functions with vector data type in OpenCL
Summary: I added a new rank to ImplicitConversionRank enum to resolve the function overload ambiguity with vector types. Rank of scalar types conversion is lower than vector splat. So, we can choose which function should we call. See test for more details.

Reviewers: Anastasia, cfe-commits

Reviewed By: Anastasia

Subscribers: bader, yaxunl

Differential Revision: https://reviews.llvm.org/D30816

llvm-svn: 298366
2017-03-21 12:55:55 +00:00
Sam Kolton f60ad58dad [ADMGPU] SDWA peephole optimization pass.
Summary:
First iteration of SDWA peephole.

This pass tries to combine several instruction into one SDWA instruction. E.g. it converts:
'''
    V_LSHRREV_B32_e32 %vreg0, 16, %vreg1
    V_ADD_I32_e32 %vreg2, %vreg0, %vreg3
    V_LSHLREV_B32_e32 %vreg4, 16, %vreg2
'''
Into:
'''
   V_ADD_I32_sdwa %vreg4, %vreg1, %vreg3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
'''

Pass structure:
    1. Iterate over machine instruction in basic block and try to apply "SDWA patterns" to each of them. SDWA patterns match machine instruction into either source or destination SDWA operand. E.g. ''' V_LSHRREV_B32_e32 %vreg0, 16, %vreg1''' is matched to source SDWA operand '''%vreg1 src_sel:WORD_1'''.
    2. Iterate over found SDWA operands and find instruction that could be potentially coverted into SDWA. E.g. for source SDWA operand potential instruction are all instruction in this basic block that uses '''%vreg0'''
    3. Iterate over all potential instructions and check if they can be converted into SDWA.
    4. Convert instructions to SDWA.

This review contains basic implementation of SDWA peephole pass. This pass requires additional testing fot both correctness and performance (no performance testing done).
There are several ways this pass can be improved:
    1. Make this pass work on whole function not only basic block. As I can see this can be done right now without changes to pass.
    2. Introduce more SDWA patterns
    3. Introduce mnemonics to limit when SDWA patterns should apply

Reviewers: vpykhtin, alex-t, arsenm, rampitec

Subscribers: wdng, nhaehnle, mgorny

Differential Revision: https://reviews.llvm.org/D30038

llvm-svn: 298365
2017-03-21 12:51:34 +00:00
Simon Pilgrim 60e924985c [X86][AVX512] Add _mm512_cvtsd_f64 and _mm512_cvtss_f32 intrinsics (PR32305)
Differential Revision: https://reviews.llvm.org/D31155

llvm-svn: 298364
2017-03-21 12:46:13 +00:00
Eric Liu 8bc2416414 [change-namespace] avoid adding leading '::' when possible.
Summary:
When changing namespaces, the tool adds leading "::" to references that need to
be fully-qualified, which would affect readability.

We avoid adding "::" when the symbol name does not conflict with the new
namespace name. For example, a symbol name "na::nb::X" conflicts with "ns::na"
since it would be resolved to "ns::na::nb::X" in the new namespace.

Reviewers: hokein

Reviewed By: hokein

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D30493

llvm-svn: 298363
2017-03-21 12:41:59 +00:00
Andrey Churbanov 3b939d070c Stride in distribute parallel for loops with no chunk size.
Patch by George Rokos.

Differential Revision: https://reviews.llvm.org/D24486

llvm-svn: 298362
2017-03-21 12:17:22 +00:00
Siddharth Bhat 44b6cb4e63 [DependenceInfo] change name Write to MustWrite to remove ambiguity [NFC]
"Write" is an overloaded term. In collectInfo() till buildFlow(), it is
used to mean "must writes". However, within the memory based analysis,
it is used to mean "both may and must writes". Renaming the Write
variable helps clarify this difference.

Reviewers: grosser

Tags: #polly

Differential Revision: https://reviews.llvm.org/D31181

llvm-svn: 298361
2017-03-21 11:54:08 +00:00
Andrea Di Biagio 7937be7dd3 [DebugInfo][X86] Teach Optimize LEAs pass to handle debug values
This patch fixes an issue in the Optimize LEAs pass where redundant LEAs were
not removed because they were being used by debug values. The debug values are
now ignored when determining whether LEAs are redundant.

For now the debug values for the redundant LEAs are marked as undefined,
effectively lost. The intention is for a follow up patch which will attempt to
preserve the debug values where possible.

Patch by Andrew Ng.

Differential Revision: https://reviews.llvm.org/D30835

llvm-svn: 298360
2017-03-21 11:36:21 +00:00
Artur Pilipenko 4cc6130f52 NFC. InstCombiner::visitFAdd extract LHSIntVal/RHSIntVal local variables
llvm-svn: 298359
2017-03-21 11:32:15 +00:00
Volkan Keles 47debaeef0 [GlobalISel] Move isTriviallyDead to Utils. NFC.
Make it accessible by the targets to avoid code duplication.

llvm-svn: 298358
2017-03-21 10:47:35 +00:00
Jonas Paulsson 54c7680e1f [DAGTypeLegalizer] Handle widening truncate to vector of i1.
Previously, PromoteIntRes_TRUNCATE() did not handle the case where
the operand needs widening, which resulted in llvm_unreachable().

This patch adds the needed handling, along with a test case.

Review: Eli Friedman, Simon Pilgrim.
https://reviews.llvm.org/D31077

llvm-svn: 298357
2017-03-21 10:24:14 +00:00
David Green da21170c49 [ConstantFolding] Fix to prevent constant folding having to repeatedly scan operands. NFCI
After the loop unroll threshold was increased in r295538, very
large constant expressions can be created. This prevents them
from having to be recursively scanned, leading to a compile
time blow-up.

Differential Revision: https://reviews.llvm.org/D30689

llvm-svn: 298356
2017-03-21 10:17:39 +00:00
Laszlo Nagy 57db7c6860 [scan-build-py] reuse command line output parameter for report directory
Differential Revision: https://reviews.llvm.org/D30861

llvm-svn: 298355
2017-03-21 10:15:18 +00:00
George Rimar 1ec03e46a7 [ELF] - Detemplate InputSection::getRelocatedSection(). NFC.
llvm-svn: 298353
2017-03-21 09:13:27 +00:00
Tobias Grosser 29eaa16b7e Update isl to isl-0.18-395-g77701b3
This is a normal maintenance update.

llvm-svn: 298352
2017-03-21 09:12:11 +00:00