maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
289,082 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

6 Commits

Author SHA1 Message Date
Shiva Chen 53489ada12 [RISCV] Add ELFObjectFileBase::getRISCVFeatures let llvm-objdump could get RISCV target feature 
llvm-objdump could get C feature by ELF::EF_RISCV_RVC e_flag,
so then we don't have to add -mattr=+c on the command line.

Differential Revision: https://reviews.llvm.org/D42629

llvm-svn: 324058
 2018-02-02 06:01:02 +00:00
Ana Pazos 1b57c7a0f4 [RISCV] Fixed setting predicates for compressed instructions. 
Summary:
Fixed setting predicates for compressed instructions.
Some instructions were being generated with C extension
enabled only, without proper checks for the other
required extensions like F, D and 32 and 64-bit target checks.
Affected instructions:
C_FLD, C_FLW, C_LD, C_FSD, C_FSW, C_SD,
C_JAL, C_ADDIW, C_SUBW, C_ADDW,
C_FLDSP, C_FLWSP, C_LDSP, C_FSDSP, C_FSWSP, C_SDSP

Reviewers: asb, shiva0217

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, llvm-commits

Differential Revision: https://reviews.llvm.org/D42132

llvm-svn: 322876
 2018-01-18 18:54:05 +00:00
Alex Bradbury 0ad4c265d7 [RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero 
c.slli/c.srli/c.srai allow a 5-bit shift in RV32C and a 6-bit shift in RV64C.
This patch adds uimmlog2xlennonzero to reflect this constraint as well as
tests.

Differential Revision: https://reviews.llvm.org/D41216

Patch by Shiva Chen.

llvm-svn: 320799
 2017-12-15 10:20:51 +00:00
Alex Bradbury 59136ffab1 [RISCV] Enable emission of alias instructions by default 
This patch switches the default for -riscv-no-aliases to false
and updates all affected MC and CodeGen tests. As recommended in
D41071, MC tests use the canonical instructions and the CodeGen
tests use the aliases.

Additionally, for the f and d instructions with rounding mode,
the tests for the aliased versions are moved and tightened such
that they can actually detect if alias emission is enabled.
(see D40902 for context)

Differential Revision: https://reviews.llvm.org/D41225

Patch by Mario Werner.

llvm-svn: 320797
 2017-12-15 09:47:01 +00:00
Alex Bradbury 60714f98ba [RISCV] MC layer support for the remaining RVC instructions 
Differential Revision: https://reviews.llvm.org/D40003

Patch by Shiva Chen.

llvm-svn: 320558
 2017-12-13 09:32:55 +00:00
Alex Bradbury 9f6aec4b7a [RISCV] MC layer support for load/store instructions of the C (compressed) extension 
Differential Revision: https://reviews.llvm.org/D40001
    
Patch by Shiva Chen.

llvm-svn: 320037
 2017-12-07 12:50:32 +00:00