2f8e146ad3
[AMDGPU][MC][GFX9] Added instructions s_mul_hi_*32, s_lshl*_add_u32
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See bugs
36841: https://bugs.llvm.org/show_bug.cgi?id=36841
36842: https://bugs.llvm.org/show_bug.cgi?id=36842
Differential Revision: https://reviews.llvm.org/D45251
Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 329562
2018-04-09 13:10:33 +00:00
36b4b0bed7
AMDGPU: Remove -mcpu=SI
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Leftover from before amdgcn/r600 split.
llvm-svn: 310277
2017-08-07 18:30:35 +00:00
5714860ee4
[AMDGPU][MC] Enabled constants for src operands of s_cbranch_g_fork
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Fixed bug 32619: https://bugs.llvm.org//show_bug.cgi?id=32619
Reviewers: artem.tamazov, vpykhtin
Differential Revision: https://reviews.llvm.org/D31973
llvm-svn: 300318
2017-04-14 11:52:26 +00:00
1bdcef7697
[AMDGPU] Assembler: refactor parsing of modifiers and immediates. Allow modifiers for imms.
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Reviewers: nhaustov, tstellarAMD
Subscribers: kzhuravl, arsenm
Differential Revision: http://reviews.llvm.org/D20166
llvm-svn: 270415
2016-05-23 09:59:02 +00:00
cb9dddb1d7
[AMDGPU] Assembler: Update SOP* tests
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Add VI encodings.
Reformat sopp.s to match style of other files.
Differential Revision: http://reviews.llvm.org/D18084
llvm-svn: 263540
2016-03-15 07:44:57 +00:00
2a62b3c244
[AMDGPU] Fix operands of S_BFE_U64 and S_BFM_B64
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src1 of s_bfe_u64 is 32-bit (same as s_bfe_i64).
src0 and src1 of s_bfm_b64 are 32-bit.
Update tests.
Review: http://reviews.llvm.org/D17480
Reviewers: arsenm
llvm-svn: 261621
2016-02-23 09:19:14 +00:00
192b282bf3
AMDGPU: Define correct number of SGPRs
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There are actually 104 so 2 were missing.
More assembler tests with high register number tuples
will be included in later patches.
llvm-svn: 251999
2015-11-03 22:39:50 +00:00
45bb48ea19
R600 -> AMDGPU rename
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llvm-svn: 239657
2015-06-13 03:28:10 +00:00
Dmitry Preobrazhensky