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3 Commits

Author SHA1 Message Date
Matt Arsenault 7b6475568d AMDGPU: Add definitions for scalar store instructions 
Also add glc bit to the scalar loads since they exist on VI
and change the caching behavior.

This currently has an assembler bug where the glc bit is incorrectly
accepted on SI/CI which do not have it.

llvm-svn: 285463
 2016-10-28 21:55:15 +00:00
Sam Kolton 1bdcef7697 [AMDGPU] Assembler: refactor parsing of modifiers and immediates. Allow modifiers for imms. 
Reviewers: nhaustov, tstellarAMD

Subscribers: kzhuravl, arsenm

Differential Revision: http://reviews.llvm.org/D20166

llvm-svn: 270415
 2016-05-23 09:59:02 +00:00
Matt Arsenault 68802d3177 AMDGPU: Disallow s[102:103] on VI in assembler 
llvm-svn: 252142
 2015-11-05 03:11:27 +00:00