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Author SHA1 Message Date
Kyle Butt f6c61ef64d CodeGen: Power: Add lowering for shifts of v1i128. 
When legalizing vector operations on vNi128, they will be split to v1i128
because that is a legal type on ppc64, but then the compiler will crash in
selection dag because it fails to select for these operations. This patch fixes
shift operations. Logical shift right and left shift can be performed in the
vector unit, but algebraic shift right requires being split.

Differential Revision: https://reviews.llvm.org/D32774

llvm-svn: 303307
 2017-05-17 21:54:41 +00:00
Ehsan Amiri a538b0f023 Adding -verify-machineinstrs option to PowerPC tests 
Currently we have a number of tests that fail with -verify-machineinstrs.
To detect this cases earlier we add the option to the testcases with the
exception of tests that will currently fail with this option. PR 27456 keeps
track of this failures.

No code review, as discussed with Hal Finkel.

llvm-svn: 277624
 2016-08-03 18:17:35 +00:00
Dan Gohman c8054d90fb Eliminate more uses of llvm-as and llvm-dis. 
llvm-svn: 81293
 2009-09-09 00:09:15 +00:00
Dan Gohman 8d2ead2e34 Add support for lowering 128-bit shifts on ppc64. 
llvm-svn: 48029
 2008-03-07 20:36:53 +00:00