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4 Commits

Author SHA1 Message Date
Daniel Sanders 1b1e25b7c5 [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. 
llvm-svn: 191498
 2013-09-27 10:08:31 +00:00
Daniel Sanders e508704b52 [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics) 
llvm-svn: 191301
 2013-09-24 14:02:15 +00:00
Daniel Sanders 2d999ebb84 [mips][msa] Summarize tests 
Adds a comment to the start of each test summarizing the area the test covers.

llvm-svn: 189465
 2013-08-28 10:02:29 +00:00
Jack Carter d12e837f05 [Mips][msa] Added the simple builtins (madd_q to xori) 
Includes:
madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su],
msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev,
pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al],
sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori

Patch by Daniel Sanders

llvm-svn: 188460
 2013-08-15 14:22:07 +00:00