1e3e8933ed
Another possible bug. Stopgap until we can autogenerate tables and
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constraint lengths.
Part of rdar://9037836 and rdar://9119939
llvm-svn: 132598
2011-06-03 22:09:12 +00:00
761a5d4280
Fix an off by one error.
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Part of rdar://9037836 and rdar://9119939
llvm-svn: 132590
2011-06-03 20:44:52 +00:00
354b2a25f3
Make the Uv constraint a memory operand. This doesn't solve the
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addressing mode problem mentioned in r132559.
Backend part of rdar://9037836 and part of rdar://9119939
llvm-svn: 132561
2011-06-03 17:24:37 +00:00
86585798af
Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol.
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rdar://9431157
llvm-svn: 132522
2011-06-03 01:13:19 +00:00
e5feef0fe1
During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def.
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Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint!
llvm-svn: 132483
2011-06-02 20:07:12 +00:00
690030c116
Allow bitcasts between valid types of the same size and vector
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types if the vector type is legal.
Fixes rdar://9306086
llvm-svn: 132420
2011-06-01 19:55:10 +00:00
7d84ece09b
On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.
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This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).
Take 2, now with more basic competence.
llvm-svn: 132295
2011-05-29 19:50:32 +00:00
e64371b932
I didn't mean to commit these residues of a personal project.
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llvm-svn: 132293
2011-05-29 19:41:56 +00:00
085d891d80
On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.
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This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).
llvm-svn: 132291
2011-05-29 19:39:04 +00:00
325110f30d
Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs
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to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.
llvm-svn: 132248
2011-05-28 04:07:29 +00:00
d00e8ad803
Implement the 'M' output modifier for arm inline asm. This is fairly
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register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.
rdar://9119939
llvm-svn: 132242
2011-05-28 01:40:44 +00:00
1d553a2cc4
Fix the remaining atomic intrinsics to use the right register classes on Thumb2,
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and add some basic tests for them.
llvm-svn: 132235
2011-05-27 23:54:00 +00:00
d23bfb8a7a
Make size computation less brittle.
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llvm-svn: 132222
2011-05-27 22:05:41 +00:00
2348f3133f
Make room for register allocation to improve.
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llvm-svn: 132213
2011-05-27 20:15:06 +00:00
518bcd0ef4
Don't use movw / movt for iOS static codegen for now to workaround some tools issues. rdar://9514789
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llvm-svn: 132211
2011-05-27 20:11:27 +00:00
97c9f84f68
Add iOS test
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llvm-svn: 132203
2011-05-27 19:04:21 +00:00
3a8d9625b0
And fix the test in r132194.
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llvm-svn: 132196
2011-05-27 18:14:28 +00:00
fe84bd659c
Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076
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llvm-svn: 132194
2011-05-27 18:02:04 +00:00
42ddaa10d3
During branch folding avoid inserting redundant DBG_VALUE machine instructions.
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llvm-svn: 132148
2011-05-26 21:47:59 +00:00
c70355195c
Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.
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The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).
rdar://9437928 .
llvm-svn: 132099
2011-05-25 23:49:02 +00:00
8c5e4192e6
Implement the 'm' modifier. Note that it only works for memory operands.
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Part of rdar://9119939
llvm-svn: 132081
2011-05-25 20:51:58 +00:00
3088e0a179
Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This
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fixes <rdar://problem/9495913>
llvm-svn: 132042
2011-05-25 04:45:27 +00:00
1b724948e9
Implement the arm 'L' asm modifier.
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Part of rdar://9119939
llvm-svn: 132024
2011-05-24 23:27:13 +00:00
b1dda56ac2
Implement the immediate part of the 'B' modifier.
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Part of rdar://9119939
llvm-svn: 132023
2011-05-24 23:15:43 +00:00
7617883ce3
Add support for the arm 'y' asm modifier.
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Fixes part of rdar://9444657
llvm-svn: 132011
2011-05-24 22:10:34 +00:00
bc90690b24
Fix <rdar://problem/9476260> by having tail calls always generate 32-bit branches
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in Darwin Thumb2 code. Tail calls are already disabled on Thumb1.
llvm-svn: 131894
2011-05-23 01:57:17 +00:00
4cd5187f5b
RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset accepts parameters (ptr, size, value) in a different order than GNU's memset (ptr, value, size), therefore the special lowering in AAPCS mode. Implementation by Evzen Muller.
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llvm-svn: 131868
2011-05-22 21:41:23 +00:00
1d11720ae4
Handle perfect shuffle case that generates a vrev for vectors of floats.
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Add test case.
llvm-svn: 131582
2011-05-18 21:44:54 +00:00
48b182c3a4
In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.
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Updated test case and reverted change to the PerfectShuffle Table.
llvm-svn: 131529
2011-05-18 06:42:21 +00:00
c7e291b354
vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case.
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llvm-svn: 131488
2011-05-17 20:48:40 +00:00
4edf17d91f
Teach LiveInterval::isZeroLength about null SlotIndexes.
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When instructions are deleted, they leave tombstone SlotIndex entries.
The isZeroLength method should ignore these null indexes.
This causes RABasic to sometimes spill a callee-saved register in the
abi-isel.ll test, so don't run that test with -regalloc=basic. Prioritizing
register allocation according to spill weight can cause more registers to be
used.
llvm-svn: 131436
2011-05-16 23:50:05 +00:00
9e56e51fab
Correction. Use explicit target triple in the test.
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llvm-svn: 131252
2011-05-12 21:55:34 +00:00
8a7beb80f0
Fixes a bug in the DAGCombiner. LoadSDNodes have two values (data, chain).
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If there is a store after the load node, then there is a chain, which means
that there is another user. Thus, asking hasOneUser would fail. Instead we
ask hasNUsesOfValue on the 'data' value.
llvm-svn: 131183
2011-05-11 14:40:50 +00:00
19c1a56287
Produce a __debug_frame section on darwin ARM when appropriate.
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llvm-svn: 131151
2011-05-10 21:04:45 +00:00
dd550305e6
Give this test an explicit register allocator, so that it can work even if
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the default register allocator is changed.
llvm-svn: 130883
2011-05-04 23:14:02 +00:00
2a40131f6b
SjLj EH could produce a machine basic block that legitimately has more than one
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landing pad as its successor.
SjLj exception handling jumps to the correct landing pad via a switch statement
that's generated right before code-gen. Loosen the constraint in the machine
instruction verifier to allow for this. Note, this isn't the most rigorous check
since we cannot determine where that switch statement came from. But it's
marginally better than turning this check off when SjLj exceptions are used.
<rdar://problem/9187612>
llvm-svn: 130881
2011-05-04 22:54:05 +00:00
e53ae508ec
This test fails on ARM. The test shouldn't explicitly specify alignment (and alignment 4 is wrong) and requires hard-float.
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llvm-svn: 130875
2011-05-04 21:57:44 +00:00
39ecf816c5
Do not emit location expression size twice.
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llvm-svn: 130854
2011-05-04 19:00:57 +00:00
51b35f7bb1
Fix a bunch of ARM tests to be register allocation independent.
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llvm-svn: 130800
2011-05-03 22:31:21 +00:00
93b5cdc5ab
Make the test less likely to fail with minor changes.
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llvm-svn: 130778
2011-05-03 19:09:32 +00:00
c5242b0e78
Remove test for iOS divmod function, since that is disabled for now.
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llvm-svn: 130769
2011-05-03 17:54:49 +00:00
168c9005b5
Add a few ARM coprocessor intrinsics. Testcases included
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llvm-svn: 130763
2011-05-03 17:29:22 +00:00
6136e94897
Add an unfolded offset field to LSR's Formula record. This is used to
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model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.
llvm-svn: 130743
2011-05-03 00:46:49 +00:00
edfabc9aad
Weekly fix of register allocation dependent unit tests.
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llvm-svn: 130567
2011-04-30 01:37:52 +00:00
4105ed1523
Make FastEmit_ri_ try a bit harder to succeed for supported operations; FastEmit_i can fail for non-Thumb2 ARM. Makes ARMSimplifyAddress work correctly, and reduces the number of fast-isel bailouts on non-Thumb ARM.
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llvm-svn: 130560
2011-04-29 23:34:52 +00:00
328bad02fa
Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns.
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llvm-svn: 130552
2011-04-29 22:48:03 +00:00
dd937843d3
Fix run-line, again. :(
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llvm-svn: 130540
2011-04-29 21:33:03 +00:00
86caced370
Re-committing r130454, which does not in fact break anything.
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Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
rdar://problem/9338332 .
llvm-svn: 130539
2011-04-29 21:22:56 +00:00
8d46b47787
Add trunc->branch support, this won't help with clang's i8->i1 truncations
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for bools, but is a start.
llvm-svn: 130534
2011-04-29 20:02:39 +00:00
517728b1ae
Revert r130454; apparently this doesn't actually work.
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llvm-svn: 130462
2011-04-28 23:55:14 +00:00
Eric Christopher