llvm-project

Commit Graph

Author	SHA1	Message	Date
Puyan Lotfi	43e94b15ea	Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922	2018-01-31 22:04:26 +00:00
Matthias Braun	88c8c9847d	AArch64/PEI: Do not add reserved regs to liveins We do not track liveness for reserved registers. It is unnecessary to add them to block livein lists. llvm-svn: 304059	2017-05-27 03:38:02 +00:00
Matthias Braun	b901d33461	LiveIntervalAnalysis: Calculate liveness even if a superreg is reserved. A register unit may be allocatable and non-reserved but some of the register(tuples) built with it are reserved. We still need to calculate liveness in this case. Note to out of tree targets: If you start seeing machine verifier errors with this commit, it probably means that you do not properly mark super registers of reserved register as reserved. See for example r292836 or r292870 for example on how to fix that. rdar://29996737 Differential Revision: https://reviews.llvm.org/D28881 llvm-svn: 292871	2017-01-24 01:12:58 +00:00

Author

SHA1

Message

Date

Puyan Lotfi

43e94b15ea

Followup on Proposal to move MIR physical register namespace to '$' sigil.

Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922

2018-01-31 22:04:26 +00:00

Matthias Braun

88c8c9847d

AArch64/PEI: Do not add reserved regs to liveins

We do not track liveness for reserved registers. It is unnecessary to
add them to block livein lists.

llvm-svn: 304059

2017-05-27 03:38:02 +00:00

Matthias Braun

b901d33461

LiveIntervalAnalysis: Calculate liveness even if a superreg is reserved.

A register unit may be allocatable and non-reserved but some of the
register(tuples) built with it are reserved. We still need to calculate
liveness in this case.

Note to out of tree targets: If you start seeing machine verifier errors
with this commit, it probably means that you do not properly mark super
registers of reserved register as reserved. See for example r292836 or
r292870 for example on how to fix that.

rdar://29996737

Differential Revision: https://reviews.llvm.org/D28881

llvm-svn: 292871

2017-01-24 01:12:58 +00:00

3 Commits