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16261 Commits

Author SHA1 Message Date
Jim Grosbach ca21cd749e Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes 
double quoting of ObjC symbol names in constant pool entries.

rdar://8652107

llvm-svn: 118688
 2010-11-10 17:59:10 +00:00
Jim Grosbach f23b2d9d8d Update ARMConstantPoolValue to not use a modifier string. Use an explicit 
VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623

llvm-svn: 118671
 2010-11-10 03:26:07 +00:00
Bruno Cardoso Lopes 67fc18a493 Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some minor tweaks 
llvm-svn: 118667
 2010-11-10 02:13:22 +00:00
Bill Wendling 91607f878c Emit a '!' if this is a "writeback" register or memory address. 
llvm-svn: 118662
 2010-11-10 01:07:54 +00:00
Matt Beaumont-Gay 55c4cc76ce Rename a parameter to avoid confusion with a local variable 
llvm-svn: 118656
 2010-11-10 00:08:58 +00:00
Bill Wendling e9a9c6da04 Emit the warning about the register list not being in ascending order only once. 
llvm-svn: 118653
 2010-11-09 23:45:59 +00:00
Bill Wendling bed9465a96 s/std::vector/SmallVector/ 
llvm-svn: 118648
 2010-11-09 23:28:44 +00:00
Bill Wendling da3c0fbc64 Delete the allocated vector. 
llvm-svn: 118644
 2010-11-09 22:51:42 +00:00
Bob Wilson d0046ca62d Define the subtarget feature for the architecture version, 
as derived from the target triple.  This is important for enabling
features that are implied based on the architecture version.

llvm-svn: 118643
 2010-11-09 22:50:47 +00:00
Bob Wilson 193722ebc8 Do not use MEMBARRIER_MCR for any Thumb code. 
It is only supported for ARM code.  Normally Thumb2 code would use DMB instead,
but depending on how the compiler is invoked (e.g., -mattr=-db) that might be
disabled.  This prevents a "cannot select MEMBARRIER_MCR" error in that
situation.  Radar 8644195

llvm-svn: 118642
 2010-11-09 22:50:44 +00:00
Bill Wendling 2cae3277a5 Two types of instructions have register lists: 
* LDM, et al, uses a bit mask to indicate the register list.
* VLDM, et al, uses a base register plus number.

The LDM instructions may be non-contiguous, but the VLDM ones must be
contiguous. Those are semantic checks that should be done later in the
compiler. Also postpone the creation of the bit mask until it's needed.

llvm-svn: 118640
 2010-11-09 22:44:22 +00:00
Jim Grosbach a942ad4222 Change the ARMConstantPoolValue modifier string to an enumeration. This will 
help in MC'izing the references that use them.

llvm-svn: 118633
 2010-11-09 21:36:17 +00:00
Jim Grosbach 2fd4c37d8b Handle ARM constant pool values that need an explicit reference to the '.' 
pseudo-label. (TLS stuff).

llvm-svn: 118609
 2010-11-09 19:40:22 +00:00
Chris Lattner 4d94e47368 add a case we fail to devirt. 
llvm-svn: 118608
 2010-11-09 19:37:28 +00:00
Jim Grosbach 68147ee320 Trailing whitespace. 
llvm-svn: 118606
 2010-11-09 19:22:26 +00:00
Jim Grosbach 38f8e76e51 Further MCize ARM constant pool values. This allows basic PIC references for 
object file emission.

llvm-svn: 118601
 2010-11-09 18:45:04 +00:00
Jim Grosbach 7e51095c23 Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding. 
llvm-svn: 118600
 2010-11-09 18:43:54 +00:00
Jim Grosbach 59002dc973 For ARM load/store instructions, encode [reg+reg] with no shifter immediate as 
a left shift by zero.

llvm-svn: 118587
 2010-11-09 17:38:15 +00:00
Jim Grosbach 9b973490c9 ARM .word data fixups don't need an adjustment. 
llvm-svn: 118586
 2010-11-09 17:36:59 +00:00
Bruno Cardoso Lopes 9c5c829d9a Fix trailing whitespace and style, no functionality change 
llvm-svn: 118515
 2010-11-09 17:25:34 +00:00
Jim Grosbach dbfb5edbdb Add encoder method for ARM load/store shifted register offset operands. 
llvm-svn: 118513
 2010-11-09 17:20:53 +00:00
Jim Grosbach 9098714f8b Add support for a few simple fixups to the ARM Darwin asm backend. This allows 
constant pool references and global variable refernces to resolve properly
for object file generation. For example,

int x;
void foo(unsigned a, unsigned *p) {
  p[a] = x;
}

can now be successfully compiled directly to an (ARM mode) object file.

llvm-svn: 118469
 2010-11-09 01:37:15 +00:00
Bill Wendling 1b83ed5f7c Revert r118457 and r118458. These won't hold for GPRs. 
llvm-svn: 118462
 2010-11-09 00:30:18 +00:00
Bill Wendling 31b850be15 Get the register and count from the register list operands. 
llvm-svn: 118458
 2010-11-08 23:51:20 +00:00
Bill Wendling aeead4d1e1 reglist has two operands. 
llvm-svn: 118457
 2010-11-08 23:50:20 +00:00
Bill Wendling 8d2aa03ce1 The "addRegListOperands()" function returns the start register and the total 
number of registers in the list.

llvm-svn: 118456
 2010-11-08 23:49:57 +00:00
Owen Anderson c7baee31ad Add support for ARM's specialized vector-compare-against-zero instructions. 
llvm-svn: 118453
 2010-11-08 23:21:22 +00:00
Bruno Cardoso Lopes 9c656fe815 Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka@mips.com) 
llvm-svn: 118447
 2010-11-08 21:42:32 +00:00
Bill Wendling a91d02bc61 Add "write back" bit encoding. 
llvm-svn: 118446
 2010-11-08 21:28:03 +00:00
Bruno Cardoso Lopes 69ba1e9ccb Fix PR8211 
llvm-svn: 118445
 2010-11-08 21:24:59 +00:00
Wesley Peck fc82674b9c Adding working version of assembly parser for the MBlaze backend 
Major cleanup of whitespace and formatting issues in MBlaze backend

llvm-svn: 118434
 2010-11-08 19:40:01 +00:00
Dale Johannesen 0ef474730f Revert 118422 in search of bot verdancy. 
llvm-svn: 118429
 2010-11-08 19:17:22 +00:00
Jason W Kim f3e224f830 Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified. 
llvm-svn: 118422
 2010-11-08 17:58:07 +00:00
Jason W Kim fc6b6bd5a6 Complete listing of ARM/MC/ELF relocation enums 
llvm-svn: 118413
 2010-11-08 16:47:27 +00:00
Che-Liang Chiou fab7697e42 Add generating function declaration for PTX 
llvm-svn: 118398
 2010-11-08 03:06:08 +00:00
Che-Liang Chiou 09bf309527 Add physical register counting functions 
llvm-svn: 118397
 2010-11-08 03:00:52 +00:00
Che-Liang Chiou c03ec0cc42 Add a dummy PTXMCAsmStreamer class 
llvm-svn: 118396
 2010-11-08 02:58:44 +00:00
Bill Wendling 424601a9b3 Make RegList an ASM operand so that TableGen will generate code for it. This is 
an initial implementation and may change once reglists are fully fleshed out.

llvm-svn: 118390
 2010-11-08 00:39:58 +00:00
Bill Wendling 2f9d17c44f Revert. 
llvm-svn: 118389
 2010-11-08 00:32:40 +00:00
Duncan Sands f532d31198 Fix a README item: when doing a comparison with the result 
of a select instruction, see if doing the compare with the
true and false values of the select gives the same result.
If so, that can be used as the value of the comparison.

llvm-svn: 118378
 2010-11-07 16:12:23 +00:00
Bill Wendling 68bac75190 In this context, a reglist is a reg. 
llvm-svn: 118375
 2010-11-07 13:08:28 +00:00
Chris Lattner 0530c024b6 implement aliases for div/idiv that have an explicit A register operand, 
implementing rdar://8431864

llvm-svn: 118364
 2010-11-06 22:41:18 +00:00
Bill Wendling e18980aeaa Add support for parsing register lists. We can't use a bitfield to keep track of 
the registers, because the register numbers may be much greater than the number
of bits available in the machine's register.

I extracted the register list verification code out of the actual parsing of the
registers. This made checking for errors much easier. It also limits the number
of warnings that would be emitted for cascading infractions.

llvm-svn: 118363
 2010-11-06 22:36:58 +00:00
Chris Lattner 9654e108d7 add aliases for movs between seg registers and mem. There are multiple 
different forms of this instruction (movw/movl/movq) which we reported
as being ambiguous.  Since they all do the same thing, gas just picks the
one with the shortest encoding.  Follow its lead here.

This implements rdar://8208615

llvm-svn: 118362
 2010-11-06 22:35:34 +00:00
Chris Lattner 7923358842 move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file. 
llvm-svn: 118361
 2010-11-06 22:25:39 +00:00
Bill Wendling b884a8ee44 Return the base register of a register list for the "getReg()" method. This is 
to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.

llvm-svn: 118360
 2010-11-06 22:19:43 +00:00
Chris Lattner 2abbeded98 work-in-progress 
llvm-svn: 118358
 2010-11-06 22:05:43 +00:00
Bill Wendling ee7f1f9914 General cleanup: 
- Make ARMOperand a class so that some things are internal to the class.
- Reformatting.

llvm-svn: 118357
 2010-11-06 21:42:12 +00:00
Chris Lattner ca7801e472 go to great lengths to work around a GAS bug my previous patch 
exposed:

GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.

Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).

As such, switch the canonical form of this instruction to "pi" instead
of "ip".  This makes the code generator and disassembler generate pi,
avoiding the gas bug.

llvm-svn: 118356
 2010-11-06 21:37:06 +00:00
Chris Lattner 64f91b9825 rework the rotate-by-1 instructions to be defined like the 
shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1.  It turns out that a bunch of these rotate
instructions were completely broken because they used 1 
instead of $1.

This fixes assembly mismatches on "rclb	$1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.

llvm-svn: 118355
 2010-11-06 21:23:40 +00:00
Chris Lattner 05031e7f1a change the fp comparison instructions to not have %st0 explicitly 
listed in its asm string, for consistency with the other similar
instructions.

llvm-svn: 118354
 2010-11-06 20:55:09 +00:00
Chris Lattner 290199f8ee move the plethora of fp stack aliases to the .td file. 
llvm-svn: 118353
 2010-11-06 20:47:38 +00:00
Chris Lattner 4869d346e3 add (and document) the ability for alias results to have 
fixed physical registers.  Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).

llvm-svn: 118352
 2010-11-06 19:57:21 +00:00
Bill Wendling 7cef447c14 Add a RegList (register list) object to ARMOperand. It will be used soon to hold 
(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.

llvm-svn: 118351
 2010-11-06 19:56:04 +00:00
Chris Lattner b6f8e8248d generalize alias support to allow the result of an alias to 
add fixed immediate values.  Move the aad and aam aliases to
use this, and document it.

llvm-svn: 118350
 2010-11-06 19:25:43 +00:00
Chris Lattner 161bf7de25 move fnstsw aliases to .td file, fix typo 
llvm-svn: 118349
 2010-11-06 18:58:32 +00:00
Chris Lattner ec66010e80 move in/out aliases to the .td files. 
llvm-svn: 118348
 2010-11-06 18:52:40 +00:00
Chris Lattner 6881e175c3 move sldt, imul, and movabsq aliases from c++ to .td file. 
llvm-svn: 118347
 2010-11-06 18:44:26 +00:00
Chris Lattner fab9413b01 correct suffix matching to search for s/l/t suffixes on 
floating point stack instructions instead of looking for b/w/l/q.

This fixes issues where we'd accidentally match fistp to fistpl,
when it is in fact an ambiguous instruction.

This changes the behavior of llvm-mc to reject fstp, which was the
correct fix for rdar://8456389:
t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt')
fstp	(%rax)

it also causes us to correctly reject fistp and fist, which addresses
PR8528:

t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl')
fistp (%rax)
^
t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl')
fist (%rax)
^

Thanks to Ismail Donmez for tracking down the issue here!

llvm-svn: 118346
 2010-11-06 18:28:02 +00:00
Bill Wendling 8300d834c9 Fix grammar. 
llvm-svn: 118341
 2010-11-06 10:51:53 +00:00
Bill Wendling 4f4bce0682 Fix grammar. 
llvm-svn: 118340
 2010-11-06 10:48:18 +00:00
Bill Wendling 518e43c453 MatchRegisterName() returns 0 if it can't match the register. 
llvm-svn: 118339
 2010-11-06 10:45:34 +00:00
Bill Wendling 6d2eb737af Use TryParseRegister() instead of MatchRegisterName(). The former returns -1 
while the latter doesn't.

llvm-svn: 118338
 2010-11-06 10:40:24 +00:00
Benjamin Kramer 8628e2a19c Add a note. 
llvm-svn: 118337
 2010-11-06 10:37:16 +00:00
Chris Lattner db6f90c61c fix a bug where we had an implicit assumption that the 
result instruction operand numbering matched the result pattern.

Fixing this allows us to move the xchg/test aliases to the .td file.

llvm-svn: 118334
 2010-11-06 08:20:59 +00:00
Eric Christopher 89965d7091 Make sure we have movw on the target before using it. 
Fixes 8559.

llvm-svn: 118333
 2010-11-06 07:53:11 +00:00
Chris Lattner aa7847df06 move the lcall/ljmp aliases to the .td file. 
llvm-svn: 118332
 2010-11-06 07:48:45 +00:00
Chris Lattner 9535f90abe move the "movsd -> movsl" alias to the .td files, 
tidy up the movsx and movzx aliases.

llvm-svn: 118331
 2010-11-06 07:34:58 +00:00
Chris Lattner 8188fb264f fix some bugs in the alias support, unblocking changing of "clr" aliases 
from c++ hacks to proper .td InstAlias definitions.  Change them!

llvm-svn: 118330
 2010-11-06 07:31:43 +00:00
Chris Lattner fecdad6237 Reimplement BuildResultOperands to be in terms of the result instruction's 
operand list instead of the operand list redundantly declared on the alias
or instruction.

With this change, we finally remove the ins/outs list on the alias.  Before:
  def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
                  "movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
  def : InstAlias<"movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;

This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.

llvm-svn: 118329
 2010-11-06 07:14:44 +00:00
Jim Grosbach 2db0ea03ba Hook up the '.code {16|32}' directive to the streamer. 
llvm-svn: 118310
 2010-11-05 22:40:53 +00:00
Jim Grosbach c6db8ce5da Hook up the '.thumb_func' directive to the streamer. 
llvm-svn: 118307
 2010-11-05 22:33:53 +00:00
Jim Grosbach 0fe92e3fea Fix past-o. 
llvm-svn: 118304
 2010-11-05 22:11:33 +00:00
Jim Grosbach 5a2c68d308 MC'ize the '.code 16' and '.thumb_func' ARM directives. 
llvm-svn: 118301
 2010-11-05 22:08:08 +00:00
Owen Anderson a4076924d1 Disallow the certain NEON modified-immediate forms when generating vorr or vbic. 
llvm-svn: 118300
 2010-11-05 21:57:54 +00:00
Jim Grosbach ff9e507d8e MC'ize simple ARMConstantValue entry emission (with a FIXME). 
llvm-svn: 118295
 2010-11-05 20:34:24 +00:00
Owen Anderson 30c4892ea5 Add codegen and encoding support for the immediate form of vbic. 
llvm-svn: 118291
 2010-11-05 19:27:46 +00:00
Jim Grosbach 2bab7570f5 Enable MachO writing for ARM/Darwin. Lots of stuff still doesn't work 
(relocations, e.g.), but this will allow simple things to flow through.

llvm-svn: 118289
 2010-11-05 18:50:35 +00:00
Jim Grosbach 46c2acbcb4 Allow targets to specify the MachO CPUType/CPUSubtype information. 
llvm-svn: 118288
 2010-11-05 18:48:58 +00:00
Jim Grosbach 1df82e67d1 Add FIXME. 
llvm-svn: 118280
 2010-11-05 17:37:13 +00:00
Duncan Sands 98512315f7 When passing a huge parameter using the byval mechanism, a long 
sequence of loads and stores was being generated to perform the
copy on the x86 targets if the parameter was less than 4 byte
aligned, causing llc to use up vast amounts of memory and time.
Use a "rep movs" form instead.  PR7170.

llvm-svn: 118260
 2010-11-04 21:16:46 +00:00
Duncan Sands 71049f78ed In the calling convention logic, ValVT is always a legal type, 
and as such can be represented by an MVT - the more complicated
EVT is not needed.  Use MVT for ValVT everywhere.

llvm-svn: 118245
 2010-11-04 10:49:57 +00:00
Evan Cheng 21acf9fb38 Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli. 
llvm-svn: 118237
 2010-11-04 05:19:35 +00:00
Jim Grosbach 0fb841fd19 Add ARM fixup info for load/store label references. Probably will need a bit of 
tweaking when we start using it for object file emission or JIT, but it's a
start.

llvm-svn: 118221
 2010-11-04 01:12:30 +00:00
Bill Wendling c002463ac4 Add encoding for VSTR. 
llvm-svn: 118220
 2010-11-04 00:59:42 +00:00
Jim Grosbach 2eed7a1310 Teach ARM Target to use the tblgen support for generating an MC'ized 
CodeEmitter.

llvm-svn: 118209
 2010-11-03 23:52:49 +00:00
Owen Anderson bc9b31c493 Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization. 
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.

llvm-svn: 118204
 2010-11-03 23:15:26 +00:00
Owen Anderson 0747307049 Add support for code generation of the one register with immediate form of vorr. 
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.

llvm-svn: 118201
 2010-11-03 22:44:51 +00:00
Jim Grosbach 49b0c45ecf trailing whitespace 
llvm-svn: 118199
 2010-11-03 22:03:20 +00:00
Eric Christopher e4dd7378d0 Optimize generated code for integer materialization a bit. 
llvm-svn: 118192
 2010-11-03 20:21:17 +00:00
Owen Anderson bb81f80af6 Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead, 
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.

llvm-svn: 118183
 2010-11-03 18:16:27 +00:00
Bob Wilson 7d0ac84abd Add codegen patterns for VST1-lane instructions. Radar 8599955. 
llvm-svn: 118176
 2010-11-03 16:24:53 +00:00
Bob Wilson ceb49296ef Check for extractelement with a variable operand for the element number. 
For NEON we had been assuming this was always an immediate constant.

llvm-svn: 118175
 2010-11-03 16:24:50 +00:00
Duncan Sands 1462777017 Simplify uses of MVT and EVT. An MVT can be compared directly 
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.

llvm-svn: 118169
 2010-11-03 12:17:33 +00:00
Duncan Sands f5dda01f33 Inside the calling convention logic LocVT is always a simple 
value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.

llvm-svn: 118167
 2010-11-03 11:35:31 +00:00
Evan Cheng 8740ee3637 Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. 
llvm-svn: 118160
 2010-11-03 06:34:55 +00:00
Evan Cheng 6f36042557 Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. 
llvm-svn: 118152
 2010-11-03 05:14:24 +00:00
Bill Wendling 6552a109bb Put the PC encoding in the correct bit position. 
llvm-svn: 118151
 2010-11-03 04:57:44 +00:00
Eric Christopher c63d846ad6 Invert these branches by default, it makes assembly comparisons a little 
easier to read.

llvm-svn: 118148
 2010-11-03 04:29:11 +00:00
Bill Wendling e84eb99cbb The MC code couldn't handle ARM LDR instructions with negative offsets: 
vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.

llvm-svn: 118144
 2010-11-03 01:49:29 +00:00
Jim Grosbach fd96701456 Remove unused function. 
llvm-svn: 118141
 2010-11-03 01:35:15 +00:00
Jim Grosbach e7f7de95e0 Remove the no longer used 'Modifier' optional operand to the ARM 
printOperand() asm printer helper functions. rdar://8425198

llvm-svn: 118140
 2010-11-03 01:11:15 +00:00
Jim Grosbach 50ba3c09bf Remove unused function. 
llvm-svn: 118139
 2010-11-03 01:07:48 +00:00
Jim Grosbach c6af2b4066 Break ARM addrmode4 (load/store multiple base address) into its constituent 
parts. Represent the operation mode as an optional operand instead.
rdar://8614429

llvm-svn: 118137
 2010-11-03 01:01:43 +00:00
Evan Cheng debf9c502a Two sets of changes. Sorry they are intermingled. 
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
   "optimize for latency". Call instructions don't have the right latency and
   this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
   not # of micro-ops since multi-latency instructions is completely executed
   even when the predicate is false. Also, some instruction will be "slower"
   when they are predicated due to the register def becoming implicit input.
   rdar://8598427

llvm-svn: 118135
 2010-11-03 00:45:17 +00:00
Evan Cheng 634ab6c2b7 Modify scheduling itineraries to correct instruction latencies (not operand 
latencies) of loads.

llvm-svn: 118134
 2010-11-03 00:40:22 +00:00
Eric Christopher 1e43892e4b Make sure we're only storing a single bit here. 
llvm-svn: 118126
 2010-11-02 23:59:09 +00:00
Chris Lattner 9c9bfb6870 per a suggestion by Frits van Bommel, mark all MBlaze Pseudo 
instructions as isCodeGenOnly in the parent class instead of
sprinkling it throughout the .td files.

llvm-svn: 118125
 2010-11-02 23:57:05 +00:00
Owen Anderson 0ebd1fd594 Revert r118097 to fix buildbots. 
llvm-svn: 118121
 2010-11-02 23:47:29 +00:00
Chris Lattner cc5dce89d4 Completely reject instructions that have an operand in their 
ins/outs list that isn't specified by their asmstring.  Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right.  Mark a bunch of ARM instructions that use this as 
isCodeGenOnly.  Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).

llvm-svn: 118119
 2010-11-02 23:40:41 +00:00
Bill Wendling f9eebb58b9 Obsessive formatting changes. No functionality impact. 
llvm-svn: 118103
 2010-11-02 22:53:11 +00:00
Bill Wendling 23436b6530 Omit unused parameter name. 
llvm-svn: 118099
 2010-11-02 22:46:04 +00:00
Bill Wendling 91da9abbee Simplify the EncodeInstruction method now that a lot of the special case stuff 
is handled with the MC encoder.

llvm-svn: 118098
 2010-11-02 22:44:12 +00:00
Owen Anderson 7c30390277 Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning. 
llvm-svn: 118097
 2010-11-02 22:41:42 +00:00
Bill Wendling 603bd8f54c Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work 
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.

llvm-svn: 118094
 2010-11-02 22:31:46 +00:00
Owen Anderson a4b63e19d2 Rename encoder methods to match naming convention. 
llvm-svn: 118093
 2010-11-02 22:28:01 +00:00
Chris Lattner 15977afb02 mark a few codegenonly instructions. 
llvm-svn: 118092
 2010-11-02 22:26:33 +00:00
Owen Anderson dec87e10fd Provide correct encodings for the remaining vst variants that we currently generate. 
llvm-svn: 118087
 2010-11-02 22:18:18 +00:00
Owen Anderson adf88d4c5f Tentative encodings for the "single element from one lane" variant of vst1. 
llvm-svn: 118084
 2010-11-02 21:54:45 +00:00
Owen Anderson b95618cfe0 Add correct encodings for basic variants for vst3 and vst4. 
llvm-svn: 118082
 2010-11-02 21:47:03 +00:00
Bob Wilson d80b29d6f7 Add NEON VST1-lane instructions. Partial fix for Radar 8599955. 
llvm-svn: 118069
 2010-11-02 21:18:25 +00:00
Owen Anderson fa08e1e277 Add correct encodings for the basic variants for vst2. 
llvm-svn: 118068
 2010-11-02 21:16:58 +00:00
Owen Anderson 87c62e54e6 Add correct encodings for the basic form of vst1. 
llvm-svn: 118067
 2010-11-02 21:06:06 +00:00
Owen Anderson 9f20daf3b4 Factor out a common encoding class for loads and stores with a lane parameter. 
llvm-svn: 118055
 2010-11-02 20:47:39 +00:00
Owen Anderson a83859539f Add correct encodings for the rest of the vld instructions that we generate. 
llvm-svn: 118053
 2010-11-02 20:40:59 +00:00
Jim Grosbach 93a4d44ee6 Sort bit assignments. Cosmetic change only. 
llvm-svn: 118029
 2010-11-02 17:59:04 +00:00
Jim Grosbach 0b7fda23cc Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke 
assumptions about stack layout. Specifically, LR must be saved next to FP.

llvm-svn: 118026
 2010-11-02 17:35:25 +00:00
Owen Anderson 526ffd57d2 Add correct NEON encodings for vld2, vld3, and vld4 basic variants. 
llvm-svn: 117997
 2010-11-02 01:24:55 +00:00
Eric Christopher b2abb508ae Remove an assert - it's possible to be hit, and we just want to avoid 
handling those cases for now.

llvm-svn: 117996
 2010-11-02 01:24:49 +00:00
Eric Christopher ac746e1b38 Whitespeace 
llvm-svn: 117995
 2010-11-02 01:22:45 +00:00
Eric Christopher e8fccc82e4 No really, no thumb1 for arm fast isel. Also add an informative comment as 
to what someone would need to do to support thumb1.

llvm-svn: 117994
 2010-11-02 01:21:28 +00:00
Owen Anderson b3ca2060c0 Attempt to provide correct encodings for a number of other vld1 variants, which we can't test 
since we can neither generate nor parse them at the moment.

llvm-svn: 117988
 2010-11-02 00:24:52 +00:00
Owen Anderson f1610f7910 Add aesthetic break. 
llvm-svn: 117986
 2010-11-02 00:14:00 +00:00
Owen Anderson ad40234eff Add correct NEON encodings for the "multiple single elements" form of vld. 
llvm-svn: 117984
 2010-11-02 00:05:05 +00:00
Jim Grosbach 2ba03aa618 Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXME 
for handling the fixup necessary.

llvm-svn: 117978
 2010-11-01 23:45:50 +00:00
Jim Grosbach a3efae35f5 Remove unused function. 
llvm-svn: 117977
 2010-11-01 23:40:56 +00:00
Bob Wilson dd9fbaa9c0 Add support for alignment operands on VLD1-lane instructions. 
This is another part of the fix for Radar 8599955.

llvm-svn: 117976
 2010-11-01 23:40:51 +00:00
Bill Wendling 3f37ade36e Missed reverting this bit. 
llvm-svn: 117971
 2010-11-01 23:17:54 +00:00
Bill Wendling f7e176a3ec Minor cleanup. 
llvm-svn: 117969
 2010-11-01 23:11:22 +00:00
Chris Lattner 60d555c178 rearrange a bit. 
llvm-svn: 117967
 2010-11-01 23:07:52 +00:00
Bob Wilson dc44990c7d Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. 
llvm-svn: 117964
 2010-11-01 22:04:05 +00:00
Bill Wendling 418bd53008 Move the machine operand MC encoding patterns to the parent classes. 
llvm-svn: 117956
 2010-11-01 21:17:06 +00:00
Chris Lattner 865dd96f22 use our fancy new MnemonicAlias mechanism to remove a bunch of hacks 
from X86AsmParser.cpp

llvm-svn: 117952
 2010-11-01 21:06:34 +00:00
Bill Wendling c6627eec13 When we look at instructions to convert to setting the 's' flag, we need to look 
at more than those which define CPSR. You can have this situation:

(1)  subs  ...
(2)  sub   r6, r5, r4
(3)  movge ...
(4)  cmp   r6, 0
(5)  movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1)  sub   r1, r2, r3
(2)  sub   r4, r5, r6
(3)  cmp   r4, ...
(5)  movge ...
(6)  cmp   r1, ...
(7)  movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.

llvm-svn: 117950
 2010-11-01 20:41:43 +00:00
Bob Wilson 44be217af1 NEON does not support truncating vector stores. Radar 8598391. 
llvm-svn: 117940
 2010-11-01 18:31:39 +00:00
Jim Grosbach 7d45c101e5 Add FIXME. 
llvm-svn: 117936
 2010-11-01 18:11:14 +00:00
Jim Grosbach fddf36d254 Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates 
codegen using the patterns; the latter gates the assembler recognizing the
instruction.

llvm-svn: 117931
 2010-11-01 17:08:58 +00:00
Jim Grosbach 0190a649e8 Mark ARM subtarget features that are available for the assembler. 
llvm-svn: 117929
 2010-11-01 16:59:54 +00:00
Jim Grosbach 99710a871c trailing whitespace 
llvm-svn: 117927
 2010-11-01 16:44:21 +00:00
Jim Grosbach 5b373341fc The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the 
patterns as such

llvm-svn: 117923
 2010-11-01 15:59:52 +00:00