240162629c
1. Adding missing immediate mode asm parser test cases.
...
2. Fixing improper immediate mode reverse subtract.
llvm-svn: 118948
2010-11-13 00:03:46 +00:00
1293c6a23a
Temporarily revert this.
...
llvm-svn: 118946
2010-11-12 23:50:48 +00:00
9c40af415f
For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr.
...
llvm-svn: 118945
2010-11-12 23:46:13 +00:00
4b074b8995
Fixing improperly encoded reverse subtract instructions in MBlaze backend.
...
llvm-svn: 118943
2010-11-12 23:41:10 +00:00
7cd724ae7d
Revert r118939 while I work out why it broke some buildbots.
...
llvm-svn: 118942
2010-11-12 23:36:03 +00:00
c542248602
1. Finishing MBlaze MC asm parser test cases
...
2. Parsing .word directive in MBlaze asm parser
3. Fixing hack where memory instructions reversed order of last two parameters
4. Fixing many improperly encoded instructions
5. Support parsing special instructions (MFS,MTS,etc.)
6. Removing unused functions from inst printer
llvm-svn: 118941
2010-11-12 23:30:17 +00:00
0003a296ad
Attemt to provide correct encodings for Thumb2 binary operators.
...
llvm-svn: 118939
2010-11-12 23:18:11 +00:00
f478cf9685
Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.
...
llvm-svn: 118938
2010-11-12 23:03:38 +00:00
49a66f7d71
Make this happen for ARM like x86. Don't entirely bail out when
...
an address is in a different block, get it into a register and go
from there.
llvm-svn: 118936
2010-11-12 22:52:32 +00:00
0fc8084a64
Add conditional mvn instructions.
...
llvm-svn: 118935
2010-11-12 22:42:47 +00:00
e09122b46b
Zap a copy/paste-o bit of dead code.
...
llvm-svn: 118926
2010-11-12 21:29:10 +00:00
31a7234a47
Refactor to parameterize some ARM load/store encoding patterns. Preparatory
...
to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.
llvm-svn: 118925
2010-11-12 21:28:15 +00:00
8fdd172502
First stab at providing correct Thumb2 encodings, start with adc.
...
llvm-svn: 118924
2010-11-12 21:12:40 +00:00
2d59ee34f1
Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next.
...
llvm-svn: 118922
2010-11-12 20:32:20 +00:00
6bb1ae9d45
Kill more unused stuff.
...
llvm-svn: 118921
2010-11-12 19:27:45 +00:00
984ff7d17e
Remove unused class.
...
llvm-svn: 118919
2010-11-12 19:24:53 +00:00
0284c5d0c7
When the definition of an address value is in a different block
...
from the user of the address, fall back to just using the
address in a register instead of bailing out of fast-isel
altogether.
llvm-svn: 118917
2010-11-12 19:14:00 +00:00
87cf7f787e
accept lret as an alias for lretl, fixing the reopened part of PR8592
...
llvm-svn: 118916
2010-11-12 18:54:56 +00:00
3fd741191d
Fill in the default predication bits for ARM unconditional branch.
...
llvm-svn: 118907
2010-11-12 18:13:26 +00:00
0deb9c20c0
Encoding for ARM LDRSB instructions.
...
llvm-svn: 118905
2010-11-12 17:52:59 +00:00
5b013b102d
implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix.
...
llvm-svn: 118903
2010-11-12 17:41:20 +00:00
64634c36dd
tidy up.
...
llvm-svn: 118896
2010-11-12 17:24:29 +00:00
0a9dd405a5
Fix memory access lowering on SPU, adding
...
support for the case where alignment<value size.
These cases were silently miscompiled before this patch.
Now they are overly verbose -especially storing is- and
any front-end should still avoid misaligned memory
accesses as much as possible. The bit juggling algorithm
added here probably has some room for improvement still.
llvm-svn: 118889
2010-11-12 10:14:03 +00:00
22d0492f34
Fix up a few more spots of addrmode2 (or not) changes that were
...
missed. Update some comments accordingly.
Fixes rdar://8652289
llvm-svn: 118888
2010-11-12 09:48:30 +00:00
6d95ed1760
Remove possibly useful info from comment, per Chris.
...
llvm-svn: 118865
2010-11-12 00:43:18 +00:00
03c0330176
Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>
...
llvm-svn: 118864
2010-11-12 00:38:32 +00:00
20b6fd7d5d
Start of support for binary emit of 16-it Thumb instructions.
...
llvm-svn: 118859
2010-11-11 23:41:09 +00:00
ce2250fba4
Fill out support for Thumb2 encodings of NEON instructions.
...
llvm-svn: 118854
2010-11-11 23:12:55 +00:00
8abdf4b6ea
The BRK instruction in the MicroBlaze is a branch-and-link.
...
llvm-svn: 118848
2010-11-11 22:21:08 +00:00
bf65066a37
Fix tblgen instruction errors exposed by MC asm parser tests
...
Fix minimum 16-bit signed value error exposed by MC asm parser tests
Add initial MC asm parser tests for the MBlaze backend
llvm-svn: 118844
2010-11-11 21:40:53 +00:00
99a8cb4875
Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].
...
llvm-svn: 118843
2010-11-11 21:36:43 +00:00
7ae11c6962
Revert the accidental commit I made reverting the previous commit.
...
llvm-svn: 118835
2010-11-11 20:50:14 +00:00
c33f28bf90
ARM fixup encoding for direct call instructions (BL).
...
llvm-svn: 118829
2010-11-11 20:05:40 +00:00
b90f7004cf
Revert this temporarily.
...
llvm-svn: 118827
2010-11-11 19:47:02 +00:00
e6283f950d
Change the prologue and epilogue to use push/pop for the low ARM registers.
...
llvm-svn: 118823
2010-11-11 19:26:03 +00:00
7ffe3b35ac
Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
...
More tests to come.
llvm-svn: 118819
2010-11-11 19:07:48 +00:00
d1a6f5a384
Fixed some bugs in MBlaze asm parser that were introduced when removing OwningPtrs from the code.
...
llvm-svn: 118807
2010-11-11 18:41:33 +00:00
932aab3cbf
add a note
...
llvm-svn: 118806
2010-11-11 18:23:57 +00:00
9d6d77a9f4
Encoding of destination fixup for ARM branch and conditional branch
...
instructions.
llvm-svn: 118801
2010-11-11 18:04:49 +00:00
1d6aa32b87
add pr#
...
llvm-svn: 118797
2010-11-11 17:17:56 +00:00
68685e644f
Encoding for ARM LDRSH_POST.
...
llvm-svn: 118794
2010-11-11 16:55:29 +00:00
19fa38000a
Remove some explicit arguments to getELFSection. This is
...
a leftover from the removal of isExplicit.
llvm-svn: 118774
2010-11-11 03:40:25 +00:00
f18b951e18
Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.
...
llvm-svn: 118767
2010-11-11 01:55:59 +00:00
e967c0a795
Fix encoding of Ra register for ARM smla* instructions.
...
llvm-svn: 118761
2010-11-11 01:27:41 +00:00
607efcbc3e
ARM STRH encoding information.
...
llvm-svn: 118757
2010-11-11 01:09:40 +00:00
c4dd2349c7
Move LDM predicate operand encoding into base clase. Add STM missing STM
...
encoding bits.
llvm-svn: 118738
2010-11-10 23:44:32 +00:00
cc4a491557
ARM LDM encoding for the mode (ia, ib, da, db) operand.
...
llvm-svn: 118736
2010-11-10 23:38:36 +00:00
58ef598cd1
Fix ARM encoding of non-return LDM instructions.
...
llvm-svn: 118732
2010-11-10 23:18:49 +00:00
e39a9fcc0e
Fix ARM encoding of LDM+Return instruction.
...
llvm-svn: 118730
2010-11-10 23:12:48 +00:00
ca52411955
Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build vector with 2 elts
...
llvm-svn: 118720
2010-11-10 21:35:41 +00:00
ca21cd749e
Simplify and clean up MC symbol lookup for ARM constant pool values. This fixes
...
double quoting of ObjC symbol names in constant pool entries.
rdar://8652107
llvm-svn: 118688
2010-11-10 17:59:10 +00:00
f23b2d9d8d
Update ARMConstantPoolValue to not use a modifier string. Use an explicit
...
VariantKind marker to indicate the additional information necessary. Update
MC to handle the new Kinds. rdar://8647623
llvm-svn: 118671
2010-11-10 03:26:07 +00:00
67fc18a493
Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some minor tweaks
...
llvm-svn: 118667
2010-11-10 02:13:22 +00:00
91607f878c
Emit a '!' if this is a "writeback" register or memory address.
...
llvm-svn: 118662
2010-11-10 01:07:54 +00:00
55c4cc76ce
Rename a parameter to avoid confusion with a local variable
...
llvm-svn: 118656
2010-11-10 00:08:58 +00:00
e9a9c6da04
Emit the warning about the register list not being in ascending order only once.
...
llvm-svn: 118653
2010-11-09 23:45:59 +00:00
bed9465a96
s/std::vector/SmallVector/
...
llvm-svn: 118648
2010-11-09 23:28:44 +00:00
da3c0fbc64
Delete the allocated vector.
...
llvm-svn: 118644
2010-11-09 22:51:42 +00:00
d0046ca62d
Define the subtarget feature for the architecture version,
...
as derived from the target triple. This is important for enabling
features that are implied based on the architecture version.
llvm-svn: 118643
2010-11-09 22:50:47 +00:00
193722ebc8
Do not use MEMBARRIER_MCR for any Thumb code.
...
It is only supported for ARM code. Normally Thumb2 code would use DMB instead,
but depending on how the compiler is invoked (e.g., -mattr=-db) that might be
disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that
situation. Radar 8644195
llvm-svn: 118642
2010-11-09 22:50:44 +00:00
2cae3277a5
Two types of instructions have register lists:
...
* LDM, et al, uses a bit mask to indicate the register list.
* VLDM, et al, uses a base register plus number.
The LDM instructions may be non-contiguous, but the VLDM ones must be
contiguous. Those are semantic checks that should be done later in the
compiler. Also postpone the creation of the bit mask until it's needed.
llvm-svn: 118640
2010-11-09 22:44:22 +00:00
a942ad4222
Change the ARMConstantPoolValue modifier string to an enumeration. This will
...
help in MC'izing the references that use them.
llvm-svn: 118633
2010-11-09 21:36:17 +00:00
2fd4c37d8b
Handle ARM constant pool values that need an explicit reference to the '.'
...
pseudo-label. (TLS stuff).
llvm-svn: 118609
2010-11-09 19:40:22 +00:00
4d94e47368
add a case we fail to devirt.
...
llvm-svn: 118608
2010-11-09 19:37:28 +00:00
68147ee320
Trailing whitespace.
...
llvm-svn: 118606
2010-11-09 19:22:26 +00:00
38f8e76e51
Further MCize ARM constant pool values. This allows basic PIC references for
...
object file emission.
llvm-svn: 118601
2010-11-09 18:45:04 +00:00
7e51095c23
Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.
...
llvm-svn: 118600
2010-11-09 18:43:54 +00:00
59002dc973
For ARM load/store instructions, encode [reg+reg] with no shifter immediate as
...
a left shift by zero.
llvm-svn: 118587
2010-11-09 17:38:15 +00:00
9b973490c9
ARM .word data fixups don't need an adjustment.
...
llvm-svn: 118586
2010-11-09 17:36:59 +00:00
9c5c829d9a
Fix trailing whitespace and style, no functionality change
...
llvm-svn: 118515
2010-11-09 17:25:34 +00:00
dbfb5edbdb
Add encoder method for ARM load/store shifted register offset operands.
...
llvm-svn: 118513
2010-11-09 17:20:53 +00:00
9098714f8b
Add support for a few simple fixups to the ARM Darwin asm backend. This allows
...
constant pool references and global variable refernces to resolve properly
for object file generation. For example,
int x;
void foo(unsigned a, unsigned *p) {
p[a] = x;
}
can now be successfully compiled directly to an (ARM mode) object file.
llvm-svn: 118469
2010-11-09 01:37:15 +00:00
1b83ed5f7c
Revert r118457 and r118458. These won't hold for GPRs.
...
llvm-svn: 118462
2010-11-09 00:30:18 +00:00
31b850be15
Get the register and count from the register list operands.
...
llvm-svn: 118458
2010-11-08 23:51:20 +00:00
aeead4d1e1
reglist has two operands.
...
llvm-svn: 118457
2010-11-08 23:50:20 +00:00
8d2aa03ce1
The "addRegListOperands()" function returns the start register and the total
...
number of registers in the list.
llvm-svn: 118456
2010-11-08 23:49:57 +00:00
c7baee31ad
Add support for ARM's specialized vector-compare-against-zero instructions.
...
llvm-svn: 118453
2010-11-08 23:21:22 +00:00
9c656fe815
Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka@mips.com)
...
llvm-svn: 118447
2010-11-08 21:42:32 +00:00
a91d02bc61
Add "write back" bit encoding.
...
llvm-svn: 118446
2010-11-08 21:28:03 +00:00
69ba1e9ccb
Fix PR8211
...
llvm-svn: 118445
2010-11-08 21:24:59 +00:00
fc82674b9c
Adding working version of assembly parser for the MBlaze backend
...
Major cleanup of whitespace and formatting issues in MBlaze backend
llvm-svn: 118434
2010-11-08 19:40:01 +00:00
0ef474730f
Revert 118422 in search of bot verdancy.
...
llvm-svn: 118429
2010-11-08 19:17:22 +00:00
f3e224f830
Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.
...
llvm-svn: 118422
2010-11-08 17:58:07 +00:00
fc6b6bd5a6
Complete listing of ARM/MC/ELF relocation enums
...
llvm-svn: 118413
2010-11-08 16:47:27 +00:00
fab7697e42
Add generating function declaration for PTX
...
llvm-svn: 118398
2010-11-08 03:06:08 +00:00
09bf309527
Add physical register counting functions
...
llvm-svn: 118397
2010-11-08 03:00:52 +00:00
c03ec0cc42
Add a dummy PTXMCAsmStreamer class
...
llvm-svn: 118396
2010-11-08 02:58:44 +00:00
424601a9b3
Make RegList an ASM operand so that TableGen will generate code for it. This is
...
an initial implementation and may change once reglists are fully fleshed out.
llvm-svn: 118390
2010-11-08 00:39:58 +00:00
2f9d17c44f
Revert.
...
llvm-svn: 118389
2010-11-08 00:32:40 +00:00
f532d31198
Fix a README item: when doing a comparison with the result
...
of a select instruction, see if doing the compare with the
true and false values of the select gives the same result.
If so, that can be used as the value of the comparison.
llvm-svn: 118378
2010-11-07 16:12:23 +00:00
68bac75190
In this context, a reglist is a reg.
...
llvm-svn: 118375
2010-11-07 13:08:28 +00:00
0530c024b6
implement aliases for div/idiv that have an explicit A register operand,
...
implementing rdar://8431864
llvm-svn: 118364
2010-11-06 22:41:18 +00:00
e18980aeaa
Add support for parsing register lists. We can't use a bitfield to keep track of
...
the registers, because the register numbers may be much greater than the number
of bits available in the machine's register.
I extracted the register list verification code out of the actual parsing of the
registers. This made checking for errors much easier. It also limits the number
of warnings that would be emitted for cascading infractions.
llvm-svn: 118363
2010-11-06 22:36:58 +00:00
9654e108d7
add aliases for movs between seg registers and mem. There are multiple
...
different forms of this instruction (movw/movl/movq) which we reported
as being ambiguous. Since they all do the same thing, gas just picks the
one with the shortest encoding. Follow its lead here.
This implements rdar://8208615
llvm-svn: 118362
2010-11-06 22:35:34 +00:00
7923358842
move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file.
...
llvm-svn: 118361
2010-11-06 22:25:39 +00:00
b884a8ee44
Return the base register of a register list for the "getReg()" method. This is
...
to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.
llvm-svn: 118360
2010-11-06 22:19:43 +00:00
2abbeded98
work-in-progress
...
llvm-svn: 118358
2010-11-06 22:05:43 +00:00
ee7f1f9914
General cleanup:
...
- Make ARMOperand a class so that some things are internal to the class.
- Reformatting.
llvm-svn: 118357
2010-11-06 21:42:12 +00:00
ca7801e472
go to great lengths to work around a GAS bug my previous patch
...
exposed:
GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.
Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).
As such, switch the canonical form of this instruction to "pi" instead
of "ip". This makes the code generator and disassembler generate pi,
avoiding the gas bug.
llvm-svn: 118356
2010-11-06 21:37:06 +00:00
64f91b9825
rework the rotate-by-1 instructions to be defined like the
...
shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1. It turns out that a bunch of these rotate
instructions were completely broken because they used 1
instead of $1.
This fixes assembly mismatches on "rclb $1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.
llvm-svn: 118355
2010-11-06 21:23:40 +00:00
Wesley Peck