0e854f3d43
Rename the AsmPrinter directory to InstPrinter for those targets that have
...
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
llvm-svn: 115360
2010-10-01 22:39:28 +00:00
14e909a942
Delete token *after* reading from it.
...
llvm-svn: 115311
2010-10-01 12:25:27 +00:00
dd224d2333
Massive rewrite of MMX:
...
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.
Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics.
MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces. Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.
The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.
llvm-svn: 115243
2010-09-30 23:57:10 +00:00
c6e13f7383
Clean up asm writer usage for x86 and msp430 to flag that the writer should
...
use MC instructions in the printInstruction() method via the tablegen flag
for it rather than a #define prior to including the autogenerated bits.
llvm-svn: 115238
2010-09-30 23:40:25 +00:00
73a7caee4b
preemptively add the rest of the non-n fpstack instructions.
...
llvm-svn: 115168
2010-09-30 17:11:29 +00:00
4373badcdf
implement support for finit, PR8258
...
llvm-svn: 115156
2010-09-30 16:42:53 +00:00
adc0dbe470
add support for fstcw, PR8259
...
llvm-svn: 115154
2010-09-30 16:39:29 +00:00
bad267fa05
Adds getPointerSize() to the AsmBackend which will be needed by the final patch
...
for the dwarf .loc support to emit dwarf line number tables.
llvm-svn: 115153
2010-09-30 16:38:07 +00:00
70d6e0e0ff
Correctly produce R_X86_64_32 or R_X86_64_32S.
...
With this patch in
movq $foo, foo(%rip)
foo:
.long foo
We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.
llvm-svn: 115134
2010-09-30 03:11:42 +00:00
0574cc556a
Noticed by inspection when looking for other cmov bits.
...
llvm-svn: 115100
2010-09-29 23:00:29 +00:00
23ebf4b319
Add parens to fix GCC warning:
...
lib/Target/X86/X86MCCodeEmitter.cpp: 190: error: suggest parentheses around '&&' within '||'
llvm-svn: 115064
2010-09-29 18:56:57 +00:00
2b43c1cf42
implement rdar://8491845 - Gas supports commuted forms of non-commutable instructions.
...
llvm-svn: 115061
2010-09-29 18:39:16 +00:00
8f7851d2b4
fix rdar://8490728 - llvm-mc rejects gpr64 form of 'movmskpd'
...
llvm-svn: 115029
2010-09-29 05:05:03 +00:00
52e6020883
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382
...
llvm-svn: 115027
2010-09-29 04:55:40 +00:00
5da7f9fcfd
make the x86 mccode emitter emit the 0x67 and 0x66 prefix bytes in the same
...
order as cctools for diffability.
llvm-svn: 115022
2010-09-29 03:43:43 +00:00
a4e1c74947
implement support for 32-bit address operands in 64-bit mode, which
...
are defined to emit the 0x67 prefix byte. rdar://8482675
llvm-svn: 115021
2010-09-29 03:33:25 +00:00
f60062fd55
add basic avx support to the disassembler, also teach it about ssmem/sdmem
...
operands.
With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'
llvm-svn: 115019
2010-09-29 02:57:56 +00:00
ff3a3930a0
add asmparser support for cvttpd2dq by removing some Int_ prefixes.
...
Clean up cvttps2dq by removing some redundant implementations of the
same instruction. rdar://8456382
llvm-svn: 115018
2010-09-29 02:36:32 +00:00
ef1c2fc305
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes.
...
llvm-svn: 115017
2010-09-29 02:24:57 +00:00
a63292a3ca
implement rdar://8456378 and PR7557 - support for the fstsw,
...
an instruction that requires a WHOLE NEW wonderful kind of alias.
llvm-svn: 115015
2010-09-29 01:50:45 +00:00
b44fd24fc1
change the protocol TargetAsmPArser::MatchInstruction method to take an
...
MCStreamer to emit into instead of an MCInst to fill in. This allows the
matcher extra flexibility and is more convenient.
llvm-svn: 115014
2010-09-29 01:42:58 +00:00
786874de82
MMX parameters aren't handled here yet.
...
llvm-svn: 114844
2010-09-27 17:29:47 +00:00
b6a7f97c88
yet more aliases.
...
llvm-svn: 114822
2010-09-27 07:24:57 +00:00
882626cd5b
add a couple more aliases, rdar://8456378
...
llvm-svn: 114821
2010-09-27 07:21:41 +00:00
972c60d821
fix rdar://8470918 - llvm-mc can't assemble smovl
...
llvm-svn: 114819
2010-09-27 07:11:53 +00:00
ff0062af62
Fix rdar://8468087 - llvm-mc commutes fmul (and friend) operands.
...
My previous fix for rdar://8456371 should only apply to fmulp/faddp,
not to fmul/fadd. Instruction set orthogonality is overrated or
something.
llvm-svn: 114818
2010-09-27 07:08:21 +00:00
b5b71e07af
improve indentation
...
llvm-svn: 114815
2010-09-27 06:34:01 +00:00
422e463be7
This code should never fire on non-darwin subtargets.
...
llvm-svn: 114811
2010-09-27 06:01:51 +00:00
4f59cbfb66
implement support for 'clr' alias. This is part of rdar://8416805,
...
but balrog was wanting it on irc.
llvm-svn: 114809
2010-09-27 04:23:03 +00:00
75d65b9a03
Move ELF to HasReliableSymbolDifference=true. Also take the opportunity to put
...
symbols defined in merge sections in independent atoms.
llvm-svn: 114786
2010-09-25 05:42:19 +00:00
6a4cd59b08
We can't return SSE/MMX vectors if SSE is disabled.
...
llvm-svn: 114745
2010-09-24 19:05:48 +00:00
2c5df619c4
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
...
reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
llvm-svn: 114710
2010-09-23 23:45:25 +00:00
bd57e0ce3d
Add isConditionalMove bits to X86 and ARM instructions.
...
llvm-svn: 114703
2010-09-23 22:57:01 +00:00
bbb9287080
Fix PR8201: Update the code to call via X86::CALL64pcrel32 in the 64-bit case.
...
llvm-svn: 114597
2010-09-22 22:35:21 +00:00
c1b3e072f4
Temporarily work around new address lowering while I figure out what
...
needs to happen for darwin.
llvm-svn: 114577
2010-09-22 20:42:08 +00:00
e1223fb583
Attempt to fix llvm-gcc build. It was crashing when building gcov.o for an
...
ARM cross-compiler on x86, because the MMO size did not match the type size.
This fixes the MMO size and also the size of the stack object to match the
type size.
llvm-svn: 114554
2010-09-22 17:35:14 +00:00
415624cf3f
fix rdar://8456371 - Handle commutable instructions written backward.
...
llvm-svn: 114536
2010-09-22 06:26:39 +00:00
bd85725341
Fix an inconsistency in the x86 backend that led it to reject "calll foo" on
...
x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly
named "callq", so this only impacted x86-32.
This fixes rdar://8456370 - llvm-mc rejects 'calll'
This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.
llvm-svn: 114534
2010-09-22 05:49:14 +00:00
37fc469f88
fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8"
...
Teaching the code generator about CR8-15, how to rex them up, etc.
llvm-svn: 114533
2010-09-22 05:29:50 +00:00
9dfd2e354e
add the missing aliases for fp stack cmovs, rdar://8456391
...
llvm-svn: 114531
2010-09-22 04:56:20 +00:00
8a236b63d8
reimplement elf TLS support in terms of addressing modes, eliminating SegmentBaseAddress.
...
llvm-svn: 114529
2010-09-22 04:39:11 +00:00
1261b81e82
Fix rdar://8456364 - llvm-mc rejects '%CS'
...
llvm-svn: 114528
2010-09-22 04:11:10 +00:00
39cf8deded
fix rdar://8456389 - llvm-mc mismatch with 'as' on 'fstp'
...
-This line, and those below, will be ignored--
M test/MC/AsmParser/X86/x86_instructions.s
M lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm-svn: 114527
2010-09-22 04:04:03 +00:00
a91e510f94
fix rdar://8456361 - llvm-mc rejects 'rep movsd'
...
llvm-svn: 114526
2010-09-22 03:50:32 +00:00
a5156c30ed
convert the last 4 X86ISD nodes that should have memoperands to have them.
...
llvm-svn: 114523
2010-09-22 01:28:21 +00:00
ed85da5600
give X86ISD::FNSTCW16m a memoperand, since it touches memory. It only
...
can access the stack due to how it is generated though.
llvm-svn: 114522
2010-09-22 01:11:26 +00:00
78f518b79b
give FP_TO_INT16_IN_MEM and friends a memoperand. They are only
...
used with stack slots, but hey, lets be safe.
llvm-svn: 114521
2010-09-22 01:05:16 +00:00
54e5329545
give VZEXT_LOAD a memory operand, it now works with segment registers.
...
llvm-svn: 114515
2010-09-22 00:34:38 +00:00
07827ba978
revert r114386 now that address modes work correctly, we get a nice
...
call through gs-relative memory now.
llvm-svn: 114510
2010-09-22 00:11:31 +00:00
e479e9643b
give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace 256/257
...
llvm-svn: 114508
2010-09-21 23:59:42 +00:00
d58d7c1907
reimplement support for GS and FS relative address space matching
...
by having X86DAGToDAGISel::SelectAddr get passed in the parent node
of the operand match (the load/store/atomic op) and having it get
the address space from that, instead of having special FS/GS addr
mode operations that require duplicating the entire instruction set
to support.
This makes FS and GS relative accesses *far* more predictable and
work much better. It also simplifies the X86 backend a bit, more
to come.
There is still a pending issue with nodes like ISD::PREFETCH and
X86ISD::FLD, which really should be MemSDNode's but aren't.
llvm-svn: 114491
2010-09-21 22:07:31 +00:00
5e65dfbb97
Reimplement r114460 in target-independent DAGCombine rather than target-dependent, by using
...
the predicate to discover the number of sign bits. Enhance X86's target lowering to provide
a useful response to this query.
llvm-svn: 114473
2010-09-21 20:42:50 +00:00
0e023ea02a
fix a long standing wart: all the ComplexPattern's were being
...
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
llvm-svn: 114471
2010-09-21 20:31:19 +00:00
c6d8839a2b
even though I'm about to rip it out, simplify the address mode stuff
...
llvm-svn: 114468
2010-09-21 19:41:58 +00:00
886250c8f0
convert a couple more places to use the new getStore()
...
llvm-svn: 114463
2010-09-21 18:51:21 +00:00
f4b1a5bdc4
When adding the carry bit to another value on X86, exploit the fact that the carry-materialization
...
(sbbl x, x) sets the registers to 0 or ~0. Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.
This fixes <rdar://problem/8449754>.
llvm-svn: 114460
2010-09-21 18:41:19 +00:00
802527adad
eliminate some uses of the getStore overload.
...
llvm-svn: 114453
2010-09-21 17:50:43 +00:00
3d178ed4d4
propagate MachinePointerInfo through various uses of the old
...
SelectionDAG::getExtLoad overload, and eliminate it.
llvm-svn: 114446
2010-09-21 17:04:51 +00:00
7727d05dbb
convert the targets off the non-MachinePointerInfo of getLoad.
...
llvm-svn: 114410
2010-09-21 06:44:06 +00:00
82fd06d3ce
it's more elegant to put the "getConstantPool" and
...
"getFixedStack" on the MachinePointerInfo class. While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSourceValue, so lets go with it.
llvm-svn: 114406
2010-09-21 06:22:23 +00:00
c3e05d6e50
update the X86 backend to use the MachinePointerInfo version of one
...
of the getLoad methods. This fixes at least one bug where an incorrect
svoffset is passed in (a potential combiner-aa miscompile).
llvm-svn: 114404
2010-09-21 06:02:19 +00:00
4470c2bb23
Fix a bug where the x86 backend would lower memcpy/memset of segment relative operations
...
into non-segment-relative copies.
llvm-svn: 114402
2010-09-21 05:43:34 +00:00
2510de2bea
reimplement memcpy/memmove/memset lowering to use MachinePointerInfo
...
instead of srcvalue/offset pairs. This corrects SV info for mem
operations whose size is > 32-bits.
llvm-svn: 114401
2010-09-21 05:40:29 +00:00
e3d864b857
convert targets to the new MF.getMachineMemOperand interface.
...
llvm-svn: 114391
2010-09-21 04:39:43 +00:00
bb0a1c44bf
fix rdar://8453210, a crash handling a call through a GS relative load.
...
For now, just disable folding the load into the call.
llvm-svn: 114386
2010-09-21 03:37:00 +00:00
ea639aa11f
X86Subtarget.h: Fix Cygwin's TD.
...
llvm-svn: 114297
2010-09-18 19:50:42 +00:00
534db8a5c8
Avoid emitting a PIC base register if no PIC addresses are needed.
...
This fixes rdar://8396318.
llvm-svn: 114201
2010-09-17 20:24:24 +00:00
cea0a8d7ae
fix rdar://8444631 - encoder crash on 'enter'
...
What a weird instruction.
llvm-svn: 114190
2010-09-17 18:02:29 +00:00
74d320db97
fix rdar://8438816 - unrecognized 'fildq' instruction
...
llvm-svn: 114116
2010-09-16 20:46:38 +00:00
ee7e6f42f8
lcall and ljmp always default to lcalll and ljmpl. This finally
...
wraps up r8418316
llvm-svn: 113949
2010-09-15 05:30:20 +00:00
09bfe645f6
apparently jmpl $1,$2 is an alias for ljmpl, similiarly
...
for call. Add this.
llvm-svn: 113948
2010-09-15 05:25:21 +00:00
6757eae45e
Disambiguate lcall/ljmp to the 32-bit version. This happens
...
even in 64-bit mode apparently.
llvm-svn: 113945
2010-09-15 05:14:54 +00:00
5be87c619b
fix the encoding of sldt GR16 to have the 0x66 prefix, and
...
add sldt GR32, which isn't documented in the intel manual
but which gas accepts. Part of rdar://8418316
llvm-svn: 113938
2010-09-15 04:45:10 +00:00
6b40b0def1
implement aliases for shld/shrd, part of rdar://8418316
...
llvm-svn: 113937
2010-09-15 04:37:18 +00:00
4bd21710b6
fix rdar://8431880 - rcl/rcr with no shift amount not recognized
...
llvm-svn: 113936
2010-09-15 04:33:27 +00:00
81ce173860
add various broken forms of fnstsw. I didn't add the %rax
...
version because it adds a prefix and makes even less sense
than the other broken forms. This wraps up rdar://8431422
llvm-svn: 113932
2010-09-15 04:15:16 +00:00
7df35dbd19
add some aliases for f[u]comi, part of rdar://8431422
...
llvm-svn: 113930
2010-09-15 04:08:38 +00:00
4dbcba0082
add a bunch of aliases for fp operations with no operand,
...
rdar://8431422
llvm-svn: 113929
2010-09-15 04:04:33 +00:00
d28452d94a
Diagnose invalid instructions like "incl" with "too few operands for instruction"
...
instead of crashing. This fixes:
rdar://8431815 - crash when invalid operand is one that isn't present
llvm-svn: 113921
2010-09-15 03:50:11 +00:00
95ede4d3b6
trailing whitespace
...
llvm-svn: 113915
2010-09-15 01:01:45 +00:00
5f2311dc29
add a terrible hack to allow out with dx is parens, a gas bug.
...
This fixes PR8114
llvm-svn: 113894
2010-09-14 23:34:29 +00:00
93c9b2ea93
Revert "CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally."
...
This reverts commit r113632
Conflicts:
cmake/modules/AddLLVM.cmake
llvm-svn: 113819
2010-09-13 23:59:48 +00:00
1eea351920
Fix typos. 128-bit PSHUFB takes 128-bit memory op.
...
v8i16 is not an MMX type; put it where it belongs.
llvm-svn: 113785
2010-09-13 21:15:43 +00:00
1094c80281
Added skeleton for inline asm multiple alternative constraint support.
...
llvm-svn: 113766
2010-09-13 18:15:37 +00:00
1bbb14ab8f
add a missed cmov alias, part of rdar://8416805
...
llvm-svn: 113693
2010-09-11 17:08:22 +00:00
3340c3e86c
add support for all the setCC aliases. Part of rdar://8416805
...
llvm-svn: 113692
2010-09-11 17:06:05 +00:00
b47c042e09
add support for pushfd/popfd which are aliases for pushfl/popfl.
...
This fixes rdar://8408129 - pushfd and popfd get invalid instruction mnemonic errors
llvm-svn: 113690
2010-09-11 16:39:16 +00:00
30561aba20
implement rdar://8407928 - support for in/out with a missing "a" register.
...
llvm-svn: 113689
2010-09-11 16:32:12 +00:00
a2a9d16b78
fix the asmparser so that the target is responsible for skipping to
...
the end of the line on a parser error, allowing skipping to happen
for syntactic errors but not for semantic errors. Before we would
miss emitting a diagnostic about the second line, because we skipped
it due to the semantic error on the first line:
foo %eax
bar %al
This fixes rdar://8414033 - llvm-mc ignores lines after an invalid instruction mnemonic errors
llvm-svn: 113688
2010-09-11 16:18:25 +00:00
dc38d36ccb
CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally.
...
llvm-svn: 113632
2010-09-10 21:14:25 +00:00
798725b24d
Reapply r113585. The msvc machine is mercurial.
...
llvm-svn: 113610
2010-09-10 20:20:28 +00:00
a9c9aaa839
r113585 was causing clang-i686-xp-msvc9 to fail in mysterious ways that I can't
...
understand (the log file was no help).
llvm-svn: 113605
2010-09-10 19:20:47 +00:00
638a098f72
Mark the sse_load_f32 and sse_load_f64 load patterns as having memoperands so
...
that the memoperands are properly set after DAG building and general mucking
about.
llvm-svn: 113585
2010-09-10 10:34:22 +00:00
e8501a468c
Add one more pattern to fallback movddup
...
llvm-svn: 113522
2010-09-09 18:48:34 +00:00
3b727f55aa
Make ELF OS ABI dependent on the OS from target triple.
...
llvm-svn: 113508
2010-09-09 17:57:50 +00:00
0ec303b97b
Move remaining MMX instructions from SSE to MMX.
...
llvm-svn: 113501
2010-09-09 17:13:07 +00:00
5f4a6f295c
Move most MMX instructions (defined as anything that
...
uses MMX, even if it also uses other things) from InstrSSE
into InstrMMX. No (intended) functional change.
llvm-svn: 113462
2010-09-09 01:02:39 +00:00
28a9c2f89a
fix rdar://8407548, I missed the commuted form of xchg/test without a suffix.
...
llvm-svn: 113427
2010-09-08 22:27:05 +00:00
d7aba234c2
fix wonky formatting.
...
llvm-svn: 113426
2010-09-08 22:22:10 +00:00
8ead237758
fix bugs in push/pop segment support, rdar://8407242
...
llvm-svn: 113422
2010-09-08 22:13:08 +00:00
0d2e6ad504
Add intrinsic-based patterns for MMX PINSRW and PEXTRW.
...
llvm-svn: 113420
2010-09-08 22:08:40 +00:00
e54dba94f9
Check in forgotten file. Should fix build.
...
llvm-svn: 113409
2010-09-08 21:09:48 +00:00
4dae01781f
Slight cleanup, use only one form of MMXI_binop_rm_int.
...
llvm-svn: 113406
2010-09-08 20:54:00 +00:00
d79bb127dd
Add intrinsic forms of mmx<->sse conversions. Notes:
...
Omission of memory form of PI2PD is intentional; this
does not use an MMX register and does not put the chip
into MMX mode (PI2PS, oddly enough, does).
Operands of PI2PS follow the gcc builtin, not Intel.
llvm-svn: 113388
2010-09-08 19:15:38 +00:00
99a9f4661a
Minor change. Fix comments and remove unused and redundant code
...
llvm-svn: 113378
2010-09-08 18:12:31 +00:00
f7fee1c185
x86 vector shuffle lowering now relies only on target specific
...
nodes to emit shuffles and don't do isel mask matching anymore.
- Add the selection of the remaining shuffle opcode (movddup)
- Introduce two new functions to "recognize" where we may get
potential folds and add several comments to them explaining why
they are not yet in the desidered shape.
- Add more patterns to fallback the case where we select
a specific shuffle opcode as if it could fold a load, but it
can't, so remap to a valid instruction.
- Add a couple of FIXMEs to address in the following days once
there's a good solution to the current folding problem.
llvm-svn: 113369
2010-09-08 17:43:25 +00:00
2907d2e419
add support for the commuted form of the test instruction, rdar://8018260.
...
llvm-svn: 113352
2010-09-08 05:51:12 +00:00
a9ca7837e4
implement proper support for sysret{,l,q}, rdar://8403907
...
llvm-svn: 113350
2010-09-08 05:45:34 +00:00
063363fa80
implement the iret suite of instructions properly,
...
fixing rdar://8403974
llvm-svn: 113349
2010-09-08 05:38:31 +00:00
086a83afb1
add support for instruction prefixes on the same line as the instruction,
...
implementing rdar://8033482 and PR7254.
llvm-svn: 113348
2010-09-08 05:17:37 +00:00
91689c1d0f
change the MC "ParseInstruction" interface to make it the
...
implementation's job to check for and lex the EndOfStatement
marker.
llvm-svn: 113347
2010-09-08 05:10:46 +00:00
8caea68a4f
gas accepts xchg <mem>, <reg> as a synonym for xchg <reg>, <mem>.
...
Add this to the mc assembler, fixing PR8061
llvm-svn: 113346
2010-09-08 04:53:27 +00:00
4703cb4a96
fix the encoding of the "jump on *cx" family of instructions,
...
rdar://8061602
llvm-svn: 113343
2010-09-08 04:30:51 +00:00
6b1d62c529
Factor out some x86 vector shuffle rewriting and add comments about the direction the shuffle lowering is heading to
...
llvm-svn: 113286
2010-09-07 21:03:14 +00:00
7c483028fb
Move code around to prepare for moving some of the logic together to another function
...
llvm-svn: 113267
2010-09-07 20:20:27 +00:00
353802114f
Add an MVT::x86mmx type. It will take the place of all current MMX vector types.
...
llvm-svn: 113261
2010-09-07 20:03:56 +00:00
5444b36e01
Remove a dead comment.
...
llvm-svn: 113259
2010-09-07 20:01:10 +00:00
5a45db3e6c
decouple MMX check from regular splat checks. Some refactoring is coming, and MMX should be left alone to be easily removed after moving to intrinsics
...
llvm-svn: 113247
2010-09-07 18:41:45 +00:00
4f5d4b4a6e
Remove now useless check, because the code can be matched below, no need to leave it for isel
...
llvm-svn: 113242
2010-09-07 18:29:03 +00:00
c9b3316fea
Minor change. Since the checks are equivalent, use isMMX
...
llvm-svn: 113239
2010-09-07 18:24:00 +00:00
605acfe533
Add patterns for MMX that use the new intrinsics.
...
Enable palignr intrinsic.
These may need adjustment for a new VT in due course.
llvm-svn: 113233
2010-09-07 18:10:56 +00:00
f0ea222255
Remove unused target specific node
...
llvm-svn: 113224
2010-09-07 17:38:55 +00:00
1ecb978214
Don't leak the old operand when transforming "sldt" into "sldtw".
...
llvm-svn: 113200
2010-09-07 14:40:58 +00:00
30bb384944
add missing cmov aliases, this resolves rdar://8208499
...
llvm-svn: 113189
2010-09-07 00:05:45 +00:00
3ae9398d5f
remove duplicated entry
...
llvm-svn: 113188
2010-09-06 23:57:24 +00:00
7ece716da2
"sldt <mem>" is ambiguous in 64-bit mode, but should
...
always be disambiguated as sldtw. sldtw and sldtq with
a mem operands have the same effect, but sldtw is more
compact. Force it to sldtw, resolving rdar://8017530
llvm-svn: 113186
2010-09-06 23:51:44 +00:00
415e04fad2
fix rdar://8017621 - llvm-mc can't guess encoding for "push $(1000)"
...
llvm-svn: 113184
2010-09-06 23:40:56 +00:00
34e366b45c
fix the operand constraints of the immediate form of in/out,
...
allowing unsigned 8-bit operands. This fixes rdar://8208481
llvm-svn: 113182
2010-09-06 23:29:05 +00:00
339cc7bfef
in the case where an instruction only has one implementation
...
of a mneumonic, report operand errors with better location
info. For example, we now report:
t.s:6:14: error: invalid operand for instruction
cwtl $1
^
but we fail for common cases like:
t.s:11:4: error: invalid operand for instruction
addl $1, $1
^
because we don't know if this is supposed to be the reg/imm or imm/reg
form.
llvm-svn: 113178
2010-09-06 22:11:18 +00:00
628fbecf4f
Now that we know if we had a total fail on the instruction mnemonic,
...
give a more detailed error. Before:
t.s:11:4: error: unrecognized instruction
addl $1, $1
^
t.s:12:4: error: unrecognized instruction
f2efqefa $1
^
After:
t.s:11:4: error: invalid operand for instruction
addl $1, $1
^
t.s:12:4: error: invalid instruction mnemonic 'f2efqefa'
f2efqefa $1
^
This fixes rdar://8017912 - llvm-mc says "unrecognized instruction" when it means "invalid operands"
llvm-svn: 113176
2010-09-06 21:54:15 +00:00
31c63fb518
simplify the hacks around jrcxz.
...
llvm-svn: 113167
2010-09-06 20:10:12 +00:00
b4be28f33d
have tblgen detect when an instruction would have matched, but
...
failed because a subtarget feature was not enabled. Use this to
remove a bunch of hacks from the X86AsmParser for rejecting things
like popfl in 64-bit mode. Previously these hacks weren't needed,
but were important to get a message better than "invalid instruction"
when used in the wrong mode.
This also fixes bugs where pushal would not be rejected correctly in
32-bit mode (just pusha).
llvm-svn: 113166
2010-09-06 20:08:02 +00:00
a22a368e7c
change MatchInstructionImpl to return an enum instead of bool.
...
llvm-svn: 113165
2010-09-06 19:22:17 +00:00
3e4582ada5
have AsmMatcherEmitter.cpp produce the hunk of code that gets included
...
into the middle of the class, and rework how the different sections of
the generated file are conditionally included for simplicity.
llvm-svn: 113163
2010-09-06 19:11:01 +00:00
e1278b57f9
Redefine LOOP* instructions from I to Ii8PCRel as they take an i8 argument.
...
llvm-svn: 113158
2010-09-06 18:43:14 +00:00
4cfbcdc7b6
random cleanups
...
llvm-svn: 113157
2010-09-06 18:32:06 +00:00
5cac0f71ca
update this.
...
llvm-svn: 113116
2010-09-05 20:22:09 +00:00
eeba0c73e5
implement rdar://6653118 - fastisel should fold loads where possible.
...
Since mem2reg isn't run at -O0, we get a ton of reloads from the stack,
for example, before, this code:
int foo(int x, int y, int z) {
return x+y+z;
}
used to compile into:
_foo: ## @foo
subq $12, %rsp
movl %edi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movl 8(%rsp), %edx
movl 4(%rsp), %esi
addl %edx, %esi
movl (%rsp), %edx
addl %esi, %edx
movl %edx, %eax
addq $12, %rsp
ret
Now we produce:
_foo: ## @foo
subq $12, %rsp
movl %edi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movl 8(%rsp), %edx
addl 4(%rsp), %edx ## Folded load
addl (%rsp), %edx ## Folded load
movl %edx, %eax
addq $12, %rsp
ret
Fewer instructions and less register use = faster compiles.
llvm-svn: 113102
2010-09-05 02:18:34 +00:00
65b48b5dfc
zap dead code.
...
llvm-svn: 113073
2010-09-04 18:12:00 +00:00
c6accda78e
Remove the last bit of isShuffleMaskLegal checks and improve the comment regarding mmx shuffles
...
llvm-svn: 113059
2010-09-04 02:58:56 +00:00
731bcc1abf
make explicit that we not handle several mmx shuffles
...
llvm-svn: 113058
2010-09-04 02:50:13 +00:00
20779ee157
Emit target specific nodes to handle palignr. Do not touch it for MMX versions yet.
...
llvm-svn: 113056
2010-09-04 02:36:07 +00:00
cff7cd18ab
Emit target specific nodes to handle splats starting at zero indicies
...
llvm-svn: 113055
2010-09-04 02:02:14 +00:00
95759917eb
Emit target specific nodes for isPSHUFHWMask and isPSHUFLWMask
...
llvm-svn: 113050
2010-09-04 01:36:45 +00:00
2b57008c72
Emit target specific nodes for isSHUFPMask
...
llvm-svn: 113048
2010-09-04 01:22:57 +00:00
2f7af36134
Previous isMOVLMask matching already emits targets nodes, remove check
...
llvm-svn: 113047
2010-09-04 00:50:08 +00:00
9f8e704151
One more check from the original isShuffleMaskLegal goes away
...
llvm-svn: 113045
2010-09-04 00:46:16 +00:00
16959372bb
Remove a duplicated but useless check that i've inserted in the previous commit.
...
llvm-svn: 113044
2010-09-04 00:43:12 +00:00
44578d38d3
Refactor some code and remove the extra checks for unpckl_undef and unpckh_undef
...
llvm-svn: 113043
2010-09-04 00:39:43 +00:00
7829d0e74b
Remove check for unpckh mask
...
llvm-svn: 113035
2010-09-03 23:32:47 +00:00
d1dacc57aa
Remove check for unpckl mask
...
llvm-svn: 113034
2010-09-03 23:31:50 +00:00
207b9d6218
Inline isShuffleMaskLegal into LowerVECTOR_SHUFFLE, so we can start
...
checking each standalone condition and decide whether emit target
specific nodes or remove the condition if it's already matched before.
llvm-svn: 113031
2010-09-03 23:24:06 +00:00
2bef20eda7
Reapply considered harmfull part of rr112934 and r112942.
...
"Use target specific nodes instead of relying in unpckl and
unpckh pattern fragments during isel time. Also place a
depth limit in getShuffleScalarElt.
llvm-svn: 113020
2010-09-03 22:09:41 +00:00
367afb5a00
Remove the rest of the nonexistent 64-bit AVX instructions.
...
Bruno, please review.
llvm-svn: 113014
2010-09-03 21:23:00 +00:00
a750d994fe
Reapply last harmless part of r112934, the pattern fragment to match X86Unpcklpd
...
llvm-svn: 113009
2010-09-03 20:44:26 +00:00
fe8717c573
Reintroduce a simple function refactoring done in r112934, also without any functionality changes
...
llvm-svn: 113008
2010-09-03 20:20:02 +00:00
48e589b122
Reapply piecies of r112942 and r112934 which don't do
...
functional changes
llvm-svn: 113007
2010-09-03 20:10:35 +00:00
6979cf0808
Reapply Fix comment
...
llvm-svn: 113006
2010-09-03 19:55:05 +00:00
6f3da24d70
Revert r112934, "- Use specific nodes to match unpckl masks.", which introduced
...
some infinite loop and select failures.
- Apologies for eager reverting, but its branch day.
llvm-svn: 113000
2010-09-03 19:38:11 +00:00
f1aacd55c0
Revert r112938 "Fix comment", which depends on r112934, which introduced some
...
infinite loop and select failures.
llvm-svn: 112999
2010-09-03 19:38:08 +00:00
0ffe4db45c
Revert r112942, "Use punpckh and unpckh family of nodes instead of using unpckh
...
mask pattern fragment", which depends on r112934, which introduced some infinite
loop and select failures.
llvm-svn: 112998
2010-09-03 19:38:05 +00:00
d6634a5b2e
AVX doesn't support mm operations neither its instrinsics.
...
The AVX versions of PALIGN and PABS* should only exist for
128-bit. Remove the unnecessary stuff.
llvm-svn: 112944
2010-09-03 02:08:45 +00:00
a85ec10483
Use punpckh and unpckh family of nodes instead of using unpckh mask pattern fragment
...
llvm-svn: 112942
2010-09-03 01:39:08 +00:00
adc6bca2dd
Fix comment
...
llvm-svn: 112938
2010-09-03 01:28:51 +00:00
cce44678b4
- Use specific nodes to match unpckl masks.
...
- Teach getShuffleScalarElt how to handle more target
specific nodes, so the DAGCombine can make use of it.
- Add another hack to avoid the node update problem
during legalization. More description on the comments
llvm-svn: 112934
2010-09-03 01:24:00 +00:00
08aede2538
Don't call Predicate_* from X86 target.
...
llvm-svn: 112921
2010-09-03 00:35:18 +00:00
a5a645559c
Properly emit __chkstk call instead of __alloca on non-mingw windows targets.
...
Patch by Cameron Esfahani!
llvm-svn: 112902
2010-09-02 23:03:46 +00:00
02a05a6a89
Move insertps mask decoding to header file
...
llvm-svn: 112896
2010-09-02 22:43:39 +00:00
a689c5b2c0
Revert win64 changes. They seem to be incomplete
...
llvm-svn: 112885
2010-09-02 22:31:32 +00:00
56291f7e53
Properly allocate win64 shadow reg area.
...
Patch by Jan Sjodin!
llvm-svn: 112875
2010-09-02 22:16:28 +00:00
814a69c330
Move decoding of insertps back to avoid unused warnings in x86 isel lowering, and fix movlhps/movhlps to decode 4 elements shuffles
...
llvm-svn: 112869
2010-09-02 21:51:11 +00:00
3c9b5f394b
Don't narrow the load and store in a load+twiddle+store sequence unless
...
there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.
This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.
llvm-svn: 112861
2010-09-02 21:18:42 +00:00
c79f50170a
Move x86 specific shuffle mask decoding to its own header, it's also going to be used elsewhere. Also trim trailing whitespaces
...
llvm-svn: 112846
2010-09-02 18:40:13 +00:00
489613f1e5
Replace unpckl_undef and unpckh_undef matching with target specific opcodes
...
llvm-svn: 112806
2010-09-02 05:23:12 +00:00
e4e4be3885
Move condition out to prepare for more matching
...
llvm-svn: 112805
2010-09-02 04:20:26 +00:00
bf7fd146c7
Remove checking for isUNPCKL_v_undef_Mask, the specific node is already emitted for it
...
llvm-svn: 112804
2010-09-02 03:57:58 +00:00
6a7f634487
become more strict about when it's safe to use X86ISD::MOVLPS
...
llvm-svn: 112799
2010-09-02 02:35:51 +00:00
04c25c15c7
Revert r112689, avoid those kind of checks cause they mess up with mmx
...
llvm-svn: 112760
2010-09-01 22:59:03 +00:00
fea81b4831
Using target specific nodes for shuffle nodes makes the mask
...
check more strict, breaking some cases not checked in the
testsuite, but also exposes some foldings not done before,
as this example:
movaps (%rdi), %xmm0
movaps (%rax), %xmm1
movaps %xmm0, %xmm2
movss %xmm1, %xmm2
shufps $36, %xmm2, %xmm0
now is generated as:
movaps (%rdi), %xmm0
movaps %xmm0, %xmm1
movlps (%rax), %xmm1
shufps $36, %xmm1, %xmm0
llvm-svn: 112753
2010-09-01 22:33:20 +00:00
b3825216ce
Use movlps, movlpd, movss and movsd specific nodes instead of pattern matching with movlp pattern fragment
...
llvm-svn: 112694
2010-09-01 05:08:25 +00:00
6aaebe877b
minor change, simplify some logic
...
llvm-svn: 112689
2010-09-01 00:57:08 +00:00
2b025707a2
Move some functions around so they can be used for some other to come function
...
llvm-svn: 112687
2010-09-01 00:51:36 +00:00
4b56d87290
Use x86 specific MOVSLDUP node, add more patterns to match it and remove useless load nodes
...
llvm-svn: 112661
2010-08-31 22:35:05 +00:00
61996ef835
Use x86 specific MOVSHDUP node and add more patterns to match it
...
llvm-svn: 112657
2010-08-31 22:22:11 +00:00
33e9fce2d6
Make %EFLAGS unallocatable.
...
No CCR virtual registers should exist, and %EFLAGS is used in ways that can
surprise RegAllocFast.
llvm-svn: 112650
2010-08-31 21:51:07 +00:00
5de15ce468
Use MOVHLPS node instead of matching using movhlps and movhlps_undef pattern fragments
...
llvm-svn: 112644
2010-08-31 21:38:49 +00:00
03e4c35302
Use MOVLHPS and MOVHLPS x86 nodes whenever possible. Also remove some useless nodes
...
llvm-svn: 112642
2010-08-31 21:15:21 +00:00
dfd9dd5d75
Use X86ISD::MOVSS and MOVSD to represent the movl mask pattern, also fix the handling of those nodes when seeking for scalars inside vector shuffles
...
llvm-svn: 112570
2010-08-31 02:26:40 +00:00
f75de6eae7
A couple of small missed optimizations.
...
llvm-svn: 112411
2010-08-29 05:07:40 +00:00
38ccc8b884
add a bunch more common shuffles to the instprinter.
...
llvm-svn: 112397
2010-08-29 03:08:08 +00:00
7a05e6dca2
I have manually decoded the imm field of an insertps one too many
...
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
llvm-svn: 112387
2010-08-28 20:42:31 +00:00
94656b1c8c
fix the buildvector->insertp[sd] logic to not always create a redundant
...
insertp[sd] $0, which is a noop. Before:
_f32: ## @f32
pshufd $1, %xmm1, %xmm2
pshufd $1, %xmm0, %xmm3
addss %xmm2, %xmm3
addss %xmm1, %xmm0
## kill: XMM0<def> XMM0<kill> XMM0<def>
insertps $0, %xmm0, %xmm0
insertps $16, %xmm3, %xmm0
ret
after:
_f32: ## @f32
movdqa %xmm0, %xmm2
addss %xmm1, %xmm2
pshufd $1, %xmm1, %xmm1
pshufd $1, %xmm0, %xmm3
addss %xmm1, %xmm3
movdqa %xmm2, %xmm0
insertps $16, %xmm3, %xmm0
ret
The extra movs are due to a random (poor) scheduling decision.
llvm-svn: 112379
2010-08-28 17:59:08 +00:00
bcb6090ad0
fix the BuildVector -> unpcklps logic to not do pointless shuffles
...
when the top elements of a vector are undefined. This happens all
the time for X86-64 ABI stuff because only the low 2 elements of
a 4 element vector are defined. For example, on:
_Complex float f32(_Complex float A, _Complex float B) {
return A+B;
}
We used to produce (with SSE2, SSE4.1+ uses insertps):
_f32: ## @f32
movdqa %xmm0, %xmm2
addss %xmm1, %xmm2
pshufd $16, %xmm2, %xmm2
pshufd $1, %xmm1, %xmm1
pshufd $1, %xmm0, %xmm0
addss %xmm1, %xmm0
pshufd $16, %xmm0, %xmm1
movdqa %xmm2, %xmm0
unpcklps %xmm1, %xmm0
ret
We now produce:
_f32: ## @f32
movdqa %xmm0, %xmm2
addss %xmm1, %xmm2
pshufd $1, %xmm1, %xmm1
pshufd $1, %xmm0, %xmm3
addss %xmm1, %xmm3
movaps %xmm2, %xmm0
unpcklps %xmm3, %xmm0
ret
This implements rdar://8368414
llvm-svn: 112378
2010-08-28 17:28:30 +00:00
96db6e66f4
improve comments in the unpcklps generating logic, introduce
...
a new EltStride variable instead of reusing NumElems variable
for a non-obvious purpose. No functionality change.
llvm-svn: 112377
2010-08-28 17:15:43 +00:00
a982aa24ef
Clean up the logic of vector shuffles -> vector shifts.
...
Also teach this logic how to handle target specific shuffles if
needed, this is necessary while searching recursively for zeroed
scalar elements in vector shuffle operands.
llvm-svn: 112348
2010-08-28 02:46:39 +00:00
c0b36921c2
Properly handle passing of FP stuff to varargs function on Win64:
...
value should be copied to the corresponding shadow reg as well.
Patch by Cameron Esfahani!
llvm-svn: 112262
2010-08-27 14:43:06 +00:00
1844a71e66
X86: Fix an encoding issue with LOCK_ADD64mr, which could lead to very hard to find miscompiles with the integrated assembler.
...
llvm-svn: 112250
2010-08-27 01:30:14 +00:00
6a77066913
Simplify eliminateFrameIndex() interface back down now that PEI doesn't need
...
to try to re-use scavenged frame index reference registers. rdar://8277890
llvm-svn: 112241
2010-08-26 23:32:16 +00:00
e25ba0c7c2
zap the now unused MVT::getIntVectorWithNumElements
...
llvm-svn: 112218
2010-08-26 20:53:12 +00:00
a967c42a3d
Fix comment typos.
...
llvm-svn: 112202
2010-08-26 18:08:11 +00:00
eb2cc0ce0e
implement SplitVecOp_CONCAT_VECTORS, fixing the included testcase with SSE1.
...
llvm-svn: 112171
2010-08-26 05:51:22 +00:00
cc60609cb4
fix sse1 only codegen in x86-64 mode, which is something we
...
apparently try to support.
llvm-svn: 112168
2010-08-26 05:24:29 +00:00
184eaea855
Fix PR7748 without using microsoft extensions
...
llvm-svn: 112128
2010-08-26 01:02:53 +00:00
aecf47a5cb
we should pattern match the SSE complex arithmetic ops.
...
llvm-svn: 112109
2010-08-25 23:31:42 +00:00
d4085f6e91
Revert this for now, PUNPCKLDQ dont operate on v4f32
...
llvm-svn: 112090
2010-08-25 21:26:37 +00:00
3d148ac089
X86: Fix misencode of RI64mi8. This fixes OpenSSL / x86_64-apple-darwin10 / clang -O3.
...
llvm-svn: 112089
2010-08-25 21:11:02 +00:00
f1f2133ac0
Remove dead recursive function. Yay for clang -Wunused-function.
...
llvm-svn: 112060
2010-08-25 17:27:58 +00:00
b3b53ecac0
Fix nasty mingw32 bug, which e.g. prevented llvm-gcc bootstrap there.
...
Mark _alloca call as clobberring EFLAGS, otherwise some DCE might remove
other flags-clobberring stuff (e.g. cmp instructions) occuring after
_alloca call.
llvm-svn: 112034
2010-08-25 07:50:11 +00:00
0770d25758
PUNPCKLDQ should also be used for v4f32
...
llvm-svn: 112020
2010-08-25 02:55:40 +00:00
2e45d522c1
teach lowering to get target specific nodes for pshufd, emulating the same isel behavior for now, so we can pass all vector shuffle tests
...
llvm-svn: 112017
2010-08-25 02:35:37 +00:00
1c8d777c93
MC/X86: Tweak imul recognition, previous hack only applies for the imul form
...
taking immediates.
llvm-svn: 111950
2010-08-24 19:37:56 +00:00
09392785b4
MC/X86: Add custom hack for recognizing "imul $12, %eax" and friends.
...
llvm-svn: 111947
2010-08-24 19:24:18 +00:00
94b84a19b9
MC/X86: Warn on scale factors > 1 without index register, instead of erroring,
...
for 'as' compatibility.
llvm-svn: 111945
2010-08-24 19:13:38 +00:00
c88fda477a
Fix X86's isLegalAddressingMode to recognize that static addresses
...
need not be RIP-relative in small mode.
llvm-svn: 111917
2010-08-24 15:55:12 +00:00
758d7b1f5c
Use pshufhw and pshuflw in more cases and fix getTargetShuffleNode number of arguments
...
llvm-svn: 111890
2010-08-24 01:16:15 +00:00
264d90fff7
Start using target speficic nodes for shuffles: pshufhw and pshuflw
...
llvm-svn: 111837
2010-08-23 20:41:02 +00:00
21fed6616c
tyops
...
llvm-svn: 111835
2010-08-23 20:30:51 +00:00
58bd73a5a7
Add a new llvm.x86.int intrinsic, allowing access to the
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x86 int and int3 instructions. Patch by Peter Housel!
llvm-svn: 111831
2010-08-23 19:39:25 +00:00
a42202e0e4
random improvement for variable shift codegen.
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llvm-svn: 111813
2010-08-23 17:30:29 +00:00
cbbe4501df
Revert invalid r111792. Jump tables are not broken on x86-64 / coff,
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it's COFF emitter which does not support differences of two symbols
(and needs to be fixed). GAS is pretty fine with code produced.
llvm-svn: 111801
2010-08-23 07:38:51 +00:00
e87231232a
Workaround broken jump tables on x86-64 COFF.
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llvm-svn: 111792
2010-08-23 04:45:37 +00:00
db9820ecaa
Use rip-rel addressing on win64 by default. For this we just
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defaults to small pic code model.
llvm-svn: 111741
2010-08-21 17:21:11 +00:00
377aa20e6e
MC: Add partial x86-64 support to COFF.
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llvm-svn: 111728
2010-08-21 05:58:13 +00:00
42ef669d81
Fix x86 fast-isel's cmp+branch folding to avoid folding when the
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comparison is in a different basic block from the branch. In such
cases, the comparison's operands may not have initialized virtual
registers available.
llvm-svn: 111709
2010-08-21 02:32:36 +00:00
9f20e7a1bf
Prepare LowerVECTOR_SHUFFLEv8i16 to use x86 target specific nodes directly
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llvm-svn: 111704
2010-08-21 01:32:18 +00:00
6f3b38a851
This is the first step towards refactoring the x86 vector shuffle code. The
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general idea here is to have a group of x86 target specific nodes which are
going to be selected during lowering and then directly matched in isel.
The commit includes the addition of those specific nodes and a *bunch* of
patterns, and incrementally we're going to switch between them and what we
have right now. Both the patterns and target specific nodes can change as
we move forward with this work.
llvm-svn: 111691
2010-08-20 22:55:05 +00:00
f547740d3f
fix PR7465, mishandling of lcall and ljmp: intersegment long
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call and jumps.
llvm-svn: 111496
2010-08-19 01:18:43 +00:00
beb506eeed
minor progress towards fixing PR7465
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llvm-svn: 111494
2010-08-19 01:00:34 +00:00
817e857b13
Marked with ATTRIBUTE_USED so that clang doesn't complain.
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llvm-svn: 111383
2010-08-18 18:40:57 +00:00
3e3e63efe1
remove some code that is dead now that lea's are modeled with segment registers.
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llvm-svn: 111343
2010-08-18 02:40:44 +00:00
88c09879c7
Revert part of one of the prev. patches - tailjmp will follow later.
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llvm-svn: 111291
2010-08-17 21:08:28 +00:00
231ab847ca
More fixes for win64:
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- Do not clobber al during variadic calls, this is AMD64 ABI-only feature
- Emit wincall64, where necessary
Patch by Cameron Esfahani!
llvm-svn: 111289
2010-08-17 21:06:07 +00:00
cd78af6e3c
Enable more win64 calls folding opportunities.
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Patch by Cameron Esfahani!
llvm-svn: 111288
2010-08-17 21:06:01 +00:00
2444da0652
Comment out some broken/unused/useless instructions which mess up disassembly.
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llvm-svn: 111185
2010-08-16 21:18:51 +00:00
51ec745509
Don't attempt to SimplifyShortMoveForm in 64-bit mode.
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llvm-svn: 111182
2010-08-16 21:03:32 +00:00
f751d856f0
Hookup ELF support for X86.
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llvm-svn: 111173
2010-08-16 18:36:14 +00:00
2cd00737c0
Partially revert r111155. It looks like MSVC is calling an operator<() that
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clang says is unused.
llvm-svn: 111167
2010-08-16 18:24:54 +00:00
b7f872197a
Remove unused functions.
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llvm-svn: 111155
2010-08-16 17:18:18 +00:00
d0fcc9a818
Revert r111082. No warnings for this common pattern.
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llvm-svn: 111102
2010-08-15 10:27:23 +00:00
54194bd127
Rework how the non-sse2 memory barrier is lowered so that the
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encoding is correct for the built-in assembler.
Based on a patch from Chris.
llvm-svn: 111083
2010-08-14 21:51:50 +00:00
7c09ddf0ae
Add ATTRIBUTE_UNUSED to methods that are not supposed to be used.
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llvm-svn: 111082
2010-08-14 21:35:10 +00:00
2f6c3434ac
improve indentation
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llvm-svn: 111073
2010-08-14 17:26:09 +00:00
160be2936b
Add comments to some pattern fragments in x86
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llvm-svn: 111041
2010-08-13 20:39:01 +00:00
8d3c89e765
Revert 110491. While not wrong, it was based on a
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misanalysis and is undesirable.
llvm-svn: 111028
2010-08-13 18:43:45 +00:00
081861b6b7
Fix comment to reflect code, and remove an unused argument
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llvm-svn: 111022
2010-08-13 17:50:47 +00:00
1187e3f09b
Improve comment to make explicit why not to touch this could before JIT goes MC
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llvm-svn: 111021
2010-08-13 17:44:10 +00:00
6e5b67ccc4
Revert last patch and r110954 as I meant to.
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llvm-svn: 111001
2010-08-13 02:37:50 +00:00
5e027fe113
Revert r110954 for now, pseudo instructions can't make it through to the JIT.
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llvm-svn: 111000
2010-08-13 02:30:00 +00:00
cc20fe5937
Some small clean-up: use of pseudo instructions
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llvm-svn: 110954
2010-08-12 20:55:18 +00:00
7f704b31a9
- Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary.
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- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.
llvm-svn: 110946
2010-08-12 20:20:53 +00:00
Jim Grosbach